void BB::allocateTempRegisters(BitVector** hardwired, PRegBList* tempRegs,
BitVectorBList* lives) {
if (!nnodes) return; // empty BB
RegisterEqClassBList regClasses(nnodes + 1);
regClasses.append(NULL); // first reg class has index 1
fint use_count[NumRegisters], def_count[NumRegisters];
for (fint i = 0; i < NumRegisters; i++) use_count[i] = def_count[i] = 0;
allocate_to_preferred_candidates_if_possible(use_count, def_count);
// allocate other temp regs (using the untouched temp regs of this BB)
fint temp = 0;
for (int i = 0; i < duInfo.info->length(); i++) {
// collect temp regs
PReg* r = duInfo.info->nth(i)->reg;
if (r->loc == UnAllocated && !r->isUnused() && r->isLocalTo(this)) {
assert(r->dus.first()->index == i, "should be the same");
for ( ; temp < NumTempRegs &&
use_count[TempRegs[temp]] + def_count[TempRegs[temp]] > 0;
temp++) ;
if (temp == NumTempRegs) break; // ran out of regs
// ok, allocate TempRegs[temp] to the preg and equivalent pregs
Location t = TempRegs[temp++];
PReg* frst = r->regClass ? regClasses.nth(r->regClass)->first : r;
for (PReg* pr = frst; pr; pr = pr->regClassLink) {
doAlloc(pr, t);
pr->regClass = 0;
}
}
r->regClass = 0;
}
if (temp == NumTempRegs) {
// ran out of temp regs with the simple strategy - try using slow
// allocation algorithm
slowAllocateTempRegisters(hardwired, tempRegs, lives);
}
}
void BB::pick_candidates_for_assignment_node(Node* n, fint use_count[], fint def_count[],
RegCandidateBList &cands) {
PReg* src = n->src();
PReg* dest = n->dest();
bool localSrc = src ->isLocalTo(this);
bool localDest = dest->isLocalTo(this);
if ( isRegister(src->loc)) {
if (dest->loc == UnAllocated && localDest) {
// PR = PR2(reg)
// allocate dest->loc to src->loc, but only if src->loc
// isn't defined again
cands.append(new RegCandidate(dest, src->loc, def_count[src->loc]));
}
} else if ( isRegister(dest->loc)) {
if (src->loc == UnAllocated && localSrc) {
// PR2(reg) = PR
// should allocate src->loc to dest->loc, but only if dest->loc
// has single definition (this one) and isn't used before
// this point [simplification]
if (def_count[dest->loc] != 1 || use_count[dest->loc]) {
// not eligible for special treatment
} else {
cands.append(new RegCandidate(src, dest->loc, 1));
}
}
} else if (localSrc && localDest) {
// both regs are local and unallocated - put them in same
// equivalence class
// fix this - should check for overlapping live ranges
// needed to say "if nonoverlapping live ranges(src, dest)"
// src->makeSameRegClass(dest, ®Classes);
// if (WizardMode) warning("basicBlock: happens");
} else {
// non-local registers - skip
}
}
// allocate PRegs that are used & defined solely within this BB
void BB::slowAllocateTempRegisters(BitVector** hardwired, PRegBList* tempRegs,
BitVectorBList* lives) {
// clear temporary data structures
tempRegs->clear();
lives->clear();
fint i;
for (i = 0; i < NumTempRegs; i++) {
hardwired[i]->setLength(nnodes);
hardwired[i]->clear();
}
for (i = 0; i < duInfo.info->length(); i++) {
// collect temp regs and hardwired temp regs
PReg* r = duInfo.info->nth(i)->reg;
if (r->isLocalTo(this)) {
assert(r->dus.first()->index == i, "should be the same");
if (r->isUnused()) {
// unused register - ignore
} else {
DUInfo* info = duInfo.info->nth(r->dus.first()->index);
tempRegs->append(r);
BitVector* bv = new BitVector(nnodes);
lives->append(bv);
fint firstUse = 0, lastUse = nnodes - 1;
duInfo.info->nth(i)->getLiveRange(firstUse, lastUse);
bv->addFromTo(firstUse, lastUse);
}
} else if (isTempReg(r->loc)) {
fint firstUse = 0, lastUse = nnodes - 1;
if (!r->incorrectDU()) {
duInfo.info->nth(i)->getLiveRange(firstUse, lastUse);
} else {
// can't really compute live range since the temp might be non-local
// so assume it's live from first node til the end
}
hardwired[RegToTempNo[r->loc]]->addFromTo(firstUse, lastUse);
}
}
// now, tempRegs holds all temp regs, and lives contains each register's
// live range (one bit per node, 1 = reg is live); hardwired contains
// the ranges where temp regs are already taken (e.g. for NLR, calls, etc)
// cycle through the temp registers to (hopefully) allow more optimizations
// later (e.g. scheduling)
fint lastTemp = 0;
# define nextTemp(n) (n == NumTempRegs - 1) ? 0 : n + 1
for (i = 0; i < tempRegs->length(); i++) {
// try to allocate tempRegs[i] to a temp register
PReg* r = tempRegs->nth(i);
if (r->loc != UnAllocated) {
assert(r->regClass == 0, "should have been cleared");
continue;
}
BitVector* liveRange = lives->nth(i);
for (fint tempNo = lastTemp, ntries = 0; ntries < NumTempRegs;
tempNo = nextTemp(tempNo), ntries++) {
if (liveRange->isDisjointFrom(hardwired[tempNo])) {
Location temp = TempRegs[tempNo];
doAlloc(r, temp);
hardwired[tempNo]->unionWith(liveRange);
lastTemp = nextTemp(tempNo);
break;
}
}
if ( r->loc == UnAllocated
&& (PrintSICTempRegisterAllocation
|| WizardMode && TARGET_ARCH != I386_ARCH /* happens normally in I386; few regs */ )) {
lprintf("*could NOT find temp assignment for local %s in BB%ld\n",
r->name(), (void*)id());
} else if (r->loc == UnAllocated) {
if (PrintSICTempRegisterAllocation) lprintf("out of temp regs");
}
r->regClass = 0;
}
}
