void PHXSimWrap::writeData(uint id, uint64_t addr, uint64_t clockcycle)
{
PRINTFN("%s: id=%d addr=%#lx clock=%lu\n",__func__,id,addr,clockcycle);
std::multimap< uint64_t, PacketPtr >::iterator it =
m_wr_pktMap.find( addr );
assert( it != m_wr_pktMap.end() );
PacketPtr pkt = it->second;
m_wr_lat.sample( curTick() - pkt->dram_enter_time );
PRINTFN("%s() `%s` addr=%#lx size=%d\n", __func__, pkt->cmdString().c_str(),
(long)pkt->getAddr(), pkt->getSize());
PhysicalMemory::doAtomicAccess( pkt );
if ( pkt->needsResponse() ) {
m_readyQ.push_back(pkt);
} else {
delete pkt;
}
m_wr_pktMap.erase( addr );
}
bool PHXSimWrap::recvTiming(PacketPtr pkt)
{
uint64_t addr = pkt->getAddr();
PRINTFN("%s: %s %#lx\n", __func__, pkt->cmdString().c_str(), (long)addr);
pkt->dram_enter_time = curTick();
if ( pkt->isRead() ) {
bool ret = m_memorySystem->AddTransaction( false, addr, 0 );
if ( ! ret ) return false;
assert(m_rd_pktMap.find( addr ) == m_rd_pktMap.end());
m_rd_pktMap[ addr ] = pkt;
} else if ( pkt->isWrite() ) {
bool ret = m_memorySystem->AddTransaction( true, addr, 0 );
if ( ! ret ) return false;
std::multimap< uint64_t, PacketPtr >::iterator it;
it = m_wr_pktMap.find( addr );
assert( it == m_wr_pktMap.end());
m_wr_pktMap.insert( pair<uint64_t, PacketPtr>(addr, pkt) );
} else {
if ( pkt->needsResponse() ) {
pkt->makeTimingResponse();
m_readyQ.push_back( pkt );
} else {
delete pkt;
}
}
return true;
}
void PHXSimWrap::readData(uint id, uint64_t addr, uint64_t clockcycle)
{
PRINTFN("%s: id=%d addr=%#lx clock=%lu\n",__func__,id,addr,clockcycle);
assert( m_rd_pktMap.find( addr ) != m_rd_pktMap.end() );
PacketPtr pkt = m_rd_pktMap[addr];
m_rd_lat.sample( curTick() - pkt->dram_enter_time );
PRINTFN("%s() `%s` addr=%#lx size=%d\n", __func__, pkt->cmdString().c_str(),
(long)pkt->getAddr(), pkt->getSize());
PhysicalMemory::doAtomicAccess( pkt );
m_readyQ.push_back(pkt);
m_rd_pktMap.erase( addr );
}