int main()
{
initCircuit();
SatSolver solver;
solver.initialize();
//
genProofModel(solver);
bool result;
// k = Solve(Gate(5) ^ !Gate(8))
Var newV = solver.newVar();
solver.addXorCNF(newV, gates[5]->getVar(), false, gates[8]->getVar(), true);
solver.assumeRelease(); // Clear assumptions
solver.assumeProperty(newV, true); // k = 1
result = solver.assumpSolve();
reportResult(solver, result);
cout << endl << endl << "======================" << endl;
// k = Solve(Gate(3) & !Gate(7))
newV = solver.newVar();
solver.addAigCNF(newV, gates[3]->getVar(), false, gates[7]->getVar(), true);
solver.assumeRelease(); // Clear assumptions
solver.assumeProperty(newV, true); // k = 1
result = solver.assumpSolve();
reportResult(solver, result);
}
// Solve whether two gates are fuctionally equivalent
// If they are equivalent, return true
// else return false
bool
CirMgr::solveGateEqBySat(SatSolver& s, CirGate* g1, CirGate* g2, bool inverse){
Var newV = s.newVar();
vector<Var> vars;
vars.push_back(g1->getVar());
vars.push_back(g2->getVar());
s.addXorCNF(newV, vars, inverse);
s.assumeRelease(); // Clear assumptions
s.assumeProperty(newV, true);
return !s.assumpSolve();
}
void SATMgr::indBmc(const V3NetId& monitor, SatProofRes& pRes) {
SatSolver* satSolver = pRes.getSatSolver();
bind(satSolver);
uint32_t i = 0;
V3NetId I = buildInitState();
satSolver->addBoundedVerifyData( I, i );
satSolver->assertProperty(I, false, i );
// Start Bounded Model Checking
for (uint32_t j = pRes.getMaxDepth(); i < j; ++i) {
// Add time frame expanded circuit to SAT Solver
satSolver->addBoundedVerifyData(monitor, i);
satSolver->assumeRelease();
satSolver->assumeProperty(monitor, false, i);
satSolver->simplify();
// Assumption Solver: If SAT, diproved!
if(satSolver->assump_solve()) {
pRes.setFired(i);
break;
}
satSolver->assertProperty(monitor, true, i);
}
}
