// This method is cloned from Operator, just resetting sign and exception bits
// (because we don't have any exception support in this toy example)
TestCase* FPSumOf3Squares::buildRandomTestCase(int i){
TestCase *tc;
/* Generate test cases using random input numbers */
tc = new TestCase(this); // TODO free all this memory when exiting TestBench
/* Fill inputs */
for (unsigned int j = 0; j < ioList_.size(); j++) {
Signal* s = ioList_[j];
if (s->type() == Signal::in) {
// ****** Modification: positive normal numbers with small exponents
mpz_class m = getLargeRandom(wF);
mpz_class bias = (mpz_class(1)<<(wE-1)) - 1;
mpz_class e = getLargeRandom(wE-2) - (mpz_class(1)<<(wE-3)) + bias; // ensure no overflow
mpz_class a = (mpz_class(1)<<(wE+wF+1)) // 01 to denote a normal number
+ (e<<wF) + m;
tc->addInput(s->getName(), a);
}
}
/* Get correct outputs */
emulate(tc);
// cout << tc->getInputVHDL();
// cout << tc->getExpectedOutputVHDL();
return tc;
}
void Operator::inPortMap(Operator* op, string componentPortName, string actualSignalName) throw(std::string) {
Signal* formal;
ostringstream e;
string name;
e << "ERROR in inPortMap(), "; // just in case
if(isSequential()) {
Signal *s;
try {
s=getSignalByName(actualSignalName);
}
catch (string e2) {
e << endl << tab << e2;
throw e.str();
}
if(s->getCycle() < 0) {
ostringstream e;
e << "signal " << actualSignalName<< " doesn't have (yet?) a valid cycle";
throw e.str();
}
if(s->getCycle() > currentCycle_) {
ostringstream e;
e << "active cycle of signal " << actualSignalName<< " is later than current cycle, cannot delay it";
throw e.str();
}
// update the lifeSpan of s
s->updateLifeSpan( currentCycle_ - s->getCycle() );
name = s->delayedName( currentCycle_ - s->getCycle() );
}
else
name = actualSignalName;
try {
formal=op->getSignalByName(componentPortName);
}
catch (string e2) {
e << endl << tab << e2;
throw e.str();
}
if (formal->type()!=Signal::in){
e << "signal " << componentPortName << " of component " << op->getName()
<< " doesn't seem to be an input port";
throw e.str();
}
// add the mapping to the mapping list of Op
op->portMap_[componentPortName] = name;
}
void Operator::inPortMapCst(Operator* op, string componentPortName, string actualSignal) throw(std::string) {
Signal* formal;
ostringstream e;
string name;
e << "ERROR in inPortMap(), "; // just in case
try {
formal=op->getSignalByName(componentPortName);
}
catch (string e2) {
e << endl << tab << e2;
throw e.str();
}
if (formal->type()!=Signal::in){
e << "signal " << componentPortName << " of component " << op->getName()
<< " doesn't seem to be an input port";
throw e.str();
}
// add the mapping to the mapping list of Op
op->portMap_[componentPortName] = actualSignal;
}
void Operator::outPortMap(Operator* op, string componentPortName, string actualSignalName) throw(std::string) {
Signal* formal;
Signal* s;
ostringstream e;
e << "ERROR in outPortMap(), "; // just in case
// check the signals doesn't already exist
if(signalMap_.find(actualSignalName) != signalMap_.end()) {
e << "signal " << actualSignalName << " already exists";
throw e.str();
}
try {
formal=op->getSignalByName(componentPortName);
}
catch (string e2) {
e << endl << tab << e2;
throw e.str();
}
if (formal->type()!=Signal::out){
e << "signal " << componentPortName << " of component " << op->getName()
<< " doesn't seem to be an output port";
throw e.str();
}
int width = formal -> width();
bool isbus = formal -> isBus();
// construct the signal (lifeSpan and cycle are reset to 0 by the constructor)
s = new Signal(actualSignalName, Signal::wire, width, isbus);
// define its cycle
if(isSequential())
s->setCycle( this->currentCycle_ + op->getPipelineDepth() );
// add the signal to signalMap and signalList
signalList_.push_back(s);
signalMap_[actualSignalName] = s ;
// add the mapping to the mapping list of Op
op->portMap_[componentPortName] = actualSignalName;
}