int main(int argc, char **argv, char **env) {
int i;
int clk;
Verilated::commandArgs(argc, argv);
// init top verilog instance
Vcounter* top = new Vcounter;
// init trace dump
Verilated::traceEverOn(true);
VerilatedVcdC* tfp = new VerilatedVcdC;
top->trace (tfp, 99);
tfp->open ("counter.vcd");
// initialize simulation inputs
top->clk = 1;
top->rst = 1;
top->cen = 0;
top->wen = 0;
top->dat = 0x55;
// run simulation for 100 clock periods
for (i=0; i<20; i++) {
top->rst = (i < 2);
// dump variables into VCD file and toggle clock
for (clk=0; clk<2; clk++) {
tfp->dump (2*i+clk);
top->clk = !top->clk;
top->eval ();
}
top->cen = (i > 5);
top->wen = (i == 10);
if (Verilated::gotFinish()) exit(0);
}
tfp->close();
exit(0);
}
int main(int argc, char **argv, char **env) {
int i;
int clk;
Verilated::commandArgs(argc, argv);
// init top verilog instance
Vcmsdk_mcu* top = new Vcmsdk_mcu;
// init trace dump
Verilated::traceEverOn(true);
VerilatedVcdC* tfp = new VerilatedVcdC;
top->trace (tfp, 99);
tfp->open ("cmsdk_mcu.vcd");
// initialize simulation inputs
top->XTAL1 = 1;
top->NRST = 0;
top->nTRST = 0;
top->TDI = 0;
top->SWCLKTCK = 0;
// run simulation for 100 clock periods
for (i=0; i<200000; i++) {
top->NRST = (i > 2);
// dump variables into VCD file and toggle clock
for (clk=0; clk<2; clk++) {
tfp->dump (2*i+clk);
top->XTAL1 = !top->XTAL1;
top->eval ();
}
if (Verilated::gotFinish()) exit(0);
}
tfp->close();
exit(0);
}
main() {
cout<<"test: O_LARGEFILE="<<O_LARGEFILE<<endl;
v1 = v2 = s1 = 0;
s2[0] = s2[1] = s2[2] = 0;
tri96[2] = tri96[1] = tri96[0] = 0;
tri96__tri[2] = tri96__tri[1] = tri96__tri[0] = ~0;
ch = 0;
doub = 0;
{
VerilatedVcdC* vcdp = new VerilatedVcdC;
vcdp->spTrace()->addCallback (&vcdInit, &vcdFull, &vcdChange, 0);
vcdp->open ("test.vcd");
// Dumping
vcdp->dump(timestamp++);
v1 = 0xfff;
tri96[2] = 4; tri96[1] = 2; tri96[0] = 1;
tri96__tri[2] = tri96__tri[1] = tri96__tri[0] = ~0; // Still tri
doub = 1.5;
vcdp->dump(timestamp++);
v2 = 0x1;
s2[1] = 2;
tri96__tri[2] = tri96__tri[1] = tri96__tri[0] = 0; // enable w/o data change
doub = -1.66e13;
vcdp->dump(timestamp++);
ch = 2;
tri96[2] = ~4; tri96[1] = ~2; tri96[0] = ~1;
doub = -3.33e-13;
vcdp->dump(timestamp++);
vcdp->dump(timestamp++);
# ifdef VERILATED_VCD_TEST_64BIT
vluint64_t bytesPerDump = 15ULL;
for (vluint64_t i=0; i<((1ULL<<32) / bytesPerDump); i++) {
v1 = i;
vcdp->dump(timestamp++);
}
# endif
vcdp->close();
}
}
void launch() {
int nstime = 0;
//Verilated::commandArgs(argc, argv);
Verilated::traceEverOn(traceOn);
VerilatedVcdC *tfp = new VerilatedVcdC;
Vbench_rrmux* top = new Vbench_rrmux;
top->reset = 1;
if (traceOn) {
top->trace (tfp, 99);
tfp->open ("rrmux.vcd");
}
while (!Verilated::gotFinish() && (nstime < finishTime)) {
if (nstime > 100) top->reset = 0;
if (nstime & 1) top->clk = 1;
else top->clk = 0;
top->eval();
tfp->dump (nstime);
nstime++;
}
if (traceOn) tfp->close();
}
int main(int argc, char **argv, char **env)
{
int eval_num = 0;
int i = 0;
Verilated::commandArgs(argc, argv);
Verilated::debug(0); //Enable debugging at a specified level
Verilated::traceEverOn(true);
Verilated::randReset(2); //Initialize all registers to random
VerilatedVcdC *tfp = new VerilatedVcdC;
Vaxi_gpgpu *top = new Vaxi_gpgpu;
top->trace(tfp, 99);
tfp->open("trace.vcd");
top->reset_n = 0;
for(i = 0 ; i < 10 ; i++){
CYCLE();
}
top->reset_n = 1;
top->axs_rready = 1;
CYCLE();
for(i = 0; i < 50 ; i++){
// master writes data into slave
if(i == 0){
top->axs_awid = 1;
top->axs_awaddr = 53;
top->axs_awlen = 0;
top->axs_awsize = 2;
top->axs_awburst = 1; //incrementing address burst
top->axs_awlock = 0; //normal access
top->axs_awcache = 0;
top->axs_awprot = 2; //normal, non-secure data access
top->axs_awvalid = 1;
CYCLE();
}
if(top->axs_awready){
CYCLE();
top->axs_awvalid = 0;
}
if(i == 2){
top->axs_wid = 1;
top->axs_wdata = 7;
top->axs_wstrb = 15;
top->axs_wlast = 1;
top->axs_wvalid = 1;
CYCLE();
}
if(top->axs_wready){
CYCLE();
top->axs_wvalid = 0;
top->axs_wlast = 0;
}
// master reads data from slave
if(i == 20){
top->axs_arid = 1;
top->axs_araddr = 53;
top->axs_arlen = 0;
top->axs_arsize = 2;
top->axs_arburst = 1; //incrementing address burst
top->axs_arlock = 0; //normal access
top->axs_arcache = 0;
top->axs_arprot = 2; //normal, non-secure data access
top->axs_arvalid = 1;
CYCLE();
}
if(top->axs_arready){
CYCLE();
top->axs_arvalid = 0;
}
CYCLE();
}
if (tfp)
tfp->close();
delete tfp;
return 0;
}
int main(int argc, char** argv) {
Verilated::commandArgs(argc, argv); // Remember args
top = new TOP_TYPE;
#if VM_TRACE // If verilator was invoked with --trace
Verilated::traceEverOn(true); // Verilator must compute traced signals
VL_PRINTF("Enabling waves...\n");
VerilatedVcdC* tfp = new VerilatedVcdC;
top->trace (tfp, 99); // Trace 99 levels of hierarchy
tfp->open ("dump.vcd"); // Open the dump file
#endif
top->reset = 1;
cout << "Starting simulation!\n";
while (!Verilated::gotFinish() && main_time < timeout) {
if (main_time > 10) {
top->reset = 0; // Deassert reset
}
if ((main_time % 10) == 1) {
top->clock = 1; // Toggle clock
}
if ((main_time % 10) == 6) {
top->clock = 0;
}
top->eval(); // Evaluate model
#if VM_TRACE
if (tfp) tfp->dump (main_time); // Create waveform trace for this timestamp
#endif
main_time++; // Time passes...
}
if (main_time >= timeout) {
cout << "Simulation terminated by timeout at time " << main_time <<
" (cycle " << main_time / 10 << ")"<< endl;
return -1;
} else {
cout << "Simulation completed at time " << main_time <<
" (cycle " << main_time / 10 << ")"<< endl;
}
// Run for 10 more clocks
vluint64_t end_time = main_time + 100;
while (main_time < end_time) {
if ((main_time % 10) == 1) {
top->clock = 1; // Toggle clock
}
if ((main_time % 10) == 6) {
top->clock = 0;
}
top->eval(); // Evaluate model
#if VM_TRACE
if (tfp) tfp->dump (main_time); // Create waveform trace for this timestamp
#endif
main_time++; // Time passes...
}
#if VM_TRACE
if (tfp) tfp->close();
#endif
}