UINT16 m68307_sim::read_pbdat(address_space &space, UINT16 mem_mask)
{
int pc = space.device().safe_pc();
m68ki_cpu_core *m68k = m68k_get_safe_token(&space.device());
if (m68k->m_m68307_portb_r)
{
// for general purpose bits, if configured as 'output' then anything output gets latched
// and anything configured as input is read from the port
UINT16 outputbits = m_pbddr;
UINT16 inputbits = ~m_pbddr;
UINT16 general_purpose_bits = ~m_pbcnt;
UINT16 indat = m68k->m_m68307_portb_r(space, false, (inputbits & general_purpose_bits)&mem_mask) & ((inputbits & general_purpose_bits) & mem_mask); // read general purpose input lines
indat |= m68k->m_m68307_portb_r(space, true, (inputbits & ~general_purpose_bits)&mem_mask) & ((inputbits & ~general_purpose_bits)& mem_mask); // read dedicated input lines
UINT16 outdat = (m_pbdat & outputbits) & general_purpose_bits; // read general purpose output lines (reads latched data)
return (indat | outdat);
}
else
{
logerror("%08x m68307_internal_sim_r (%04x) (Port B (16-bit) Data Register - PBDAT)\n", pc, mem_mask);
}
return 0xffff;
}
debug_view_memory_source::debug_view_memory_source(const char *name, address_space &space)
: debug_view_source(name, &space.device()),
m_space(&space),
m_memintf(dynamic_cast<device_memory_interface *>(&space.device())),
m_base(nullptr),
m_length(0),
m_offsetxor(0),
m_endianness(space.endianness()),
m_prefsize(space.data_width() / 8)
{
}
void lpc210x_device::write_timer(address_space &space, int timer, int offset, UINT32 data, UINT32 mem_mask)
{
switch (offset * 4)
{
case 0x0c:
COMBINE_DATA(&m_TxPR[timer]);
logerror("%08x Timer %d Prescale Register set to %08x\n", space.device().safe_pc(),timer, m_TxPR[timer]);
break;
default:
logerror("%08x unhandled write timer %d offset %02x data %08x mem_mask %08x\n", space.device().safe_pc(),timer, offset * 4, data, mem_mask);
}
}
void m68307_sim::write_pbdat(address_space &space, UINT16 data, UINT16 mem_mask)
{
int pc = space.device().safe_pc();
m68ki_cpu_core *m68k = m68k_get_safe_token(&space.device());
COMBINE_DATA(&m_pbdat);
if (m68k->m_m68307_portb_w)
{
m68k->m_m68307_portb_w(space, false, data, mem_mask);
}
else
{
logerror("%08x m68307_internal_sim_w %04x (%04x) (Port B (16-bit) Data Register - PBDAT)\n", pc, data,mem_mask);
}
}
uint8_t a2bus_hsscsi_device::read_c0nx(address_space &space, uint8_t offset)
{
switch (offset)
{
case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
// printf("Read 5380 @ %x\n", offset);
return m_ncr5380->read(space, offset);
case 0xc:
return 0x00; // indicate watchdog?
case 0xe: // code at cf32 wants to RMW this without killing the ROM bank
return m_c0ne;
case 0xf:
return m_c0nf;
default:
printf("Read c0n%x (PC=%x)\n", offset, space.device().safe_pc());
break;
}
return 0xff;
}
uint16_t gaelco_decrypt(address_space &space, int offset, int data, int param1, int param2)
{
static int lastpc, lastoffset, lastencword, lastdecword;
int thispc = space.device().safe_pc();
// int savedata = data;
/* check if 2nd half of 32 bit */
if(lastpc == thispc && offset == lastoffset + 1)
{
lastpc = 0;
data = decrypt(param1, param2, lastencword, lastdecword, data);
}
else
{
/* code as 1st word */
lastpc = thispc;
lastoffset = offset;
lastencword = data;
/* high word returned */
data = decrypt(param1, param2, 0, 0, data);
lastdecword = data;
// logerror("%s : data1 = %4x > %4x @ %8x\n",space.machine().describe_context(),savedata,data,lastoffset);
}
return data;
}
void eolith_speedup_read(address_space &space)
{
/* for debug */
//if ((space.device().safe_pc()!=eolith_speedup_address) && (eolith_vblank!=1) )
// printf("%s:eolith speedup_read data %02x\n",space.machine().describe_context(), eolith_vblank);
if (eolith_vblank==0 && eolith_scanline < eolith_speedup_resume_scanline)
{
int pc = space.device().safe_pc();
if ((pc==eolith_speedup_address) || (pc==eolith_speedup_address2))
{
space.device().execute().spin_until_trigger(1000);
}
}
}
void a2bus_hsscsi_device::write_c0nx(address_space &space, uint8_t offset, uint8_t data)
{
switch (offset)
{
case 0:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
// printf("%02x to 5380 reg %x\n", data, offset);
m_ncr5380->write(space, offset, data);
break;
#if 0
case 8: // DMA address low
break;
case 9: // DMA address high
break;
case 0xa: // DMA count low
break;
case 0xb: // DMA count high
break;
case 0xc: // DMA control
break;
#endif
case 0xd: // DMA enable / reset
printf("%02x to DMA enable/reset\n", data);
if (data & 0x2)
{
// printf("Resetting SCSI: %02x at %x\n", data, space.device().safe_pc());
m_ncr5380->reset();
}
break;
case 0xe:
m_c0ne = data;
m_rombank = (data & 0x1f) * 0x400;
printf("c0ne to %x (ROM bank %x)\n", data & 0x1f, m_rombank);
break;
case 0xf:
m_c0nf = data;
m_rambank = (data & 0x7) * 0x400;
printf("c0nf to %x (RAM bank %x)\n", data & 0x7, m_rambank);
break;
default:
printf("Write %02x to c0n%x (PC=%x)\n", data, offset, space.device().safe_pc());
break;
}
}
void a2bus_pcxporter_device::write_c0nx(address_space &space, uint8_t offset, uint8_t data)
{
switch (offset)
{
default:
printf("Write %02x to c0n%x (PC=%x)\n", data, offset, space.device().safe_pc());
break;
}
}
uint8_t a2bus_pcxporter_device::read_c0nx(address_space &space, uint8_t offset)
{
switch (offset)
{
default:
printf("Read c0n%x (PC=%x)\n", offset, space.device().safe_pc());
break;
}
return 0xff;
}
static UINT32 pm_io(address_space &space, int reg, int write, UINT32 d)
{
mdsvp_state *state = space.machine().driver_data<mdsvp_state>();
if (state->m_emu_status & SSP_PMC_SET)
{
state->m_pmac_read[write ? reg + 6 : reg] = state->m_pmc.d;
state->m_emu_status &= ~SSP_PMC_SET;
return 0;
}
// just in case
if (state->m_emu_status & SSP_PMC_HAVE_ADDR) {
state->m_emu_status &= ~SSP_PMC_HAVE_ADDR;
}
if (reg == 4 || (space.device().state().state_int(SSP_ST) & 0x60))
{
#define CADDR ((((mode<<16)&0x7f0000)|addr)<<1)
UINT16 *dram = (UINT16 *)state->m_dram;
if (write)
{
int mode = state->m_pmac_write[reg]>>16;
int addr = state->m_pmac_write[reg]&0xffff;
if ((mode & 0x43ff) == 0x0018) // DRAM
{
int inc = get_inc(mode);
if (mode & 0x0400) {
overwrite_write(&dram[addr], d);
} else dram[addr] = d;
state->m_pmac_write[reg] += inc;
}
else if ((mode & 0xfbff) == 0x4018) // DRAM, cell inc
{
if (mode & 0x0400) {
overwrite_write(&dram[addr], d);
} else dram[addr] = d;
state->m_pmac_write[reg] += (addr&1) ? 31 : 1;
}
else if ((mode & 0x47ff) == 0x001c) // IRAM
{
int inc = get_inc(mode);
((UINT16 *)state->m_iram)[addr&0x3ff] = d;
state->m_pmac_write[reg] += inc;
}
else
{
logerror("ssp FIXME: PM%i unhandled write mode %04x, [%06x] %04x\n",
reg, mode, CADDR, d);
}
}
else
{
UINT32 lpc210x_device::read_timer(address_space &space, int timer, int offset, UINT32 mem_mask)
{
switch (offset*4)
{
case 0x0c:
return m_TxPR[timer];
default:
logerror("%08x unhandled read from timer %d offset %02x mem_mask %08x\n", space.device().safe_pc(),timer, offset * 4, mem_mask);
}
return 0x00000000;
}
void m68307_sim::write_pbdat(m68307cpu_device* m68k, address_space &space, UINT16 data, UINT16 mem_mask)
{
int pc = space.device().safe_pc();
COMBINE_DATA(&m_pbdat);
if (!m68k->m_m68307_portb_w.isnull())
{
m68k->m_m68307_portb_w(space, false, data, mem_mask);
}
else
{
logerror("%08x m68307_internal_sim_w %04x (%04x) (Port B (16-bit) Data Register - PBDAT)\n", pc, data,mem_mask);
}
}
UINT8 a2bus_corvus_device::read_c0nx(address_space &space, UINT8 offset)
{
switch (offset)
{
case 0:
return m_corvushd->read(space, 0);
case 1:
return m_corvushd->status_r(space, 0);
default:
logerror("Corvus: read unhandled c0n%x (PC=%x)\n", offset, space.device().safe_pc());
break;
}
return 0xff;
}
UINT16 m68307_sim::read_padat(m68307cpu_device* m68k, address_space &space, UINT16 mem_mask)
{
int pc = space.device().safe_pc();
if (!m68k->m_m68307_porta_r.isnull())
{
// for general purpose bits, if configured as 'output' then anything output gets latched
// and anything configured as input is read from the port
UINT8 outputbits = m_paddr;
UINT8 inputbits = ~m_paddr;
UINT8 general_purpose_bits = ~m_pacnt;
UINT8 indat = m68k->m_m68307_porta_r(space, false, (inputbits & general_purpose_bits)&mem_mask) & ((inputbits & general_purpose_bits) & mem_mask); // read general purpose input lines
indat |= m68k->m_m68307_porta_r(space, true, (inputbits & ~general_purpose_bits)&mem_mask) & ((inputbits & ~general_purpose_bits)& mem_mask); // read dedicated input lines
UINT8 outdat = (m_padat & outputbits) & general_purpose_bits; // read general purpose output lines (reads latched data)
return (indat | outdat);
}
else
{
logerror("%08x m68307_internal_sim_r (%04x) (Port A (8-bit) Data Register - PADAT)\n", pc, mem_mask);
}
return 0xffff;
}
void tigeroad_state::f1dream_protection_w(address_space &space)
{
int indx;
int value = 255;
int prevpc = space.device().safe_pcbase();
if (prevpc == 0x244c)
{
/* Called once, when a race is started.*/
indx = m_ram16[0x3ff0/2];
m_ram16[0x3fe6/2] = f1dream_2450_lookup[indx];
m_ram16[0x3fe8/2] = f1dream_2450_lookup[++indx];
m_ram16[0x3fea/2] = f1dream_2450_lookup[++indx];
m_ram16[0x3fec/2] = f1dream_2450_lookup[++indx];
}
else if (prevpc == 0x613a)
{
/* Called for every sprite on-screen.*/
if (m_ram16[0x3ff6/2] < 15)
{
indx = f1dream_613ea_lookup[m_ram16[0x3ff6/2]] - m_ram16[0x3ff4/2];
if (indx > 255)
{
indx <<= 4;
indx += m_ram16[0x3ff6/2] & 0x00ff;
value = f1dream_613eb_lookup[indx];
}
}
m_ram16[0x3ff2/2] = value;
}
else if (prevpc == 0x17b70)
{
/* Called only before a real race, not a time trial.*/
if (m_ram16[0x3ff0/2] >= 0x04) indx = 128;
else if (m_ram16[0x3ff0/2] > 0x02) indx = 96;
else if (m_ram16[0x3ff0/2] == 0x02) indx = 64;
else if (m_ram16[0x3ff0/2] == 0x01) indx = 32;
else indx = 0;
indx += m_ram16[0x3fee/2];
if (indx < 128)
{
m_ram16[0x3fe6/2] = f1dream_17b74_lookup[indx];
m_ram16[0x3fe8/2] = f1dream_17b74_lookup[++indx];
m_ram16[0x3fea/2] = f1dream_17b74_lookup[++indx];
m_ram16[0x3fec/2] = f1dream_17b74_lookup[++indx];
}
else
{
m_ram16[0x3fe6/2] = 0x00ff;
m_ram16[0x3fe8/2] = 0x00ff;
m_ram16[0x3fea/2] = 0x00ff;
m_ram16[0x3fec/2] = 0x00ff;
}
}
else if ((prevpc == 0x27f8) || (prevpc == 0x511a) || (prevpc == 0x5142) || (prevpc == 0x516a))
{
/* The main CPU stuffs the byte for the soundlatch into 0xfffffd.*/
soundlatch_byte_w(space,2,m_ram16[0x3ffc/2]);
}
}
static void log_protection( address_space &space, const char *warning )
{
quizpun2_state *state = space.machine().driver_data<quizpun2_state>();
struct prot_t &prot = state->m_prot;
logerror("%04x: protection - %s (state %x, wait %x, param %02x, cmd %02x, addr %02x)\n", space.device().safe_pc(), warning,
prot.state,
prot.wait_param,
prot.param,
prot.cmd,
prot.addr
);
}
void a2bus_pcxporter_device::write_cnxx(address_space &space, uint8_t offset, uint8_t data)
{
printf("Write %02x to cn%02x (PC=%x)\n", data, offset, space.device().safe_pc());
}
static UINT16
ReadWriteC148( address_space &space, offs_t offset, UINT16 data, int bWrite )
{
offs_t addr = ((offset * 2) + 0x1c0000) & 0x1fe000;
device_t *altcpu = NULL;
UINT16 *pC148Reg = NULL;
UINT16 *pC148RegAlt = NULL;
UINT16 result = 0;
if (&space.device() == space.machine().device("maincpu"))
{
pC148Reg = namcos2_68k_master_C148;
altcpu = space.machine().device("slave");
pC148RegAlt = namcos2_68k_slave_C148;
}
else if (&space.device() == space.machine().device("slave"))
{
pC148Reg = namcos2_68k_slave_C148;
altcpu = space.machine().device("maincpu");
pC148RegAlt = namcos2_68k_master_C148;
}
else if (&space.device() == space.machine().device("gpu"))
{
pC148Reg = namcos2_68k_gpu_C148;
altcpu = space.machine().device("maincpu");
pC148RegAlt = namcos2_68k_master_C148;
}
if( bWrite )
{
int reg = (addr >> 13) & 0x1f;
// If writing an IRQ priority register, clear any pending IRQs.
// Dirt Fox and Winning Run require this behaviour
if (reg < 8)
space.device().execute().set_input_line(pC148Reg[reg], CLEAR_LINE);
pC148Reg[reg] = data & 0x0007;
}
switch(addr)
{
case 0x1c0000: break; /* ? NAMCOS2_C148_0 */
case 0x1c2000: break; /* ? NAMCOS2_C148_1 */
case 0x1c4000: break; /* ? NAMCOS2_C148_2 */
/* IRQ level */
case 0x1c6000: break; /* NAMCOS2_C148_CPUIRQ */
case 0x1c8000: break; /* NAMCOS2_C148_EXIRQ */
case 0x1ca000: break; /* NAMCOS2_C148_POSIRQ */
case 0x1cc000: break; /* NAMCOS2_C148_SERIRQ */
case 0x1ce000: break; /* NAMCOS2_C148_VBLANKIRQ */
case 0x1d0000: /* ? NAMCOS2_C148_0 */
if( bWrite )
{
// mame_printf_debug( "cpu(%d) RAM[0x%06x] = 0x%x\n", cpu, addr, data );
/* Dubious to assert IRQ for other CPU here, but Starblade seems to rely on it.
It fails to show large polygons otherwise. */
altcpu->execute().set_input_line(pC148RegAlt[NAMCOS2_C148_CPUIRQ], ASSERT_LINE);
}
break;
case 0x1d2000: break; /* ? NAMCOS2_C148_1 */
case 0x1d4000: /* ? NAMCOS2_C148_2 */
if( bWrite )
{
// mame_printf_debug( "cpu(%d) RAM[0x%06x] = 0x%x\n", cpu, addr, data );
/* Dubious to assert IRQ for other CPU here: Rolling Thunder 2 and Fine Hour break. */
// altcpu->execute().set_input_line(pC148RegAlt[NAMCOS2_C148_CPUIRQ], ASSERT_LINE);
}
break;
/* IRQ ack */
case 0x1d6000: /* NAMCOS2_C148_CPUIRQ */
// if( bWrite ) mame_printf_debug( "cpu(%d) RAM[0x%06x] = 0x%x\n", cpu, addr, data );
space.device().execute().set_input_line(pC148Reg[NAMCOS2_C148_CPUIRQ], CLEAR_LINE);
break;
case 0x1d8000: /* NAMCOS2_C148_EXIRQ */
// if( bWrite ) mame_printf_debug( "cpu(%d) RAM[0x%06x] = 0x%x\n", cpu, addr, data );
space.device().execute().set_input_line(pC148Reg[NAMCOS2_C148_EXIRQ], CLEAR_LINE);
break;
case 0x1da000: /* NAMCOS2_C148_POSIRQ */
// if( bWrite ) mame_printf_debug( "cpu(%d) RAM[0x%06x] = 0x%x\n", cpu, addr, data );
space.device().execute().set_input_line(pC148Reg[NAMCOS2_C148_POSIRQ], CLEAR_LINE);
break;
case 0x1dc000: /* NAMCOS2_C148_SERIRQ */
// if( bWrite ) mame_printf_debug( "cpu(%d) RAM[0x%06x] = 0x%x\n", cpu, addr, data );
space.device().execute().set_input_line(pC148Reg[NAMCOS2_C148_SERIRQ], CLEAR_LINE);
break;
case 0x1de000: /* NAMCOS2_C148_VBLANKIRQ */
space.device().execute().set_input_line(pC148Reg[NAMCOS2_C148_VBLANKIRQ], CLEAR_LINE);
break;
case 0x1e0000: /* EEPROM Status Register */
result = ~0; /* Only BIT0 used: 1=EEPROM READY 0=EEPROM BUSY */
break;
case 0x1e2000: /* Sound CPU Reset control */
if (&space.device() == space.machine().device("maincpu")) /* ? */
{
if (data & 0x01)
{
/* Resume execution */
space.machine().device("audiocpu")->execute().set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
space.device().execute().yield();
}
else
{
/* Suspend execution */
space.machine().device("audiocpu")->execute().set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
}
if (namcos2_kickstart != NULL)
{
//printf( "dspkick=0x%x\n", data );
if (data & 0x04)
{
(*namcos2_kickstart)(space.machine(), 1);
}
}
}
break;
case 0x1e4000: /* Alt 68000 & IO CPU Reset */
if (&space.device() == space.machine().device("maincpu")) /* ? */
{
if (data & 0x01)
{ /* Resume execution */
ResetAllSubCPUs(space.machine(), CLEAR_LINE);
/* Give the new CPU an immediate slice of the action */
space.device().execute().yield();
}
else
{ /* Suspend execution */
ResetAllSubCPUs(space.machine(), ASSERT_LINE);
}
}
break;
case 0x1e6000: /* Watchdog reset kicker */
/* watchdog_reset_w(0,0); */
break;
default:
break;
}
return result;
}