/** Parse an Import Lookup Table or Import Address Table. The table begins at the specified address and consists of 32- or 64-
* bit vectors which are (1) an ordinal number with high order bit set, (2) a relative virtual address of a hint/name pair, or
* (3) a virtual address filled in by the dynamic linker when the shared object is bound. The last case is assumed if @p
* @p assume_bound is set.
*
* Normally, the ILT and IAT of an executable file have identical structure and content and the IAT is changed only after the
* shared objects are dynamically linked. However, we might encounter cases where we discover that the IAT has values that
* are different than the ILT even when @p assume_bound is false. When this happens, we emit a warning message and treat the
* conflicting IAT entry as a bound address. */
void
SgAsmPEImportDirectory::parse_ilt_iat(const rose_rva_t &table_start, bool assume_bound)
{
SgAsmPEImportSection *isec = SageInterface::getEnclosingNode<SgAsmPEImportSection>(this);
assert(isec!=NULL);
SgAsmPEFileHeader *fhdr = isSgAsmPEFileHeader(isec->get_header());
assert(fhdr!=NULL);
assert(fhdr->get_word_size() <= sizeof(uint64_t));
assert(get_imports()!=NULL);
SgAsmPEImportItemPtrList &imports = get_imports()->get_vector();
bool processing_iat = !imports.empty(); // we always process the ILT first (but it might be empty)
if (0==table_start.get_rva())
return; // no ILT/IAT present
rose_addr_t entry_va=table_start.get_va(), entry_size=fhdr->get_word_size();
uint64_t by_ordinal_bit = 1ull << (8*entry_size-1);
for (size_t idx=0; 1; ++idx, entry_va+=entry_size) {
/* Read the 32- or 64-bit ILT/IAT entry from proces mapped memory. */
uint64_t entry_word = 0;
try {
isec->read_content(fhdr->get_loader_map(), entry_va, &entry_word, entry_size);
} catch (const MemoryMap::NotMapped &e) {
if (SgAsmPEImportSection::show_import_mesg()) {
mlog[WARN] <<"SgAsmPEImportDirectory: ILT/IAT entry #" <<idx
<<" at va " <<StringUtility::addrToString(entry_va)
<<": table entry is outside mapped memory\n";
if (e.map) {
mlog[WARN] <<" Memory map in effect at time of error:\n";
e.map->dump(mlog[WARN], " ");
}
}
}
entry_word = ByteOrder::le_to_host(entry_word);
/* ILT/IAT are to be terminated by a zero word. However, the length of the IAT is required to be the same as the
* length of the ILT. Handle three cases here:
* (1) Termination of the ILT by a zero entry; stop now
* (2) Premature termination of the IAT; continue processing
* (3) Missing (or late) termination of the IAT; stop now */
if (0==entry_word) {
if (idx<imports.size()) {
if (SgAsmPEImportSection::show_import_mesg()) {
mlog[ERROR] <<"SgAsmPEImportDirectory: IAT entry #" <<idx
<<" at va " <<StringUtility::addrToString(entry_va)
<<": IAT zero termination occurs before end of corresponding ILT;"
<<(assume_bound?"":"assuming this is a bound null address and ")
<<" continuing to read IAT entries.\n";
}
assert(idx<imports.size());
imports[idx]->set_bound_rva(rose_rva_t(entry_word).bind(fhdr));
continue;
} else {
break;
}
} else if (processing_iat && idx>=imports.size()) {
if (SgAsmPEImportSection::show_import_mesg()) {
mlog[WARN] <<"SgAsmPEImportDirectory: IAT entry #" <<idx
<<" at va " <<StringUtility::addrToString(entry_va)
<<": IAT extends beyond end of corresponding ILT (it is not zero terminated)"
<<"; forcibly terminating here\n";
}
break;
}
/* Create the new table entry if necessary. */
bool entry_existed = true;
if (idx>=imports.size()) {
assert(idx==imports.size());
new SgAsmPEImportItem(get_imports()); // adds new item to imports list
entry_existed = false;
}
SgAsmPEImportItem *import_item = imports[idx];
if (assume_bound) {
/* The entry word is a virtual address. */
if (entry_existed && import_item->get_bound_rva().get_rva()>0 &&
import_item->get_bound_rva().get_rva()!=entry_word) {
if (SgAsmPEImportSection::show_import_mesg()) {
mlog[WARN] <<"SgAsmPEImportDirectory: ILT/IAT entry #" <<idx
<<" at va " <<StringUtility::addrToString(entry_va)
<<": bound address " <<StringUtility::addrToString(entry_word)
<<" conflicts with bound address already discovered "
<<import_item->get_bound_rva().get_rva() <<" (using new value)\n";
}
}
import_item->set_bound_rva(rose_rva_t(entry_word).bind(fhdr));
} else if (0!=(entry_word & by_ordinal_bit)) {
/* The entry is an ordinal number. */
if (entry_existed && import_item->get_ordinal()!=0 && import_item->get_ordinal()!=(entry_word & 0xffff)) {
if (SgAsmPEImportSection::show_import_mesg()) {
mlog[WARN] <<"SgAsmPEImportDirectory: ILT/IAT entry #" <<idx
<<" at va " <<StringUtility::addrToString(entry_va)
<<": ordinal " <<(entry_word & 0xffff) <<" conflicts with ordinal already discovered "
<<import_item->get_ordinal()
<<" (assuming this is a bound address)\n";
}
import_item->set_bound_rva(rose_rva_t(entry_word).bind(fhdr));
} else {
import_item->set_by_ordinal(true);
import_item->set_ordinal(entry_word & 0xffff);
if (0!=(entry_word & ~(by_ordinal_bit | 0xffff))) {
if (SgAsmPEImportSection::show_import_mesg()) {
mlog[WARN] <<"SgAsmPEImportDirectory: ILT/IAT entry #" <<idx
<<" at va " <<StringUtility::addrToString(entry_va)
<<": contains extra bits in violation of PE specification"
<<" (extra bits removed)\n";
}
}
}
} else {
/* The entry word points to a Hint/Name pair: a 2-byte, little endian hint, followed by a NUL-terminated string,
* followed by an optional extra byte to make the total length a multiple of two. */
if (entry_existed && import_item->get_by_ordinal()) {
if (SgAsmPEImportSection::show_import_mesg()) {
mlog[WARN] <<"SgAsmPEImportDirectory: ILT/IAT entry #" <<idx
<<" at va " <<StringUtility::addrToString(entry_va)
<<": entry type \"hint/name\" conflicts with entry type already discovered"
<<" \"ordinal\" (assuming this is a bound address)\n";
}
import_item->set_bound_rva(rose_rva_t(entry_word).bind(fhdr));
} else if (entry_existed && import_item->get_hintname_rva().get_rva()>0 &&
import_item->get_hintname_rva().get_rva()!=entry_word) {
if (SgAsmPEImportSection::show_import_mesg()) {
mlog[WARN] <<"SgAsmPEImportDirectory: ILT/IAT entry #" <<idx
<<" at va " <<StringUtility::addrToString(entry_va)
<<": hint/name rva " <<entry_word
<<" conflicts with hint/name rva already discovered "
<<import_item->get_hintname_rva().get_rva()
<<" (assuming this is a bound address)\n";
}
import_item->set_bound_rva(rose_rva_t(entry_word).bind(fhdr));
} else {
import_item->set_by_ordinal(false);
import_item->set_hintname_rva(rose_rva_t(entry_word).bind(fhdr));
import_item->set_hintname_nalloc(0); // for now, will adjust after we read it
rose_addr_t entry_word_va = entry_word + fhdr->get_base_va();
uint16_t hint;
try {
isec->read_content(fhdr->get_loader_map(), entry_word_va, &hint, sizeof hint);
} catch (const MemoryMap::NotMapped &e) {
import_item->set_hint(0);
import_item->get_name()->set_string("");
if (SgAsmPEImportSection::show_import_mesg()) {
mlog[WARN] <<"SgAsmPEImportDirectory: ILT/IAT entry #" <<idx
<<" at va " <<StringUtility::addrToString(entry_va)
<<": points to unmapped Hint/Name pair at va "
<<StringUtility::addrToString(entry_word_va) <<"\n";
if (e.map) {
mlog[WARN] <<" Memory map in effect at time of error:\n";
e.map->dump(mlog[WARN], " ");
}
}
continue; // to next ILT/IAT entry
}
hint = ByteOrder::le_to_host(hint);
import_item->set_hint(hint);
std::string s;
try {
s = isec->read_content_str(fhdr->get_loader_map(), entry_word_va+2);
} catch (const MemoryMap::NotMapped &e) {
import_item->get_name()->set_string("");
if (SgAsmPEImportSection::show_import_mesg()) {
mlog[WARN] <<"SgAsmPEImportDirectory: ILT/IAT entry #" <<idx
<<" at va " <<StringUtility::addrToString(entry_va)
<<": points to an unmapped Hint/Name pair at va "
<<StringUtility::addrToString(entry_word_va) <<"\n";
if (e.map) {
mlog[WARN] <<" Memory map in effect at time of error:\n";
e.map->dump(mlog[WARN], " ");
}
}
continue; // to next ILT/IAT entry
}
import_item->get_name()->set_string(s);
if ((s.size()+1) % 2) {
uint8_t byte = 0;
try {
isec->read_content(fhdr->get_loader_map(), entry_word_va+2+s.size()+1, &byte, 1);
} catch (const MemoryMap::NotMapped &e) {
if (SgAsmPEImportSection::show_import_mesg()) {
mlog[WARN] <<"SgAsmPEImportDirectory: ILT/IAT entry #" <<idx
<<" at va " <<StringUtility::addrToString(entry_va)
<<": points to an unmapped Hint/Name pair at va "
<<StringUtility::addrToString(entry_word_va)
<<" (when reading pad byte)\n";
if (e.map) {
mlog[WARN] <<" Memory map in effect at time of error:\n";
e.map->dump(mlog[WARN], " ");
}
}
continue; // to next ILT/IAT entry
}
if (byte) {
if (SgAsmPEImportSection::show_import_mesg()) {
mlog[WARN] <<"SgAsmPEImportDirctory: ILT/IAT entry #" <<idx
<<" at va " <<StringUtility::addrToString(entry_va)
<<": has a non-zero padding byte: "
<<StringUtility::toHex2(byte, 8) <<"\n";
}
}
}
import_item->set_hintname_nalloc(import_item->hintname_required_size());
}
}
}
}
size_t
SgAsmGenericSection::read_content(const MemoryMap::Ptr &map, const rose_rva_t &start, void *dst_buf,
rose_addr_t size, bool strict) {
return read_content(map, start.get_va(), dst_buf, size, strict);
}
