void Interface::save(unsigned id, const stream& stream) {
if(id == ID::ProgramRAM) {
stream.write(cartridge.board->prgram.data, cartridge.board->prgram.size);
}
if(id == ID::CharacterRAM) {
stream.write(cartridge.board->chrram.data, cartridge.board->chrram.size);
}
}
void writeConverter(stream<memCtrlWord> &memWrCmd, stream<ap_uint<memBusWidth> > &memWrData, stream<datamoverCtrlWord> &dmWrCmd, stream<axiWord> &dmWrData, stream<ap_uint<8> > &dmWrStatus) {
#pragma HLS INTERFACE ap_ctrl_none port=return
#pragma HLS DATA_PACK variable=memWrCmd
#pragma HLS DATA_PACK variable=dmWrCmd
#pragma HLS DATA_PACK variable=dmWrData
#pragma HLS RESOURCE variable=memWrCmd core=AXI4Stream
#pragma HLS RESOURCE variable=memWrData core=AXI4Stream
#pragma HLS RESOURCE variable=dmWrCmd core=AXI4Stream
#pragma HLS RESOURCE variable=dmWrData core=AXI4Stream
#pragma HLS RESOURCE variable=dmWrStatus core=AXI4Stream
static ap_uint<4> tagCounter = 0;
static ap_uint<16> noOfBytesToWrite = 0;
static ap_uint<16> byteCount = 0;
static enum wcState{WRC_IDLE = 0, WRC_FWD, WRC_STATUS} writeConverterState;
switch(writeConverterState) {
case WRC_IDLE:
if (!memWrCmd.empty() && !dmWrCmd.full()) {
memCtrlWord writeTemp = memWrCmd.read();
ap_uint<32> convertedAddress = writeTemp.address * 64;
datamoverCtrlWord writeCtrlWord = {(writeTemp.count*(memBusWidth/8)), 1, 0, 1, 0, convertedAddress, tagCounter, 0};
noOfBytesToWrite = writeTemp.count;
dmWrCmd.write(writeCtrlWord);
tagCounter++;
writeConverterState = WRC_FWD;
}
break;
case WRC_FWD:
if (!memWrData.empty() && !dmWrData.full()) {
axiWord writeTemp2 = {0, 0xFFFFFFFFFFFFFFFF, 0};
memWrData.read(writeTemp2.data);
if (byteCount == noOfBytesToWrite - 1) {
writeTemp2.last = 1;
writeConverterState = WRC_STATUS;
byteCount = 0;
}
else
byteCount++;
dmWrData.write(writeTemp2);
}
break;
case WRC_STATUS:
if (!dmWrStatus.empty()) {
ap_uint<8> tempVariable = dmWrStatus.read();
writeConverterState = WRC_IDLE;
}
break;
}
}
void Interface::save(unsigned id, const stream& stream) {
if(id == ID::RAM) {
stream.write(cartridge.ram.data, cartridge.ram.size);
}
if(id == ID::EEPROM) {
stream.write(cartridge.eeprom.data, cartridge.eeprom.size);
}
if(id == ID::FlashROM) {
stream.write(cartridge.flashrom.data, cartridge.flashrom.size);
}
}
void simulateTxBuffer(stream<mmCmd>& command,
stream<axiWord>& dataOut)
{
static mmCmd cmd;
static ap_uint<1> fsmState = 0;
static ap_uint<16> wordCount = 0;
axiWord memWord;
switch (fsmState)
{
case 0:
if (!command.empty())
{
command.read(cmd);
fsmState = 1;
}
break;
case 1:
memWord.data = 0x3031323334353637;
memWord.keep = 0xff;
memWord.last = 0x0;
wordCount += 8;
if (wordCount >= cmd.bbt)
{
memWord.last = 0x1;
fsmState = 0;
wordCount = 0;
}
dataOut.write(memWord);
break;
}
}
int main()
{
static stream<ap_uint<16> > clearTimerFifo;
static stream<ap_uint<16> > setTimerFifo;
static stream<event> eventFifo;
event ev;
int count = 0;
//for (int i=0; i < 10; i++)
//{
setTimerFifo.write(7);
//}
while (count < 50000)
{
/*if (count < 100)
{
setTimerFifo.write(count);
std::cout << "set Timer for: " << count << std::endl;
}*/
if (count == 9 || count == 12)
{
//for (int i=0; i < 10; i++)
//{
setTimerFifo.write(7); //try 33
//}
}
if (count == 21)
{
clearTimerFifo.write(22);
setTimerFifo.write(22);
}
probe_timer(clearTimerFifo, setTimerFifo, eventFifo);
if (!eventFifo.empty())
{
eventFifo.read(ev);
std::cout << "ev happened, ID: " << ev.sessionID;// << std::endl;
std::cout << "\t\tcount: " << count << std::endl;
}
count++;
}
return 0;
}
void readConverter(stream<memCtrlWord> &memRdCmd, stream<ap_uint<memBusWidth> > &memRdData, stream<datamoverCtrlWord> &dmRdCmd,
stream<axiWord> &dmRdData, stream<ap_uint<8> > &dmRdStatus) {
#pragma HLS INTERFACE ap_ctrl_none port=return
#pragma HLS pipeline II=1 enable_flush
#pragma HLS DATA_PACK variable=memRdCmd
#pragma HLS DATA_PACK variable=dmRdCmd
#pragma HLS DATA_PACK variable=dmRdData
#pragma HLS RESOURCE variable=dmRdStatus core=AXI4Stream
#pragma HLS RESOURCE variable=memRdData core=AXI4Stream
#pragma HLS RESOURCE variable=dmRdCmd core=AXI4Stream
#pragma HLS RESOURCE variable=dmRdData core=AXI4Stream
#pragma HLS RESOURCE variable=memRdCmd core=AXI4Stream
static ap_uint<4> tagCounter = 0;
//static enum rcState{RDC_IDLE = 0, RDC_FWD, RDC_STATUS} readConverterState;
//switch(readConverterState) {
//case RDC_IDLE:
if (!memRdCmd.empty() && !dmRdCmd.full()) {
memCtrlWord readTemp = memRdCmd.read();
ap_uint<32> convertedAddress = readTemp.address * 64;
datamoverCtrlWord readCtrlWord = {(readTemp.count * (memBusWidth/8)), 1, 0, 1, 0, convertedAddress, tagCounter, 0};
//ap_uint<16> readCtrlWord = readTemp.address.range(15, 0);
dmRdCmd.write(readCtrlWord);
tagCounter++;
//readConverterState = RDC_FWD;
}
//break;
//case RDC_FWD:
if (!dmRdData.empty() && !memRdData.full()) {
axiWord readTemp = dmRdData.read();
memRdData.write(readTemp.data);
//if (readTemp.last)
//readConverterState = RDC_STATUS;
}
//break;
//case RDC_STATUS:
if (!dmRdStatus.empty()) {
ap_uint<8> tempVariable = dmRdStatus.read();
//readConverterState = RDC_IDLE;
}
//break;
}
void simulateRevSLUP(stream<ap_uint<16> >& txEng2sLookup_rev_req,
stream<fourTuple>& sLookup2txEng_rev_rsp)
{
fourTuple tuple;
tuple.dstIp = 0x0101010a;
tuple.dstPort = 0x5001;
tuple.srcIp = 0x01010101;
tuple.srcPort = 0xaffff;
if (!txEng2sLookup_rev_req.empty())
{
txEng2sLookup_rev_req.read();
sLookup2txEng_rev_rsp.write(tuple);
}
}
void simulateSARtables( stream<rxSarEntry>& rxSar2txEng_upd_rsp,
stream<txSarEntry>& txSar2txEng_upd_rsp,
stream<ap_uint<16> >& txEng2rxSar_upd_req,
stream<txTxSarQuery>& txEng2txSar_upd_req)
{
ap_uint<16> addr;
txTxSarQuery in_txaccess;
if (!txEng2rxSar_upd_req.empty())
{
txEng2rxSar_upd_req.read(addr);
rxSar2txEng_upd_rsp.write((rxSarEntry) {0x0023, 0xadbd});
}
if (!txEng2txSar_upd_req.empty())
{
txEng2txSar_upd_req.read(in_txaccess);
if (in_txaccess.write == 0)
{
txSar2txEng_upd_rsp.write(((txSarEntry) {3, 5, 0xffff, 5, 1}));
}
//omit write
}
}
void ad_window(stream<axiInIndex> &inData, stream<axiIndex> &outData) {
#pragma HLS pipeline II=1 enable_flush
// Current Word
axiInIndex currWord = {0};
// Score
axiIndex currIndex = {0, 0, 0, 0, 0, 0};
// Read Data
inData.read(currWord);
// DET SHIFT REGISTER
static INDEXTYPE det_window[DET_W];
#pragma HLS ARRAY_PARTITION variable=det_window complete dim=0
for (int i = 0; i < DET_W-1; i++) {
#pragma HLS unroll
det_window[i] = det_window[i+1];
}
det_window[DET_W-1] = currWord.ind;
// REF SHIFT REGISTER
static INDEXTYPE ref_window[REF_W];
#pragma HLS ARRAY_PARTITION variable=ref_window complete dim=0
for (int i = 0; i < REF_W-1; i++) {
#pragma HLS unroll
ref_window[i] = ref_window[i+1];
}
ref_window[REF_W-1] = currWord.ind;
currIndex.a = det_window[0];
currIndex.b = det_window[1];
currIndex.c = ref_window[0];
currIndex.d = ref_window[1];
currIndex.e = det_window[DET_W-2];
currIndex.f = currWord.ind;
outData.write(currIndex);
}
void sub(stream<CMD> &io_cmd, stream<RESP> &io_resp){
#pragma HLS data_pack variable=io_cmd
#pragma HLS data_pack variable=io_resp
CMD cmd_token;
RESP resp_token;
cmd_token = io_cmd.read();
ap_uint<64> a = cmd_token.rs1;
ap_uint<64> b = cmd_token.rs2;
// martin's module
a = a - b;
resp_token.io_busy = 0;
resp_token.io_interrupt = 0;
resp_token.io_autl_acquire_ready = 0;
resp_token.io_autl_acquire_valid = 0;
resp_token.io_mem_req_valid = 0;
resp_token.rd = cmd_token.inst_rd;
resp_token.data = a;
io_resp.write(resp_token);
}
void Interface::save(unsigned id, const stream& stream) {
if(id == ID::RAM) {
stream.write(cartridge.ramdata, cartridge.ramsize);
}
}
void Interface::save(unsigned id, const stream& stream) {
if(id == ID::RAM) stream.write(cartridge.ram.data(), cartridge.ram.size());
if(id == ID::EventRAM) stream.write(event.ram.data(), event.ram.size());
if(id == ID::SA1IRAM) stream.write(sa1.iram.data(), sa1.iram.size());
if(id == ID::SA1BWRAM) stream.write(sa1.bwram.data(), sa1.bwram.size());
if(id == ID::SuperFXRAM) stream.write(superfx.ram.data(), superfx.ram.size());
if(id == ID::ArmDSPRAM) {
for(unsigned n = 0; n < 16 * 1024; n++) stream.write(armdsp.programRAM[n]);
}
if(id == ID::HitachiDSPRAM) stream.write(hitachidsp.ram.data(), hitachidsp.ram.size());
if(id == ID::HitachiDSPDRAM) {
for(unsigned n = 0; n < 3072; n++) stream.writel(hitachidsp.dataRAM[n], 1);
}
if(id == ID::Nec7725DSPRAM) {
for(unsigned n = 0; n < 256; n++) stream.writel(necdsp.dataRAM[n], 2);
}
if(id == ID::Nec96050DSPRAM) {
for(unsigned n = 0; n < 2048; n++) stream.writel(necdsp.dataRAM[n], 2);
}
if(id == ID::EpsonRTC) {
uint8 data[16] = {0};
epsonrtc.save(data);
stream.write(data, sizeof data);
}
if(id == ID::SharpRTC) {
uint8 data[16] = {0};
sharprtc.save(data);
stream.write(data, sizeof data);
}
if(id == ID::SPC7110RAM) stream.write(spc7110.ram.data(), spc7110.ram.size());
if(id == ID::SDD1RAM) stream.write(sdd1.ram.data(), sdd1.ram.size());
if(id == ID::OBC1RAM) stream.write(obc1.ram.data(), obc1.ram.size());
if(id == ID::SuperGameBoyRAM) stream.write(GameBoy::cartridge.ramdata, GameBoy::cartridge.ramsize);
if(id == ID::BsxRAM) stream.write(bsxcartridge.ram.data(), bsxcartridge.ram.size());
if(id == ID::BsxPSRAM) stream.write(bsxcartridge.psram.data(), bsxcartridge.psram.size());
if(id == ID::SufamiTurboSlotARAM) stream.write(sufamiturboA.ram.data(), sufamiturboA.ram.size());
if(id == ID::SufamiTurboSlotBRAM) stream.write(sufamiturboB.ram.data(), sufamiturboB.ram.size());
}
void ad_grid(stream<axiRawValues> &inData, stream<axiValues> &outData){
#pragma HLS pipeline II=1 enable_flush
// Current Raw Values
axiRawValues currRawValues = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
// Current Values
axiValues currValues = {0, 0, 0, 0, 0, 0};
// Read In Values
inData.read(currRawValues);
MATHTYPE det_det_prev = currRawValues.det_det_prev;
MATHTYPE det_ref_prev = currRawValues.det_ref_prev;
MATHTYPE det_curr_prev = currRawValues.det_curr_prev;
MATHTYPE ref_det_prev = currRawValues.ref_det_prev;
MATHTYPE ref_ref_prev = currRawValues.ref_ref_prev;
MATHTYPE ref_curr_prev = currRawValues.ref_curr_prev;
MATHTYPE det_det_curr = currRawValues.det_det_curr;
MATHTYPE det_ref_curr = currRawValues.det_ref_curr;
MATHTYPE det_curr_curr = currRawValues.det_curr_curr;
MATHTYPE ref_det_curr = currRawValues.ref_det_curr;
MATHTYPE ref_ref_curr = currRawValues.ref_ref_curr;
MATHTYPE ref_curr_curr = currRawValues.ref_curr_curr;
// Remove det_window[0], det_window[1]
MATHTYPE det_rm;
#pragma HLS RESOURCE variable=det_rm core=AddSubnS
det_rm = (det_det_prev - ref_det_prev);
// Remove ref_window[0], ref_window[1]
MATHTYPE ref_rm;
#pragma HLS RESOURCE variable=ref_rm core=AddSubnS
ref_rm = (det_ref_prev - ref_ref_prev);
// Remove currWord.data, det_window[DET_W-2]
MATHTYPE curr_rm;
#pragma HLS RESOURCE variable=curr_rm core=AddSubnS
curr_rm = (det_curr_prev - ref_curr_prev);
// Add det_window[0], det_window[1]
MATHTYPE det_add;
#pragma HLS RESOURCE variable=det_add core=AddSubnS
det_add = (det_det_curr - ref_det_curr);
// Add ref_window[0], ref_window[1]
MATHTYPE ref_add;
#pragma HLS RESOURCE variable=ref_add core=AddSubnS
ref_add = (det_ref_curr - ref_ref_curr);
// Add currWord.data, det_window[DET_W-2]
MATHTYPE curr_add;
#pragma HLS RESOURCE variable=curr_add core=AddSubnS
curr_add = (det_curr_curr - ref_curr_curr);
currValues.det_rm = det_rm;
currValues.ref_rm = ref_rm;
currValues.curr_rm = curr_rm;
currValues.det_add = det_add;
currValues.ref_add = ref_add;
currValues.curr_add = curr_add;
outData.write(currValues);
}