Assembler::Jump Binop::genInlineBinop(IR::Expr *leftSource, IR::Expr *rightSource, IR::Expr *target)
{
Assembler::Jump done;
// Try preventing a call for a few common binary operations. This is used in two cases:
// - no register allocation was performed (not available for the platform, or the IR was
// not transformed into SSA)
// - type inference found that either or both operands can be of non-number type, and the
// register allocator will have prepared for a call (meaning: all registers that do not
// hold operands are spilled to the stack, which makes them available here)
// Note: FPGPr0 can still not be used, because uint32->double conversion uses it as a scratch
// register.
switch (op) {
case IR::OpAdd: {
Assembler::FPRegisterID lReg = getFreeFPReg(rightSource, 2);
Assembler::FPRegisterID rReg = getFreeFPReg(leftSource, 4);
Assembler::Jump leftIsNoDbl = as->genTryDoubleConversion(leftSource, lReg);
Assembler::Jump rightIsNoDbl = as->genTryDoubleConversion(rightSource, rReg);
as->addDouble(rReg, lReg);
as->storeDouble(lReg, target);
done = as->jump();
if (leftIsNoDbl.isSet())
leftIsNoDbl.link(as);
if (rightIsNoDbl.isSet())
rightIsNoDbl.link(as);
}
break;
case IR::OpMul: {
Assembler::FPRegisterID lReg = getFreeFPReg(rightSource, 2);
Assembler::FPRegisterID rReg = getFreeFPReg(leftSource, 4);
Assembler::Jump leftIsNoDbl = as->genTryDoubleConversion(leftSource, lReg);
Assembler::Jump rightIsNoDbl = as->genTryDoubleConversion(rightSource, rReg);
as->mulDouble(rReg, lReg);
as->storeDouble(lReg, target);
done = as->jump();
if (leftIsNoDbl.isSet())
leftIsNoDbl.link(as);
if (rightIsNoDbl.isSet())
rightIsNoDbl.link(as);
}
break;
case IR::OpSub: {
Assembler::FPRegisterID lReg = getFreeFPReg(rightSource, 2);
Assembler::FPRegisterID rReg = getFreeFPReg(leftSource, 4);
Assembler::Jump leftIsNoDbl = as->genTryDoubleConversion(leftSource, lReg);
Assembler::Jump rightIsNoDbl = as->genTryDoubleConversion(rightSource, rReg);
as->subDouble(rReg, lReg);
as->storeDouble(lReg, target);
done = as->jump();
if (leftIsNoDbl.isSet())
leftIsNoDbl.link(as);
if (rightIsNoDbl.isSet())
rightIsNoDbl.link(as);
}
break;
case IR::OpDiv: {
Assembler::FPRegisterID lReg = getFreeFPReg(rightSource, 2);
Assembler::FPRegisterID rReg = getFreeFPReg(leftSource, 4);
Assembler::Jump leftIsNoDbl = as->genTryDoubleConversion(leftSource, lReg);
Assembler::Jump rightIsNoDbl = as->genTryDoubleConversion(rightSource, rReg);
as->divDouble(rReg, lReg);
as->storeDouble(lReg, target);
done = as->jump();
if (leftIsNoDbl.isSet())
leftIsNoDbl.link(as);
if (rightIsNoDbl.isSet())
rightIsNoDbl.link(as);
}
break;
default:
break;
}
return done;
}
void Binop::doubleBinop(IR::Expr *lhs, IR::Expr *rhs, IR::Temp *target)
{
Q_ASSERT(lhs->asConst() == 0 || rhs->asConst() == 0);
Q_ASSERT(isPregOrConst(lhs));
Q_ASSERT(isPregOrConst(rhs));
Assembler::FPRegisterID targetReg;
if (target->kind == IR::Temp::PhysicalRegister)
targetReg = (Assembler::FPRegisterID) target->index;
else
targetReg = Assembler::FPGpr0;
switch (op) {
case IR::OpAdd:
as->addDouble(as->toDoubleRegister(lhs), as->toDoubleRegister(rhs),
targetReg);
break;
case IR::OpMul:
as->mulDouble(as->toDoubleRegister(lhs), as->toDoubleRegister(rhs),
targetReg);
break;
case IR::OpSub:
#if CPU(X86) || CPU(X86_64)
if (IR::Temp *rightTemp = rhs->asTemp()) {
if (rightTemp->kind == IR::Temp::PhysicalRegister && rightTemp->index == targetReg) {
as->moveDouble(targetReg, Assembler::FPGpr0);
as->moveDouble(as->toDoubleRegister(lhs, targetReg), targetReg);
as->subDouble(Assembler::FPGpr0, targetReg);
break;
}
} else if (rhs->asConst() && targetReg == Assembler::FPGpr0) {
Q_ASSERT(lhs->asTemp());
Q_ASSERT(lhs->asTemp()->kind == IR::Temp::PhysicalRegister);
as->moveDouble(as->toDoubleRegister(lhs, targetReg), targetReg);
Assembler::FPRegisterID reg = (Assembler::FPRegisterID) lhs->asTemp()->index;
as->moveDouble(as->toDoubleRegister(rhs, reg), reg);
as->subDouble(reg, targetReg);
break;
}
#endif
as->subDouble(as->toDoubleRegister(lhs), as->toDoubleRegister(rhs),
targetReg);
break;
case IR::OpDiv:
#if CPU(X86) || CPU(X86_64)
if (IR::Temp *rightTemp = rhs->asTemp()) {
if (rightTemp->kind == IR::Temp::PhysicalRegister && rightTemp->index == targetReg) {
as->moveDouble(targetReg, Assembler::FPGpr0);
as->moveDouble(as->toDoubleRegister(lhs, targetReg), targetReg);
as->divDouble(Assembler::FPGpr0, targetReg);
break;
}
} else if (rhs->asConst() && targetReg == Assembler::FPGpr0) {
Q_ASSERT(lhs->asTemp());
Q_ASSERT(lhs->asTemp()->kind == IR::Temp::PhysicalRegister);
as->moveDouble(as->toDoubleRegister(lhs, targetReg), targetReg);
Assembler::FPRegisterID reg = (Assembler::FPRegisterID) lhs->asTemp()->index;
as->moveDouble(as->toDoubleRegister(rhs, reg), reg);
as->divDouble(reg, targetReg);
break;
}
#endif
as->divDouble(as->toDoubleRegister(lhs), as->toDoubleRegister(rhs),
targetReg);
break;
default: {
Q_ASSERT(target->type == IR::BoolType);
Assembler::Jump trueCase = as->branchDouble(false, op, lhs, rhs);
as->storeBool(false, target);
Assembler::Jump done = as->jump();
trueCase.link(as);
as->storeBool(true, target);
done.link(as);
} return;
}
if (target->kind != IR::Temp::PhysicalRegister)
as->storeDouble(Assembler::FPGpr0, target);
}
void Binop::doubleBinop(IR::Expr *lhs, IR::Expr *rhs, IR::Expr *target)
{
IR::Temp *targetTemp = target->asTemp();
Assembler::FPRegisterID targetReg;
if (targetTemp && targetTemp->kind == IR::Temp::PhysicalRegister)
targetReg = (Assembler::FPRegisterID) targetTemp->index;
else
targetReg = Assembler::FPGpr0;
switch (op) {
case IR::OpAdd:
if (lhs->asConst())
std::swap(lhs, rhs); // Y = constant + X -> Y = X + constant
#if CPU(X86)
if (IR::Const *c = rhs->asConst()) { // Y = X + constant -> Y = X; Y += [constant-address]
as->moveDouble(as->toDoubleRegister(lhs, targetReg), targetReg);
Assembler::Address addr = as->constantTable().loadValueAddress(c, Assembler::ScratchRegister);
as->addDouble(addr, targetReg);
break;
}
if (IR::Temp *t = rhs->asTemp()) { // Y = X + [temp-memory-address] -> Y = X; Y += [temp-memory-address]
if (t->kind != IR::Temp::PhysicalRegister) {
as->moveDouble(as->toDoubleRegister(lhs, targetReg), targetReg);
as->addDouble(as->loadTempAddress(t), targetReg);
break;
}
}
#endif
as->addDouble(as->toDoubleRegister(lhs, Assembler::FPGpr0), as->toDoubleRegister(rhs, Assembler::FPGpr1), targetReg);
break;
case IR::OpMul:
if (lhs->asConst())
std::swap(lhs, rhs); // Y = constant * X -> Y = X * constant
#if CPU(X86)
if (IR::Const *c = rhs->asConst()) { // Y = X * constant -> Y = X; Y *= [constant-address]
as->moveDouble(as->toDoubleRegister(lhs, targetReg), targetReg);
Assembler::Address addr = as->constantTable().loadValueAddress(c, Assembler::ScratchRegister);
as->mulDouble(addr, targetReg);
break;
}
if (IR::Temp *t = rhs->asTemp()) { // Y = X * [temp-memory-address] -> Y = X; Y *= [temp-memory-address]
if (t->kind != IR::Temp::PhysicalRegister) {
as->moveDouble(as->toDoubleRegister(lhs, targetReg), targetReg);
as->mulDouble(as->loadTempAddress(t), targetReg);
break;
}
}
#endif
as->mulDouble(as->toDoubleRegister(lhs, Assembler::FPGpr0), as->toDoubleRegister(rhs, Assembler::FPGpr1), targetReg);
break;
case IR::OpSub:
#if CPU(X86)
if (IR::Const *c = rhs->asConst()) { // Y = X - constant -> Y = X; Y -= [constant-address]
as->moveDouble(as->toDoubleRegister(lhs, targetReg), targetReg);
Assembler::Address addr = as->constantTable().loadValueAddress(c, Assembler::ScratchRegister);
as->subDouble(addr, targetReg);
break;
}
if (IR::Temp *t = rhs->asTemp()) { // Y = X - [temp-memory-address] -> Y = X; Y -= [temp-memory-address]
if (t->kind != IR::Temp::PhysicalRegister) {
as->moveDouble(as->toDoubleRegister(lhs, targetReg), targetReg);
as->subDouble(as->loadTempAddress(t), targetReg);
break;
}
}
#endif
if (rhs->asTemp() && rhs->asTemp()->kind == IR::Temp::PhysicalRegister
&& targetTemp
&& targetTemp->kind == IR::Temp::PhysicalRegister
&& targetTemp->index == rhs->asTemp()->index) { // Y = X - Y -> Tmp = Y; Y = X - Tmp
as->moveDouble(as->toDoubleRegister(rhs, Assembler::FPGpr1), Assembler::FPGpr1);
as->subDouble(as->toDoubleRegister(lhs, Assembler::FPGpr0), Assembler::FPGpr1, targetReg);
break;
}
as->subDouble(as->toDoubleRegister(lhs, Assembler::FPGpr0), as->toDoubleRegister(rhs, Assembler::FPGpr1), targetReg);
break;
case IR::OpDiv:
#if CPU(X86)
if (IR::Const *c = rhs->asConst()) { // Y = X / constant -> Y = X; Y /= [constant-address]
as->moveDouble(as->toDoubleRegister(lhs, targetReg), targetReg);
Assembler::Address addr = as->constantTable().loadValueAddress(c, Assembler::ScratchRegister);
as->divDouble(addr, targetReg);
break;
}
if (IR::Temp *t = rhs->asTemp()) { // Y = X / [temp-memory-address] -> Y = X; Y /= [temp-memory-address]
if (t->kind != IR::Temp::PhysicalRegister) {
as->moveDouble(as->toDoubleRegister(lhs, targetReg), targetReg);
as->divDouble(as->loadTempAddress(t), targetReg);
break;
}
}
#endif
if (rhs->asTemp() && rhs->asTemp()->kind == IR::Temp::PhysicalRegister
&& targetTemp
&& targetTemp->kind == IR::Temp::PhysicalRegister
&& targetTemp->index == rhs->asTemp()->index) { // Y = X / Y -> Tmp = Y; Y = X / Tmp
as->moveDouble(as->toDoubleRegister(rhs, Assembler::FPGpr1), Assembler::FPGpr1);
as->divDouble(as->toDoubleRegister(lhs, Assembler::FPGpr0), Assembler::FPGpr1, targetReg);
break;
}
as->divDouble(as->toDoubleRegister(lhs, Assembler::FPGpr0), as->toDoubleRegister(rhs, Assembler::FPGpr1), targetReg);
break;
default: {
Q_ASSERT(target->type == IR::BoolType);
Assembler::Jump trueCase = as->branchDouble(false, op, lhs, rhs);
as->storeBool(false, target);
Assembler::Jump done = as->jump();
trueCase.link(as);
as->storeBool(true, target);
done.link(as);
}
return;
}
if (!targetTemp || targetTemp->kind != IR::Temp::PhysicalRegister)
as->storeDouble(targetReg, target);
}