// Copies parameters from where they enter the method (either on stack or in a
// linkage register) to their "home location" where the method body will expect
// to find them (either on stack or in a global register).
//
TR::Instruction *
TR::X86SystemLinkage::copyParametersToHomeLocation(TR::Instruction *cursor)
{
TR::Machine *machine = cg()->machine();
TR::RealRegister *framePointer = machine->getX86RealRegister(TR::RealRegister::vfp);
TR::ResolvedMethodSymbol *bodySymbol = comp()->getJittedMethodSymbol();
ListIterator<TR::ParameterSymbol> paramIterator(&(bodySymbol->getParameterList()));
TR::ParameterSymbol *paramCursor;
const TR::RealRegister::RegNum noReg = TR::RealRegister::NoReg;
TR_ASSERT(noReg == 0, "noReg must be zero so zero-initializing movStatus will work");
TR::MovStatus movStatus[TR::RealRegister::NumRegisters] = {{(TR::RealRegister::RegNum)0,(TR::RealRegister::RegNum)0,(TR_MovDataTypes)0}};
// We must always do the stores first, then the reg-reg copies, then the
// loads, so that we never clobber a register we will need later. However,
// the logic is simpler if we do the loads and stores in the same loop.
// Therefore, we maintain a separate instruction cursor for the loads.
//
// We defer the initialization of loadCursor until we generate the first
// load. Otherwise, if we happen to generate some stores first, then the
// store cursor would get ahead of the loadCursor, and the instructions
// would end up in the wrong order despite our efforts.
//
TR::Instruction *loadCursor = NULL;
// Phase 1: generate RegMem and MemReg movs, and collect information about
// the required RegReg movs.
//
for (paramCursor = paramIterator.getFirst();
paramCursor != NULL;
paramCursor = paramIterator.getNext())
{
int8_t lri = paramCursor->getLinkageRegisterIndex(); // How the parameter enters the method
TR::RealRegister::RegNum ai // Where method body expects to find it
= (TR::RealRegister::RegNum)paramCursor->getAllocatedIndex();
int32_t offset = paramCursor->getParameterOffset(); // Location of the parameter's stack slot
TR_MovDataTypes movDataType = paramMovType(paramCursor); // What sort of MOV instruction does it need?
// Copy the parameter to wherever it should be
//
if (lri == NOT_LINKAGE) // It's on the stack
{
if (ai == NOT_ASSIGNED) // It only needs to be on the stack
{
// Nothing to do
}
else // Method body expects it to be in the ai register
{
if (loadCursor == NULL)
loadCursor = cursor;
if (debug("traceCopyParametersToHomeLocation"))
diagnostic("copyParametersToHomeLocation: Loading %d\n", ai);
// ai := stack
loadCursor = generateRegMemInstruction(
loadCursor,
TR::Linkage::movOpcodes(RegMem, movDataType),
machine->getX86RealRegister(ai),
generateX86MemoryReference(framePointer, offset, cg()),
cg()
);
}
}
else // It's in a linkage register
{
TR::RealRegister::RegNum sourceIndex = getProperties().getArgumentRegister(lri, isFloat(movDataType));
// Copy to the stack if necessary
//
if (ai == NOT_ASSIGNED || hasToBeOnStack(paramCursor))
{
if (comp()->getOption(TR_TraceCG))
traceMsg(comp(), "copyToHomeLocation param %p, linkage reg index %d, allocated index %d, parameter offset %d, hasToBeOnStack %d, parm->isParmHasToBeOnStack() %d.\n", paramCursor, lri, ai, offset, hasToBeOnStack(paramCursor), paramCursor->isParmHasToBeOnStack());
if (debug("traceCopyParametersToHomeLocation"))
diagnostic("copyParametersToHomeLocation: Storing %d\n", sourceIndex);
// stack := lri
cursor = generateMemRegInstruction(
cursor,
TR::Linkage::movOpcodes(MemReg, movDataType),
generateX86MemoryReference(framePointer, offset, cg()),
machine->getX86RealRegister(sourceIndex),
cg()
);
}
// Copy to the ai register if necessary
//
if (ai != NOT_ASSIGNED && ai != sourceIndex)
{
// This parameter needs a RegReg move. We don't know yet whether
// we need the value in the target register, so for now we just
// remember that we need to do this and keep going.
//
TR_ASSERT(movStatus[ai ].sourceReg == noReg, "Each target reg must have only one source");
TR_ASSERT(movStatus[sourceIndex].targetReg == noReg, "Each source reg must have only one target");
if (debug("traceCopyParametersToHomeLocation"))
diagnostic("copyParametersToHomeLocation: Planning to move %d to %d\n", sourceIndex, ai);
movStatus[ai].sourceReg = sourceIndex;
movStatus[sourceIndex].targetReg = ai;
movStatus[sourceIndex].outgoingDataType = movDataType;
}
if (debug("traceCopyParametersToHomeLocation") && ai == sourceIndex)
{
diagnostic("copyParametersToHomeLocation: Parameter #%d already in register %d\n", lri, ai);
}
}
}
// Phase 2: Iterate through the parameters again to insert the RegReg moves.
//
for (paramCursor = paramIterator.getFirst();
paramCursor != NULL;
paramCursor = paramIterator.getNext())
{
if (paramCursor->getLinkageRegisterIndex() == NOT_LINKAGE)
continue;
const TR::RealRegister::RegNum paramReg =
getProperties().getArgumentRegister(paramCursor->getLinkageRegisterIndex(), isFloat(paramMovType(paramCursor)));
if (movStatus[paramReg].targetReg == 0)
{
// This parameter does not need to be copied anywhere
if (debug("traceCopyParametersToHomeLocation"))
diagnostic("copyParametersToHomeLocation: Not moving %d\n", paramReg);
}
else
{
if (debug("traceCopyParametersToHomeLocation"))
diagnostic("copyParametersToHomeLocation: Preparing to move %d\n", paramReg);
// If a mov's target register is the source for another mov, we need
// to do that other mov first. The idea is to find the end point of
// the chain of movs starting with paramReg and ending with a
// register whose current value is not needed; then do that chain of
// movs in reverse order.
//
TR_ASSERT(noReg == 0, "noReg must be zero (not %d) for zero-filled initialization to work", noReg);
TR::RealRegister::RegNum regCursor;
// Find the last target in the chain
//
regCursor = movStatus[paramReg].targetReg;
while(movStatus[regCursor].targetReg != noReg)
{
// Haven't found the end yet
regCursor = movStatus[regCursor].targetReg;
TR_ASSERT(regCursor != paramReg, "Can't yet handle cyclic dependencies");
// TODO:AMD64 Use scratch register to break cycles
// A properly-written pickRegister should never
// cause cycles to occur in the first place. However, we may want
// to consider adding cycle-breaking logic so that (1) pickRegister
// has more flexibility, and (2) we're more robust against
// otherwise harmless bugs in pickRegister.
}
// Work our way backward along the chain, generating all the necessary movs
//
while(movStatus[regCursor].sourceReg != noReg)
{
TR::RealRegister::RegNum source = movStatus[regCursor].sourceReg;
if (debug("traceCopyParametersToHomeLocation"))
diagnostic("copyParametersToHomeLocation: Moving %d to %d\n", source, regCursor);
// regCursor := regCursor.sourceReg
cursor = generateRegRegInstruction(
cursor,
TR::Linkage::movOpcodes(RegReg, movStatus[source].outgoingDataType),
machine->getX86RealRegister(regCursor),
machine->getX86RealRegister(source),
cg()
);
// Update movStatus as we go so we don't generate redundant movs
movStatus[regCursor].sourceReg = noReg;
movStatus[source ].targetReg = noReg;
// Continue with the next register in the chain
regCursor = source;
}
}
}
// Return the last instruction we inserted, whether or not it was a load.
//
return loadCursor? loadCursor : cursor;
}
void
TR::AMD64ABILinkage::mapIncomingParms(
TR::ResolvedMethodSymbol *method,
uint32_t &stackIndex)
{
ListIterator<TR::ParameterSymbol> parameterIterator(&method->getParameterList());
TR::ParameterSymbol *parmCursor = parameterIterator.getFirst();
if (!parmCursor) return;
if (parmCursor->getLinkageRegisterIndex() < 0)
{
copyLinkageInfoToParameterSymbols();
}
// 1st: handle parameters which are passed through stack
//
TR::X86SystemLinkage::mapIncomingParms(method);
// 2nd: handle parameters which are passed through linkage registers, but are
// not assigned any register after RA (or say, by their first usage point,
// a MOV is needed to load it from stack to register).
//
// AMD64 SysV ABI says that: a parameter is placed either in registers or
// pushed on the stack, but can't take both. So, for parms passed through
// linkage registers but don't have physical registers assigned after RA,
// we will allocate stack space in local variable region.
//
for (parmCursor = parameterIterator.getFirst(); parmCursor; parmCursor = parameterIterator.getNext())
{
if ((parmCursor->getLinkageRegisterIndex() >= 0) && (parmCursor->getAllocatedIndex() < 0 || hasToBeOnStack(parmCursor)))
{
uint32_t align = getAlignment(parmCursor->getDataType());
uint32_t alignMinus1 = (align <= AMD64_STACK_SLOT_SIZE) ? (AMD64_STACK_SLOT_SIZE - 1) : (align - 1);
uint32_t pos = -stackIndex;
pos += parmCursor->getSize();
pos = (pos + alignMinus1) & (~alignMinus1);
stackIndex = -pos;
parmCursor->setParameterOffset(stackIndex);
if (comp()->getOption(TR_TraceCG))
traceMsg(comp(), "mapIncomingParms setParameterOffset %d for param symbol (reg param without home location) %p, hasToBeOnStack() %d\n", parmCursor->getParameterOffset(), parmCursor, hasToBeOnStack(parmCursor));
}
else if (parmCursor->getLinkageRegisterIndex() >=0 && parmCursor->getAllocatedIndex() >= 0)
{
//parmCursor->setDontHaveStackSlot(0); // this is a hack , so as we could print stack layout table in createPrologue
if (comp()->getOption(TR_TraceCG))
traceMsg(comp(), "mapIncomingParms no need to set parm %p, for it has got register %d assigned\n", parmCursor, parmCursor->getAllocatedIndex());
}
}
}
void
TR::ARM64SystemLinkage::createPrologue(TR::Instruction *cursor, List<TR::ParameterSymbol> &parmList)
{
TR::CodeGenerator *codeGen = cg();
TR::Machine *machine = codeGen->machine();
TR::ResolvedMethodSymbol *bodySymbol = comp()->getJittedMethodSymbol();
const TR::ARM64LinkageProperties& properties = getProperties();
TR::RealRegister *sp = machine->getRealRegister(properties.getStackPointerRegister());
TR::Node *firstNode = comp()->getStartTree()->getNode();
// allocate stack space
uint32_t frameSize = (uint32_t)codeGen->getFrameSizeInBytes();
if (constantIsUnsignedImm12(frameSize))
{
cursor = generateTrg1Src1ImmInstruction(codeGen, TR::InstOpCode::subimmx, firstNode, sp, sp, frameSize, cursor);
}
else
{
TR_UNIMPLEMENTED();
}
// save link register (x30)
if (machine->getLinkRegisterKilled())
{
TR::MemoryReference *stackSlot = new (trHeapMemory()) TR::MemoryReference(sp, 0, codeGen);
cursor = generateMemSrc1Instruction(cg(), TR::InstOpCode::strimmx, firstNode, stackSlot, machine->getRealRegister(TR::RealRegister::x30), cursor);
}
// spill argument registers
int32_t nextIntArgReg = 0;
int32_t nextFltArgReg = 0;
ListIterator<TR::ParameterSymbol> parameterIterator(&parmList);
for (TR::ParameterSymbol *parameter = parameterIterator.getFirst();
parameter != NULL && (nextIntArgReg < getProperties().getNumIntArgRegs() || nextFltArgReg < getProperties().getNumFloatArgRegs());
parameter = parameterIterator.getNext())
{
TR::MemoryReference *stackSlot = new (trHeapMemory()) TR::MemoryReference(sp, parameter->getParameterOffset(), codeGen);
TR::InstOpCode::Mnemonic op;
switch (parameter->getDataType())
{
case TR::Int8:
case TR::Int16:
case TR::Int32:
case TR::Int64:
case TR::Address:
if (nextIntArgReg < getProperties().getNumIntArgRegs())
{
op = (parameter->getSize() == 8) ? TR::InstOpCode::strimmx : TR::InstOpCode::strimmw;
cursor = generateMemSrc1Instruction(cg(), op, firstNode, stackSlot, machine->getRealRegister((TR::RealRegister::RegNum)(TR::RealRegister::x0 + nextIntArgReg)), cursor);
nextIntArgReg++;
}
else
{
nextIntArgReg = getProperties().getNumIntArgRegs() + 1;
}
break;
case TR::Float:
case TR::Double:
if (nextFltArgReg < getProperties().getNumFloatArgRegs())
{
op = (parameter->getSize() == 8) ? TR::InstOpCode::vstrimmd : TR::InstOpCode::vstrimms;
cursor = generateMemSrc1Instruction(cg(), op, firstNode, stackSlot, machine->getRealRegister((TR::RealRegister::RegNum)(TR::RealRegister::v0 + nextFltArgReg)), cursor);
nextFltArgReg++;
}
else
{
nextFltArgReg = getProperties().getNumFloatArgRegs() + 1;
}
break;
case TR::Aggregate:
TR_ASSERT(false, "Function parameters of aggregate types are not currently supported on AArch64.");
break;
default:
TR_ASSERT(false, "Unknown parameter type.");
}
}
// save callee-saved registers
uint32_t offset = bodySymbol->getLocalMappingCursor();
for (int r = TR::RealRegister::x19; r <= TR::RealRegister::x28; r++)
{
TR::RealRegister *rr = machine->getRealRegister((TR::RealRegister::RegNum)r);
if (rr->getHasBeenAssignedInMethod())
{
TR::MemoryReference *stackSlot = new (trHeapMemory()) TR::MemoryReference(sp, offset, codeGen);
cursor = generateMemSrc1Instruction(cg(), TR::InstOpCode::strimmx, firstNode, stackSlot, rr, cursor);
offset += 8;
}
}
for (int r = TR::RealRegister::v8; r <= TR::RealRegister::v15; r++)
{
TR::RealRegister *rr = machine->getRealRegister((TR::RealRegister::RegNum)r);
if (rr->getHasBeenAssignedInMethod())
{
TR::MemoryReference *stackSlot = new (trHeapMemory()) TR::MemoryReference(sp, offset, codeGen);
cursor = generateMemSrc1Instruction(cg(), TR::InstOpCode::vstrimmd, firstNode, stackSlot, rr, cursor);
offset += 8;
}
}
}
void TR::ARMSystemLinkage::createPrologue(TR::Instruction *cursor)
{
TR::CodeGenerator *codeGen = cg();
const TR::ARMLinkageProperties& properties = getProperties();
TR::Machine *machine = codeGen->machine();
TR::ResolvedMethodSymbol* bodySymbol = comp()->getJittedMethodSymbol();
TR::Node *firstNode = comp()->getStartTree()->getNode();
TR::RealRegister *stackPtr = machine->getRealRegister(properties.getStackPointerRegister());
// Entry breakpoint
//
if (comp()->getOption(TR_EntryBreakPoints))
{
cursor = new (trHeapMemory()) TR::Instruction(cursor, ARMOp_bad, firstNode, cg());
}
// allocate stack space
auto frameSize = codeGen->getFrameSizeInBytes();
cursor = generateTrg1Src1ImmInstruction(codeGen, ARMOp_sub, firstNode, stackPtr, stackPtr, frameSize, 0, cursor);
// spill argument registers
auto nextIntArgReg = 0;
auto nextFltArgReg = 0;
ListIterator<TR::ParameterSymbol> parameterIterator(&bodySymbol->getParameterList());
for (TR::ParameterSymbol *parameter = parameterIterator.getFirst();
parameter!=NULL && (nextIntArgReg < getProperties().getNumIntArgRegs() || nextFltArgReg < getProperties().getNumFloatArgRegs());
parameter=parameterIterator.getNext())
{
auto *stackSlot = new (trHeapMemory()) TR::MemoryReference(stackPtr, parameter->getParameterOffset(), codeGen);
switch (parameter->getDataType())
{
case TR::Int8:
case TR::Int16:
case TR::Int32:
case TR::Address:
if (nextIntArgReg < getProperties().getNumIntArgRegs())
{
cursor = generateMemSrc1Instruction(cg(), ARMOp_str, firstNode, stackSlot, machine->getRealRegister((TR::RealRegister::RegNum)(TR::RealRegister::gr0 + nextIntArgReg)), cursor);
nextIntArgReg++;
}
else
{
nextIntArgReg = getProperties().getNumIntArgRegs() + 1;
}
break;
case TR::Int64:
nextIntArgReg += nextIntArgReg & 0x1; // round to next even number
if (nextIntArgReg + 1 < getProperties().getNumIntArgRegs())
{
cursor = generateMemSrc1Instruction(cg(), ARMOp_str, firstNode, stackSlot, machine->getRealRegister((TR::RealRegister::RegNum)(TR::RealRegister::gr0 + nextIntArgReg)), cursor);
stackSlot = new (trHeapMemory()) TR::MemoryReference(stackPtr, parameter->getParameterOffset() + 4, codeGen);
cursor = generateMemSrc1Instruction(cg(), ARMOp_str, firstNode, stackSlot, machine->getRealRegister((TR::RealRegister::RegNum)(TR::RealRegister::gr0 + nextIntArgReg + 1)), cursor);
nextIntArgReg += 2;
}
else
{
nextIntArgReg = getProperties().getNumIntArgRegs() + 1;
}
break;
case TR::Float:
comp()->failCompilation<UnsupportedParameterType>("Compiling methods with a single precision floating point parameter is not supported");
break;
case TR::Double:
if (nextFltArgReg < getProperties().getNumFloatArgRegs())
{
cursor = generateMemSrc1Instruction(cg(), ARMOp_fstd, firstNode, stackSlot, machine->getRealRegister((TR::RealRegister::RegNum)(TR::RealRegister::fp0 + nextFltArgReg)), cursor);
nextFltArgReg += 1;
}
else
{
nextFltArgReg = getProperties().getNumFloatArgRegs() + 1;
}
break;
case TR::Aggregate:
TR_ASSERT(false, "Function parameters of aggregate types are not currently supported on ARM.");
}
}
// save all preserved registers
for (int r = TR::RealRegister::gr4; r <= TR::RealRegister::gr11; ++r)
{
auto *stackSlot = new (trHeapMemory()) TR::MemoryReference(stackPtr, (TR::RealRegister::gr11 - r + 1)*4 + bodySymbol->getLocalMappingCursor(), codeGen);
cursor = generateMemSrc1Instruction(cg(), ARMOp_str, firstNode, stackSlot, machine->getRealRegister((TR::RealRegister::RegNum)r), cursor);
}
// save link register (r14)
auto *stackSlot = new (trHeapMemory()) TR::MemoryReference(stackPtr, bodySymbol->getLocalMappingCursor(), codeGen);
cursor = generateMemSrc1Instruction(cg(), ARMOp_str, firstNode, stackSlot, machine->getRealRegister(TR::RealRegister::gr14), cursor);
}
TR::Instruction *OMR::Power::Linkage::flushArguments(TR::Instruction *cursor)
{
TR::Machine *machine = self()->machine();
TR::RealRegister *stackPtr = self()->cg()->getStackPointerRegister();
TR::ResolvedMethodSymbol *bodySymbol = self()->comp()->getJittedMethodSymbol();
ListIterator<TR::ParameterSymbol> paramIterator(&(bodySymbol->getParameterList()));
TR::ParameterSymbol *paramCursor = paramIterator.getFirst();
TR::Node *firstNode = self()->comp()->getStartTree()->getNode();
int32_t numIntArgs = 0, numFloatArgs = 0;
const TR::PPCLinkageProperties& properties = self()->getProperties();
while ( (paramCursor!=NULL) &&
( (numIntArgs < properties.getNumIntArgRegs()) ||
(numFloatArgs < properties.getNumFloatArgRegs()) ) )
{
TR::RealRegister *argRegister;
int32_t offset = paramCursor->getParameterOffset();
// If parm is referenced or required to be on stack (i.e. FSD), we have to flush.
bool hasToStoreToStack = paramCursor->isReferencedParameter() || paramCursor->isParmHasToBeOnStack();
switch (paramCursor->getDataType())
{
case TR::Int8:
case TR::Int16:
case TR::Int32:
if (hasToStoreToStack &&
numIntArgs<properties.getNumIntArgRegs())
{
argRegister = machine->getRealRegister(properties.getIntegerArgumentRegister(numIntArgs));
cursor = generateMemSrc1Instruction(self()->cg(), TR::InstOpCode::stw, firstNode,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 4, self()->cg()),
argRegister, cursor);
}
numIntArgs++;
break;
case TR::Address:
if (numIntArgs<properties.getNumIntArgRegs())
{
argRegister = machine->getRealRegister(properties.getIntegerArgumentRegister(numIntArgs));
cursor = generateMemSrc1Instruction(self()->cg(),TR::InstOpCode::Op_st, firstNode,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, TR::Compiler->om.sizeofReferenceAddress(), self()->cg()),
argRegister, cursor);
}
numIntArgs++;
break;
case TR::Int64:
if (hasToStoreToStack &&
numIntArgs<properties.getNumIntArgRegs())
{
argRegister = machine->getRealRegister(properties.getIntegerArgumentRegister(numIntArgs));
if (TR::Compiler->target.is64Bit())
cursor = generateMemSrc1Instruction(self()->cg(),TR::InstOpCode::Op_st, firstNode,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 8, self()->cg()),
argRegister, cursor);
else
{
cursor = generateMemSrc1Instruction(self()->cg(), TR::InstOpCode::stw, firstNode,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 4, self()->cg()),
argRegister, cursor);
if (numIntArgs < properties.getNumIntArgRegs()-1)
{
argRegister = machine->getRealRegister(properties.getIntegerArgumentRegister(numIntArgs+1));
cursor = generateMemSrc1Instruction(self()->cg(), TR::InstOpCode::stw, firstNode,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset+4, 4, self()->cg()),
argRegister, cursor);
}
}
}
if (TR::Compiler->target.is64Bit())
numIntArgs++;
else
numIntArgs+=2;
break;
case TR::Float:
if (hasToStoreToStack &&
numFloatArgs<properties.getNumFloatArgRegs())
{
argRegister = machine->getRealRegister(properties.getFloatArgumentRegister(numFloatArgs));
cursor = generateMemSrc1Instruction(self()->cg(), TR::InstOpCode::stfs, firstNode,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 4, self()->cg()),
argRegister, cursor);
}
numFloatArgs++;
break;
case TR::Double:
if (hasToStoreToStack &&
numFloatArgs<properties.getNumFloatArgRegs())
{
argRegister = machine->getRealRegister(properties.getFloatArgumentRegister(numFloatArgs));
cursor = generateMemSrc1Instruction(self()->cg(), TR::InstOpCode::stfd, firstNode,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 8, self()->cg()),
argRegister, cursor);
}
numFloatArgs++;
break;
}
paramCursor = paramIterator.getNext();
}
return(cursor);
}
TR::Instruction *OMR::Power::Linkage::loadUpArguments(TR::Instruction *cursor)
{
if (!self()->cg()->buildInterpreterEntryPoint())
// would be better to use a different linkage for this purpose
return cursor;
TR::Machine *machine = self()->machine();
TR::RealRegister *stackPtr = self()->cg()->getStackPointerRegister();
TR::ResolvedMethodSymbol *bodySymbol = self()->comp()->getJittedMethodSymbol();
ListIterator<TR::ParameterSymbol> paramIterator(&(bodySymbol->getParameterList()));
TR::ParameterSymbol *paramCursor = paramIterator.getFirst();
TR::Node *firstNode = self()->comp()->getStartTree()->getNode();
int32_t numIntArgs = 0, numFloatArgs = 0;
const TR::PPCLinkageProperties& properties = self()->getProperties();
while ( (paramCursor!=NULL) &&
( (numIntArgs < properties.getNumIntArgRegs()) ||
(numFloatArgs < properties.getNumFloatArgRegs()) ) )
{
TR::RealRegister *argRegister;
int32_t offset = paramCursor->getParameterOffset();
bool hasToLoadFromStack = paramCursor->isReferencedParameter() || paramCursor->isParmHasToBeOnStack();
switch (paramCursor->getDataType())
{
case TR::Int8:
case TR::Int16:
case TR::Int32:
if (hasToLoadFromStack &&
numIntArgs<properties.getNumIntArgRegs())
{
argRegister = machine->getRealRegister(properties.getIntegerArgumentRegister(numIntArgs));
cursor = generateTrg1MemInstruction(self()->cg(), TR::InstOpCode::lwz, firstNode, argRegister,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 4, self()->cg()), cursor);
}
numIntArgs++;
break;
case TR::Address:
if (numIntArgs<properties.getNumIntArgRegs())
{
argRegister = machine->getRealRegister(properties.getIntegerArgumentRegister(numIntArgs));
cursor = generateTrg1MemInstruction(self()->cg(),TR::InstOpCode::Op_load, firstNode, argRegister,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, TR::Compiler->om.sizeofReferenceAddress(), self()->cg()), cursor);
}
numIntArgs++;
break;
case TR::Int64:
if (hasToLoadFromStack &&
numIntArgs<properties.getNumIntArgRegs())
{
argRegister = machine->getRealRegister(properties.getIntegerArgumentRegister(numIntArgs));
if (TR::Compiler->target.is64Bit())
cursor = generateTrg1MemInstruction(self()->cg(), TR::InstOpCode::ld, firstNode, argRegister,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 8, self()->cg()), cursor);
else
{
cursor = generateTrg1MemInstruction(self()->cg(), TR::InstOpCode::lwz, firstNode, argRegister,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 4, self()->cg()), cursor);
if (numIntArgs < properties.getNumIntArgRegs()-1)
{
argRegister = machine->getRealRegister(properties.getIntegerArgumentRegister(numIntArgs+1));
cursor = generateTrg1MemInstruction(self()->cg(), TR::InstOpCode::lwz, firstNode, argRegister,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset+4, 4, self()->cg()), cursor);
}
}
}
if (TR::Compiler->target.is64Bit())
numIntArgs++;
else
numIntArgs+=2;
break;
case TR::Float:
if (hasToLoadFromStack &&
numFloatArgs<properties.getNumFloatArgRegs())
{
argRegister = machine->getRealRegister(properties.getFloatArgumentRegister(numFloatArgs));
cursor = generateTrg1MemInstruction(self()->cg(), TR::InstOpCode::lfs, firstNode, argRegister,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 4, self()->cg()), cursor);
}
numFloatArgs++;
break;
case TR::Double:
if (hasToLoadFromStack &&
numFloatArgs<properties.getNumFloatArgRegs())
{
argRegister = machine->getRealRegister(properties.getFloatArgumentRegister(numFloatArgs));
cursor = generateTrg1MemInstruction(self()->cg(), TR::InstOpCode::lfd, firstNode, argRegister,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 8, self()->cg()), cursor);
}
numFloatArgs++;
break;
}
paramCursor = paramIterator.getNext();
}
return(cursor);
}
TR::Instruction *OMR::Power::Linkage::saveArguments(TR::Instruction *cursor, bool fsd, bool saveOnly,
List<TR::ParameterSymbol> &parmList)
{
#define REAL_REGISTER(ri) machine->getRealRegister(ri)
#define REGNUM(ri) ((TR::RealRegister::RegNum)(ri))
const TR::PPCLinkageProperties& properties = self()->getProperties();
TR::Machine *machine = self()->machine();
TR::RealRegister *stackPtr = self()->cg()->getStackPointerRegister();
TR::ResolvedMethodSymbol *bodySymbol = self()->comp()->getJittedMethodSymbol();
ListIterator<TR::ParameterSymbol> paramIterator(&parmList);
TR::ParameterSymbol *paramCursor;
TR::Node *firstNode = self()->comp()->getStartTree()->getNode();
TR_BitVector freeScratchable;
int32_t busyMoves[3][64];
int32_t busyIndex = 0, i1;
bool all_saved = false;
// the freeScratchable structure will not be used when saveOnly == true
// no additional conditions were added with the intention of keeping the code easier to read
// and not full of if conditions
freeScratchable.init(TR::RealRegister::LastFPR + 1, self()->trMemory());
// first, consider all argument registers free
for (i1=TR::RealRegister::FirstGPR; i1<=TR::RealRegister::LastFPR; i1++)
{
if (!properties.getReserved(REGNUM(i1)))
{
freeScratchable.set(i1);
}
}
// second, go through all parameters and reset registers that are actually used
for (paramCursor=paramIterator.getFirst(); paramCursor!=NULL; paramCursor=paramIterator.getNext())
{
int32_t lri = paramCursor->getLinkageRegisterIndex();
TR::DataType type = paramCursor->getType();
if (lri >= 0)
{
TR::RealRegister::RegNum regNum;
bool twoRegs = (TR::Compiler->target.is32Bit() && type.isInt64() && lri < properties.getNumIntArgRegs()-1);
if (!type.isFloatingPoint())
{
regNum = properties.getIntegerArgumentRegister(lri);
if (paramCursor->isReferencedParameter()) freeScratchable.reset(regNum);
if (twoRegs)
if (paramCursor->isReferencedParameter()) freeScratchable.reset(regNum+1);
}
else
{
regNum = properties.getFloatArgumentRegister(lri);
if (paramCursor->isReferencedParameter()) freeScratchable.reset(regNum);
if (twoRegs)
if (paramCursor->isReferencedParameter()) freeScratchable.reset(regNum+1);
}
}
}
for (paramCursor=paramIterator.getFirst(); paramCursor!=NULL; paramCursor=paramIterator.getNext())
{
int32_t lri = paramCursor->getLinkageRegisterIndex();
int32_t ai = paramCursor->getAllocatedIndex();
int32_t offset = self()->calculateParameterRegisterOffset(paramCursor->getParameterOffset(), *paramCursor);
TR::DataType type = paramCursor->getType();
int32_t dtype = type.getDataType();
// TODO: Is there an accurate assume to insert here ?
if (lri >= 0)
{
if (!paramCursor->isReferencedParameter() && !paramCursor->isParmHasToBeOnStack()) continue;
TR::RealRegister::RegNum regNum;
bool twoRegs = (TR::Compiler->target.is32Bit() && type.isInt64() && lri < properties.getNumIntArgRegs()-1);
if (type.isFloatingPoint())
regNum = properties.getFloatArgumentRegister(lri);
else
regNum = properties.getIntegerArgumentRegister(lri);
// Do not save arguments to the stack if in Full Speed Debug and saveOnly is not set.
// If not in Full Speed Debug, the arguments will be saved.
if (((ai<0 || self()->hasToBeOnStack(paramCursor)) && !fsd) || (fsd && saveOnly))
{
switch (dtype)
{
case TR::Int8:
case TR::Int16:
case TR::Int32:
{
TR::InstOpCode::Mnemonic op = TR::InstOpCode::stw;
if (!all_saved) cursor = generateMemSrc1Instruction(self()->cg(), op, firstNode,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 4, self()->cg()), REAL_REGISTER(regNum), cursor);
}
break;
case TR::Address:
if (!all_saved) cursor = generateMemSrc1Instruction(self()->cg(),TR::InstOpCode::Op_st, firstNode,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, TR::Compiler->om.sizeofReferenceAddress(), self()->cg()), REAL_REGISTER(regNum), cursor);
break;
case TR::Int64:
if (!all_saved) cursor = generateMemSrc1Instruction(self()->cg(),TR::InstOpCode::Op_st, firstNode,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, TR::Compiler->om.sizeofReferenceAddress(), self()->cg()), REAL_REGISTER(regNum), cursor);
if (twoRegs)
{
if (!all_saved) cursor = generateMemSrc1Instruction(self()->cg(), TR::InstOpCode::stw, firstNode,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset+4, 4, self()->cg()),
REAL_REGISTER(REGNUM(regNum+1)), cursor);
if (ai<0)
freeScratchable.set(regNum+1);
}
break;
case TR::Float:
cursor = generateMemSrc1Instruction(self()->cg(), TR::InstOpCode::stfs, firstNode,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 4, self()->cg()),
REAL_REGISTER(regNum), cursor);
break;
case TR::Double:
cursor = generateMemSrc1Instruction(self()->cg(), TR::InstOpCode::stfd, firstNode,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 8, self()->cg()),
REAL_REGISTER(regNum), cursor);
break;
default:
TR_ASSERT(false, "assertion failure");
break;
}
if (ai<0)
freeScratchable.set(regNum);
}
// Global register is allocated to this argument.
// Don't process if in Full Speed Debug and saveOnly is set
if (ai>=0 && (!fsd || !saveOnly))
{
if (regNum != ai) // Equal assignment: do nothing
{
if (freeScratchable.isSet(ai))
{
cursor = generateTrg1Src1Instruction(self()->cg(),
(type.isFloatingPoint()) ? TR::InstOpCode::fmr:TR::InstOpCode::mr,
firstNode, REAL_REGISTER(REGNUM(ai)), REAL_REGISTER(regNum), cursor);
freeScratchable.reset(ai);
freeScratchable.set(regNum);
}
else // The status of target global register is unclear (i.e. it is a arg reg)
{
busyMoves[0][busyIndex] = regNum;
busyMoves[1][busyIndex] = ai;
busyMoves[2][busyIndex] = 0;
busyIndex++;
}
}
if (TR::Compiler->target.is32Bit() && type.isInt64())
{
int32_t aiLow = paramCursor->getAllocatedLow();
if (!twoRegs) // Low part needs to come from memory
{
offset += 4; // We are dealing with the low part
if (freeScratchable.isSet(aiLow))
{
cursor = generateTrg1MemInstruction(self()->cg(), TR::InstOpCode::lwz, firstNode, REAL_REGISTER(REGNUM(aiLow)),
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 4, self()->cg()), cursor);
freeScratchable.reset(aiLow);
}
else
{
busyMoves[0][busyIndex] = offset;
busyMoves[1][busyIndex] = aiLow;
busyMoves[2][busyIndex] = 1;
busyIndex++;
}
}
else if (regNum+1 != aiLow) // Low part needs to be moved
{
if (freeScratchable.isSet(aiLow))
{
cursor = generateTrg1Src1Instruction(self()->cg(), TR::InstOpCode::mr,
firstNode, REAL_REGISTER(REGNUM(aiLow)),
REAL_REGISTER(REGNUM(regNum+1)), cursor);
freeScratchable.reset(aiLow);
freeScratchable.set(regNum+1);
}
else
{
busyMoves[0][busyIndex] = regNum+1;
busyMoves[1][busyIndex] = aiLow;
busyMoves[2][busyIndex] = 0;
busyIndex++;
}
}
}
}
}
// Don't process if in Full Speed Debug and saveOnly is set
else if (ai >= 0 && (!fsd || !saveOnly)) // lri<0: arg needs to come from memory
{
switch (dtype)
{
case TR::Int8:
case TR::Int16:
case TR::Int32:
if (freeScratchable.isSet(ai))
{
cursor = generateTrg1MemInstruction(self()->cg(), TR::InstOpCode::lwz, firstNode, REAL_REGISTER(REGNUM(ai)),
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 4, self()->cg()), cursor);
freeScratchable.reset(ai);
}
else
{
busyMoves[0][busyIndex] = offset;
busyMoves[1][busyIndex] = ai;
busyMoves[2][busyIndex] = 1;
busyIndex++;
}
break;
case TR::Address:
if (freeScratchable.isSet(ai))
{
cursor = generateTrg1MemInstruction(self()->cg(),TR::InstOpCode::Op_load, firstNode, REAL_REGISTER(REGNUM(ai)),
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, TR::Compiler->om.sizeofReferenceAddress(), self()->cg()), cursor);
freeScratchable.reset(ai);
}
else
{
busyMoves[0][busyIndex] = offset;
busyMoves[1][busyIndex] = ai;
if (TR::Compiler->target.is64Bit())
busyMoves[2][busyIndex] = 2;
else
busyMoves[2][busyIndex] = 1;
busyIndex++;
}
break;
case TR::Int64:
if (TR::Compiler->target.is64Bit())
{
if (freeScratchable.isSet(ai))
{
cursor = generateTrg1MemInstruction(self()->cg(), TR::InstOpCode::ld, firstNode, REAL_REGISTER(REGNUM(ai)),
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 8, self()->cg()), cursor);
freeScratchable.reset(ai);
}
else
{
busyMoves[0][busyIndex] = offset;
busyMoves[1][busyIndex] = ai;
busyMoves[2][busyIndex] = 2;
busyIndex++;
}
}
else // 32-bit
{
if (freeScratchable.isSet(ai))
{
cursor = generateTrg1MemInstruction(self()->cg(), TR::InstOpCode::lwz, firstNode, REAL_REGISTER(REGNUM(ai)),
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 4, self()->cg()), cursor);
freeScratchable.reset(ai);
}
else
{
busyMoves[0][busyIndex] = offset;
busyMoves[1][busyIndex] = ai;
busyMoves[2][busyIndex] = 1;
busyIndex++;
}
ai = paramCursor->getAllocatedLow();
if (freeScratchable.isSet(ai))
{
cursor = generateTrg1MemInstruction(self()->cg(), TR::InstOpCode::lwz, firstNode, REAL_REGISTER(REGNUM(ai)),
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset+4, 4, self()->cg()), cursor);
freeScratchable.reset(ai);
}
else
{
busyMoves[0][busyIndex] = offset+4;
busyMoves[1][busyIndex] = ai;
busyMoves[2][busyIndex] = 1;
busyIndex++;
}
}
break;
case TR::Float:
if (freeScratchable.isSet(ai))
{
cursor = generateTrg1MemInstruction(self()->cg(), TR::InstOpCode::lfs, firstNode, REAL_REGISTER(REGNUM(ai)),
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 4, self()->cg()), cursor);
freeScratchable.reset(ai);
}
else
{
busyMoves[0][busyIndex] = offset;
busyMoves[1][busyIndex] = ai;
busyMoves[2][busyIndex] = 3;
busyIndex++;
}
break;
case TR::Double:
if (freeScratchable.isSet(ai))
{
cursor = generateTrg1MemInstruction(self()->cg(), TR::InstOpCode::lfd, firstNode, REAL_REGISTER(REGNUM(ai)),
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 8, self()->cg()), cursor);
freeScratchable.reset(ai);
}
else
{
busyMoves[0][busyIndex] = offset;
busyMoves[1][busyIndex] = ai;
busyMoves[2][busyIndex] = 4;
busyIndex++;
}
break;
default:
break;
}
}
}
if (!fsd || !saveOnly)
{
bool freeMore = true;
int32_t numMoves = busyIndex;
while (freeMore && numMoves>0)
{
freeMore = false;
for (i1=0; i1<busyIndex; i1++)
{
int32_t source = busyMoves[0][i1];
int32_t target = busyMoves[1][i1];
if (!(target<0) && freeScratchable.isSet(target))
{
switch(busyMoves[2][i1])
{
case 0:
cursor = generateTrg1Src1Instruction(self()->cg(), (source<=TR::RealRegister::LastGPR)?TR::InstOpCode::mr:TR::InstOpCode::fmr,
firstNode, REAL_REGISTER(REGNUM(target)), REAL_REGISTER(REGNUM(source)), cursor);
freeScratchable.set(source);
break;
case 1:
cursor = generateTrg1MemInstruction(self()->cg(), TR::InstOpCode::lwz, firstNode, REAL_REGISTER(REGNUM(target)),
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, source, 4, self()->cg()), cursor);
break;
case 2:
cursor = generateTrg1MemInstruction(self()->cg(), TR::InstOpCode::ld, firstNode, REAL_REGISTER(REGNUM(target)),
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, source, 8, self()->cg()), cursor);
break;
case 3:
cursor = generateTrg1MemInstruction(self()->cg(), TR::InstOpCode::lfs, firstNode, REAL_REGISTER(REGNUM(target)),
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, source, 4, self()->cg()), cursor);
break;
case 4:
cursor = generateTrg1MemInstruction(self()->cg(), TR::InstOpCode::lfd, firstNode, REAL_REGISTER(REGNUM(target)),
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, source, 8, self()->cg()), cursor);
break;
}
freeScratchable.reset(target);
freeMore = true;
busyMoves[0][i1] = busyMoves[1][i1] = -1;
numMoves--;
}
}
}
TR_ASSERT(numMoves<=0, "Circular argument register dependency can and should be avoided.");
}
return(cursor);
}