static void dc_callvm_argFloat_mips_o32(DCCallVM* in_self, DCfloat x)
{
DCCallVM_mips_o32* self = (DCCallVM_mips_o32*)in_self;
dcVecAppend(&self->mVecHead, &x, sizeof(DCfloat) );
if (self->mArgCount < 2) {
#if defined(DC__Endian_LITTLE)
self->mRegData.u[self->mArgCount].f[0] = x;
#else
self->mRegData.u[self->mArgCount].f[1] = x;
#endif
#if 0
self->mRegData.u[self->mArgCount].f[1] = x;
call kernel
mips:
lwc1 $f12, 4($5) <--- byte offset 4
lwc1 $f13, 0($5)
lwc1 $f14, 12($5) <--- byte offset 12
lwc1 $f15, 8($5)
mipsel:
lwc1 $f12, 0($5) <--- byte offset 4
lwc1 $f13, 4($5)
lwc1 $f14, 8($5) <--- byte offset 12
lwc1 $f15, 12($5)
#if defined(DC__Endian_LITTLE)
/* index 0 and 2 */
self->mRegData.floats[self->mArgCount*2] = x;
#else
/* index 1 and 3 */
self->mRegData.floats[self->mArgCount*2+1] = x;
#endif
#endif
}
asm void
bsp_flash_init( void )
{
extern uint32_t _internal_ram_end;
enum { BIUCR = 0xC3F8801Cul };
nofralloc
mflr r7 /**< no stack available here */
lis r5, __set_value@h /**< __set_value fcall - source */
ori r5, r5, __set_value@l
/**< __set_value fcall - dest */
lis r6, _internal_ram_end@h
ori r6, r6, (_internal_ram_end-sizeof(__set_value))@l
/**< unrolled copy */
lwz r4, 0(r5) /**< __set_value[0] */
stw r4, 0(r6)
lwz r4, 4(r5) /**< __set_value[1] */
stw r4, 4(r6)
lwz r4, 8(r5) /**< __set_value[2] */
stw r4, 8(r6)
lwz r4, 12(r5) /**< __set_value[3] */
stw r4, 12(r6)
lis r4, BIUCR@h /**< BIUCR (base) */
ori r4, r4, BIUCR@l /* */
lis r3, 0x0001 /**< 82MHz operation, I+D prefetch*/
ori r3, r3, 0x6B55 /* enabled */
xor r5, r5, r5 /**< BIUCR+0=BIUCR */
mtlr r6 /**< addr of __set_value() */
blrl
lis r3, (3<<14) /**< 3 buf inst, 1 buf data */
li r5, 8 /**< BIUCR+8=BIUCR2 */
mtlr r6 /**< addr of __set_value() */
blrl
xor r3, r3, r3 /**< NO prefetching on Bank1 */
li r5, 12 /**< BIUCR+12=PFCR3 */
mtlr r6 /**< addr of __set_value() */
blrl
mtlr r7
blr
}
static void dc_callvm_argFloat_mips_o32(DCCallVM* in_self, DCfloat x)
{
DCCallVM_mips_o32* self = (DCCallVM_mips_o32*)in_self;
dcVecAppend(&self->mVecHead, &x, sizeof(DCfloat));
#if defined(DC__ABI_HARDFLOAT)
if (self->mArgCount < 2) {
/* @@@ unsure if we should zero init, here; seems to work as-is */
# if defined(DC__Endian_LITTLE)
self->mRegData.u[self->mArgCount].f[0] = x;
# else
self->mRegData.u[self->mArgCount].f[1] = x; // floats in regs always right justified
# endif
# if 0
self->mRegData.u[self->mArgCount].f[1] = x;
call kernel
mips:
lwc1 $f12, 4($5) <--- byte offset 4
lwc1 $f13, 0($5)
lwc1 $f14, 12($5) <--- byte offset 12
lwc1 $f15, 8($5)
mipsel:
lwc1 $f12, 0($5) <--- byte offset 4
lwc1 $f13, 4($5)
lwc1 $f14, 8($5) <--- byte offset 12
lwc1 $f15, 12($5)
# if defined(DC__Endian_LITTLE)
/* index 0 and 2 */
self->mRegData.floats[self->mArgCount*2] = x;
# else
/* index 1 and 3 */
self->mRegData.floats[self->mArgCount*2+1] = x;
# endif
# endif
}
// -----------------------------------------------------------------------
// This function handles IRQ's for the P6502 by jumping to the address
// at 0xFFFE.
asm void N6502::_IRQ()
{
lbz r5,_F(r3)
andi. r7,r5,I_FLAG
bnelr
// save regs
stw r24,-4(SP)
stw r25,-8(SP)
stw r27,-12(SP)
lwz r8,_MEM_X(r3)
lbz r6,_SP(r3) // setup regs for _PUSHB macro
lwz r27,RAMSeg1_Ind(r8)
addi r25,r6,0x100
lhz r24,_PC(r3)
li r9,D_FLAG
srwi r7,r24,8 // push pc,flags
li r8,B_FLAG
_pushb (r7)
not r8,r8
not r9,r9
_pushb (r24)
and r6,r5,r8
/*
* General Pascal library routines
*/
{ 2, "_ROUND\n",
" movd (sp)+,r0\n\
cvtrdl r0,r0\n"
},
{ 2, "_TRUNC\n",
" movd (sp)+,r0\n\
cvtdl r0,r0\n"
},
{ 1, "_ACTFILE\n",
" movl (sp)+,r1\n\
movl 12(r1),r0\n"
},
{ 2, "_FCALL\n",
" movl (sp)+,r5\n\
movl (sp),r0\n\
movc3 4(r0),__disply+8,(r5)\n\
movl (sp)+,r0\n\
movc3 4(r0),8(r0),__disply+8\n"
},
{ 2, "_FRTN\n",
" movl (sp)+,r0\n\
movl (sp)+,r5\n\
movc3 4(r0),(r5),__disply+8\n"
},
