/** adc_init * \brief initialize and calibrate ADC0 module * \brief 48MHz IPBus clock; ADC clock = 48M/2/8 = 3MHz * \brief Total conversion time: 56N+4ADCK * \brief given sampling rate Fs = 6.4K, 156us/sample, 156*3= 468 ADCK * \author FSL * \param none * \return none * \warning assumes 48MHz IPBus clock */ void adc_init(void) { uint8_t cal_ok; SIM_SCGC6 |= SIM_SCGC6_ADC0_MASK; #ifdef CMSIS NVIC_EnableIRQ(ADC0_IRQn); #else enable_irq(INT_ADC0 - 16); #endif /* 48MHz IPBus clock * ADC clock = 48M/2/8 = 3MHz * Total conversion time: 56N+4ADCK * Given sampling rate Fs = 6.4K, 156us/sample, 156*3= 468 ADCK * the maximum h/w average number = 8 * use h/w average number = 4 * Total conversion time: 56*4+4 = 228 ADC clocks,76us * There are 468-228 = 240 ADC clocks (ie. 80us) free for post processing */ // Initialize ADC0 // Do calibration first with 32 h/w averages Master_Adc_Config.CONFIG1 = ADLPC_NORMAL | ADC_CFG1_ADIV(ADIV_8) | ADLSMP_LONG | ADC_CFG1_MODE(MODE_16) | ADC_CFG1_ADICLK(ADICLK_BUS_2); Master_Adc_Config.CONFIG2 = MUXSEL_ADCA | ADACKEN_ENABLED | ADHSC_HISPEED | ADC_CFG2_ADLSTS(ADLSTS_20) ; Master_Adc_Config.COMPARE1 = 0x1234u ; Master_Adc_Config.COMPARE2 = 0x5678u ; Master_Adc_Config.STATUS2 = ADTRG_SW | ACFE_DISABLED | ACFGT_GREATER | ACREN_ENABLED | DMAEN_DISABLED | ADC_SC2_REFSEL(REFSEL_EXT); Master_Adc_Config.STATUS3 = CAL_OFF | ADCO_SINGLE | AVGE_ENABLED | ADC_SC3_AVGS(AVGS_32); // Master_Adc_Config.PGA = PGAEN_DISABLED | PGACHP_NOCHOP | PGALP_NORMAL | ADC_PGA_PGAG(PGAG_64); Master_Adc_Config.STATUS1A = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(31); Master_Adc_Config.STATUS1B = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(31); ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config); // config ADC cal_ok = ADC_Cal(ADC0_BASE_PTR); // do the calibration if (cal_ok != 0) printf("ADC calibration error"); ADC_Read_Cal(ADC0_BASE_PTR,&CalibrationStore[1]); // store the cal // Now do normal ADC configuration with 4 h/w averages and h/w trigger from PDB Master_Adc_Config.CONFIG1 = ADLPC_NORMAL | ADC_CFG1_ADIV(ADIV_8) | ADLSMP_LONG | ADC_CFG1_MODE(MODE_12) | ADC_CFG1_ADICLK(ADICLK_BUS_2); Master_Adc_Config.CONFIG2 = MUXSEL_ADCB | ADACKEN_ENABLED | ADHSC_HISPEED | ADC_CFG2_ADLSTS(ADLSTS_20) ; Master_Adc_Config.COMPARE1 = 0x1234u ; Master_Adc_Config.COMPARE2 = 0x5678u ; Master_Adc_Config.STATUS2 = !ADTRG_HW | ACFE_DISABLED | ACFGT_GREATER | ACREN_DISABLED | DMAEN_DISABLED | ADC_SC2_REFSEL(REFSEL_EXT); Master_Adc_Config.STATUS3 = CAL_OFF | ADCO_SINGLE | AVGE_ENABLED | ADC_SC3_AVGS(AVGS_4); // Master_Adc_Config.PGA = PGAEN_DISABLED | PGACHP_NOCHOP | PGALP_NORMAL | ADC_PGA_PGAG(PGAG_64); Master_Adc_Config.STATUS1A = !AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(31); Master_Adc_Config.STATUS1B = !AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(31); ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config); // config the ADC again to default conditions }
void init_ADC16(void){ // Turn on the ADC0 clock as well as the PDB clocks to test ADC triggered by PDB SIM_SCGC6 |= (SIM_SCGC6_ADC0_MASK ); // SIM_SCGC6 |= SIM_SCGC6_PDB_MASK ; pdb PMC_REGSC |= PMC_REGSC_BGBE_MASK ; // setup the initial ADC default configuration Master_Adc_Config.CONFIG1 = ADLPC_LOW | ADC_CFG1_ADIV(ADIV_1) | ADLSMP_LONG | ADC_CFG1_MODE(MODE_16) | ADC_CFG1_ADICLK(ADICLK_BUS); Master_Adc_Config.CONFIG2 = MUXSEL_ADCA | ADACKEN_DISABLED | ADHSC_HISPEED | ADC_CFG2_ADLSTS(ADLSTS_20) ; Master_Adc_Config.COMPARE1 = 0x1234u ; // can be anything Master_Adc_Config.COMPARE2 = 0x5678u ; // can be anything // since not using // compare feature Master_Adc_Config.STATUS2 = ADTRG_SW | ACFE_DISABLED | ACFGT_GREATER | ACREN_DISABLED | DMAEN_DISABLED | ADC_SC2_REFSEL(REFSEL_EXT); Master_Adc_Config.STATUS3 = CAL_OFF | ADCO_SINGLE | !AVGE_ENABLED | ADC_SC3_AVGS(AVGS_4); Master_Adc_Config.STATUS1A = !AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(31); // Configure ADC as it will be used, but becuase ADC_SC1_ADCH is 31, // the ADC will be inactive. Channel 31 is just disable function. // There really is no channel 31. ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config); // config ADC // Calibrate the ADC in the configuration in which it will be used: ADC_Cal(ADC0_BASE_PTR); // do the calibration // The structure still has the desired configuration. So restore it. // Why restore it? The calibration makes some adjustments to the // configuration of the ADC. The are now undone: // config the ADC again to desired conditions ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config); }
void InitADC_12Bit() { SIM_SCGC6 |= SIM_SCGC6_ADC0_MASK; // setup the initial ADC default configuration to get setup for calibration Master_Adc_Config.CONFIG1 = ADLPC_NORMAL | ADC_CFG1_ADIV(ADIV_4) | ADLSMP_LONG | ADC_CFG1_MODE(MODE_12) | ADC_CFG1_ADICLK(ADICLK_BUS); Master_Adc_Config.CONFIG2 = MUXSEL_ADCA | ADACKEN_DISABLED | ADHSC_HISPEED | ADC_CFG2_ADLSTS(ADLSTS_20) ; Master_Adc_Config.COMPARE1 = 0x1234u ; // can be anything Master_Adc_Config.COMPARE2 = 0x5678u ; // can be anything // since not using // compare feature Master_Adc_Config.STATUS2 = ACFE_DISABLED | ACFGT_GREATER | ACREN_ENABLED | DMAEN_DISABLED | ADC_SC2_REFSEL(REFSEL_EXT); Master_Adc_Config.STATUS3 = CAL_OFF | ADCO_SINGLE | AVGE_ENABLED | ADC_SC3_AVGS(AVGS_16); Master_Adc_Config.STATUS1A = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(31); Master_Adc_Config.STATUS1B = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(31); // Configure ADC as it will be used, but becuase ADC_SC1_ADCH is 31, // the ADC will be inactive. Channel 31 is just disable function. // There really is no channel 31. ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config); // config ADC // Calibrate the ADC in the configuration in which it will be used: ADC_Cal(ADC0_BASE_PTR); // do the calibration // The structure still has the desired configuration. So restore it. // Why restore it? The calibration makes some adjustments to the // configuration of the ADC. The are now undone: // config the ADC again to desired conditions ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config); // ***************************************************************************** // ADC0 using the PDB trigger in ping pong // ***************************************************************************** // use interrupts, single ended mode, and real channel numbers now: ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config); // config ADC0 }
uint8_t Hw_Trig_Test(void) { // Notes: // PDB settings : continous mode, started by sotware trigger. // This means that once the software "pulls the trigger" by setting a certain bit, the PDB starts counting // and handing out four triggers per cycle of its counter. // PDB settings: CH0_DLY0, CH0_DLY1 , CH1_DLY0, CH1_DLY1 // set to different values to distinguish effect on ADCx_Ry register // need to provide 4 different voltages to convert at two ADC0 and two ADC1 input channels // PDB counter clock prescaled to allow time for printf's and slow down things to they are visible, each trigger. // Using adiclk= BUS , and adidiv/4 to get 12,5MHz on Tower demonstration. // visibility of PDB start trigger is obtained by generating a toggling edge on // GPIOxx with PDBisr set to trigger immediatly at zero value of PDB counter. // Conversion end of each ADC and channel within the ADC ( A,B ) will be done by // toggling second GPIO pin inside ADCisr ( this pin is also reset by PDB isr ) // GPIO PIN to low voltage .. this macro sets the PIN low. PIN_LOW // Initialize PIN1 and PIN2 GPIO outputs Init_Gpio2(); // Disable ADC and PDB interrupts disable_irq(ADC0_irq_no) ; // not ready for this interrupt yet. Plug vector first. disable_irq(ADC1_irq_no) ; // not ready for this interrupt yet. Plug vector first. disable_irq(PDB_irq_no) ; // not ready for this interrupt yet. Plug vector first. // Dynamic interrupt vector modification whilst those interruts are disabled __VECTOR_RAM[73] = (uint32)adc0_isr; // plug isr into vector table in case not there already __VECTOR_RAM[74] = (uint32)adc1_isr; // plug isr into vector table in case not there already __VECTOR_RAM[88] = (uint32)pdb_isr; // plug isr into vector table in case not there already // The System Integration Module largely determines the role of the different ball map locations on Kinetis. // When an external pin is used, the System Integration Module should be consulted and invoked as needed. // System integration module registers start with SIM_ // Turn on the ADC0 and ADC1 clocks as well as the PDB clocks to test ADC triggered by PDB SIM_SCGC6 |= (SIM_SCGC6_ADC0_MASK ); SIM_SCGC3 |= (SIM_SCGC3_ADC1_MASK ); SIM_SCGC6 |= SIM_SCGC6_PDB_MASK ; // Configure System Integration Module for defaults as far as ADC SIM_SOPT7 &= ~(SIM_SOPT7_ADC1ALTTRGEN_MASK | // selects PDB not ALT trigger SIM_SOPT7_ADC1PRETRGSEL_MASK | SIM_SOPT7_ADC0ALTTRGEN_MASK | // selects PDB not ALT trigger SIM_SOPT7_ADC0ALTTRGEN_MASK) ; SIM_SOPT7 = SIM_SOPT7_ADC0TRGSEL(0); // applies only in case of ALT trigger, in which case // PDB external pin input trigger for ADC SIM_SOPT7 = SIM_SOPT7_ADC1TRGSEL(0); // same for both ADCs ///////////////////////////////////////////////////////////////////////////////////////// //PDB configured below 以下是PDB配置 // Configure the Peripheral Delay Block (PDB): // enable PDB, pdb counter clock = busclock / 20 , continous triggers, sw trigger , and use prescaler too PDB0_SC = PDB_SC_CONT_MASK // Contintuous, rather than one-shot, mode | PDB_SC_PDBEN_MASK // PDB enabled | PDB_SC_PDBIE_MASK // PDB Interrupt Enable | PDB_SC_PRESCALER(0x5) // Slow down the period of the PDB for testing | PDB_SC_TRGSEL(0xf) // Trigger source is Software Trigger to be invoked in this file | PDB_SC_MULT(2); // Multiplication factor 20 for the prescale divider for the counter clock // the software trigger, PDB_SC_SWTRIG_MASK is not triggered at this time. PDB0_IDLY = 0x0000; // need to trigger interrupt every counter reset which happens when modulus reached PDB0_MOD = 0xffff; // largest period possible with the slections above, so slow you can see each conversion. // channel 0 pretrigger 0 and 1 enabled and delayed PDB0_CH0C1 = PDB_C1_EN(0x01) | PDB_C1_TOS(0x01) | PDB_C1_EN(0x02) | PDB_C1_TOS(0x02) ; PDB0_CH0DLY0 = ADC0_DLYA ; PDB0_CH0DLY1 = ADC0_DLYB ; // channel 1 pretrigger 0 and 1 enabled and delayed PDB0_CH1C1 = PDB_C1_EN(0x01) | PDB_C1_TOS(0x01) | PDB_C1_EN(0x02) | PDB_C1_TOS(0x02) ; PDB0_CH1DLY0 = ADC1_DLYA ; PDB0_CH1DLY1 = ADC1_DLYB ; PDB0_SC = PDB_SC_CONT_MASK // Contintuous, rather than one-shot, mode | PDB_SC_PDBEN_MASK // PDB enabled | PDB_SC_PDBIE_MASK // PDB Interrupt Enable | PDB_SC_PRESCALER(0x5) // Slow down the period of the PDB for testing | PDB_SC_TRGSEL(0xf) // Trigger source is Software Trigger to be invoked in this file | PDB_SC_MULT(2) // Multiplication factor 20 for the prescale divider for the counter clock | PDB_SC_LDOK_MASK; // Need to ok the loading or it will not load certain regsiters! // the software trigger, PDB_SC_SWTRIG_MASK is not triggered at this time. //PDB configured above 以上是PDB配置 ///////////////////////////////////////////////////////////////////////////////////////// //ADC configured below 以下是ADC配置 // setup the initial ADC default configuration Master_Adc_Config.CONFIG1 = ADLPC_NORMAL | ADC_CFG1_ADIV(ADIV_4) | ADLSMP_LONG | ADC_CFG1_MODE(MODE_16) | ADC_CFG1_ADICLK(ADICLK_BUS); Master_Adc_Config.CONFIG2 = MUXSEL_ADCA | ADACKEN_DISABLED | ADHSC_HISPEED | ADC_CFG2_ADLSTS(ADLSTS_20) ; Master_Adc_Config.COMPARE1 = 0x1234u ; // can be anything Master_Adc_Config.COMPARE2 = 0x5678u ; // can be anything // since not using // compare feature Master_Adc_Config.STATUS2 = ADTRG_HW | ACFE_DISABLED | ACFGT_GREATER | ACREN_ENABLED | DMAEN_DISABLED | ADC_SC2_REFSEL(REFSEL_EXT); Master_Adc_Config.STATUS3 = CAL_OFF | ADCO_SINGLE | AVGE_ENABLED | ADC_SC3_AVGS(AVGS_32); Master_Adc_Config.PGA = PGAEN_DISABLED | PGACHP_NOCHOP | PGALP_NORMAL | ADC_PGA_PGAG(PGAG_64); Master_Adc_Config.STATUS1A = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(31); Master_Adc_Config.STATUS1B = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(31); // Configure ADC as it will be used, but becuase ADC_SC1_ADCH is 31, // the ADC will be inactive. Channel 31 is just disable function. // There really is no channel 31. ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config); // config ADC // Calibrate the ADC in the configuration in which it will be used: ADC_Cal(ADC0_BASE_PTR); // do the calibration // The structure still has the desired configuration. So restore it. // Why restore it? The calibration makes some adjustments to the // configuration of the ADC. The are now undone: // config the ADC again to desired conditions ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config); // REPEAT for BOTH ADC's. However we will only 'use' the results from // the ADC wired to the Potentiometer on the Kinetis Tower Card. // Repeating for ADC1: ADC_Config_Alt(ADC1_BASE_PTR, &Master_Adc_Config); // config ADC ADC_Cal(ADC1_BASE_PTR); // do the calibration // ADC_Read_Cal(ADC1_BASE_PTR,&CalibrationStore[0]); // store the cal // config the ADC again to default conditions ADC_Config_Alt(ADC1_BASE_PTR, &Master_Adc_Config); // ***************************************************************************** // ADC0 and ADC1 using the PDB trigger in ping pong // ***************************************************************************** // use interrupts, single ended mode, and real channel numbers now: Master_Adc_Config.STATUS1A = AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(ADC0_CHANA); Master_Adc_Config.STATUS1B = AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(ADC0_CHANB); ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config); // config ADC0 Master_Adc_Config.STATUS1A = AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(ADC1_CHANA); Master_Adc_Config.STATUS1B = AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(ADC1_CHANB); ADC_Config_Alt(ADC1_BASE_PTR, &Master_Adc_Config); // config ADC1 // Note that three different balls are being sampled: // ADC0_CHANA not used in this demo, but readings are shown // ADC0_CHANB not used in this demo, but readings are shown // ADC1_CHANA POT channel set the same as the following for demo: 20 // ADC1_CHANB POT channel set the same as the above for demo: 20 // The potentiometer is only on ADC1. That is the one used // to calculate the change of the potentiometer below. while(char_present()) in_char(); // flush terminal buffer printf ("\n\n\n"); printf("********************************************************\n"); printf("* Running ADC0 & ADC1 HARDWARE TRIGGER by PDB *\n"); printf("* The one PDB is triggering both ADC0 and ADC1 *\n"); printf("* ADC1 A,B is the POT. Vary the POT setting. *\n"); printf("* Hit any key to exit (ADC0 readings not used) *\n"); printf("********************************************************\n"); printf ("\n\n"); // Enable the ADC and PDB interrupts in NVIC enable_irq(ADC0_irq_no) ; // ready for this interrupt. enable_irq(ADC1_irq_no) ; // ready for this interrupt. enable_irq(PDB_irq_no) ; // ready for this interrupt. // In case previous test did not end with interrupts enabled, enable used ones. EnableInterrupts ; cycle_flags=0; PDB0_SC |= PDB_SC_SWTRIG_MASK ; // kick off the PDB - just once //The system is now working!!!! The PDB is *continuously* triggering ADC // conversions. Now, to display the results! The line above // was the SOFTWARE TRIGGER... // The demo will continue as long as no character is pressed on the terminal. while(!char_present()) // as long as no operater intervention, keep running this: { while( cycle_flags != ( ADC0A_DONE | ADC0B_DONE | ADC1A_DONE | ADC1B_DONE )); // wait for one complete cycle printf("R0A=%6d R0B=%6d R1A=%6d R1B=%6d POT=%6d\r", result0A,result0B,result1A,result1B, exponentially_filtered_result1); } // disable the PDB PDB0_SC = 0 ; // Disable the ADC and PDB interrupts in NVIC disable_irq(ADC0_irq_no) ; // through with this interrupt. disable_irq(ADC1_irq_no) ; // through with this interrupt. disable_irq(PDB_irq_no) ; // through with this interrupt. printf ("\n\n\n"); printf("********************************************************\n"); printf("* Demonstration ended at operator request *\n"); printf("* ADC0 & ADC1 PDB TRIGGER DEMO COMPLETE *\n"); printf("********************************************************\n"); printf ("\n\n"); return 0; }
void InitADC1() { tADC_Config Master_Adc1_Config; SIM_SCGC3 |= (SIM_SCGC3_ADC1_MASK); //Lets calibrate the ADC. 1st setup how the channel will be used. disable_irq(INT_ADC1-16); Master_Adc1_Config.CONFIG1 = ADLPC_NORMAL //No low power mode | ADC_CFG1_ADIV(ADIV_4) //divide input by 4 | ADLSMP_LONG //long sample time | ADC_CFG1_MODE(MODE_8)//single ended 8-bit conversion | ADC_CFG1_ADICLK(ADICLK_BUS); Master_Adc1_Config.CONFIG2 = MUXSEL_ADCA // select the A side of the ADC channel. | ADACKEN_DISABLED | ADHSC_HISPEED | ADC_CFG2_ADLSTS(ADLSTS_2);//Extra long sample Time (20 extra clocks) Master_Adc1_Config.COMPARE1 = 00000; // Comparators don't matter for calibration Master_Adc1_Config.COMPARE1 = 0xFFFF; Master_Adc1_Config.STATUS2 = ADTRG_HW //hardware triggers for calibration | ACFE_DISABLED //disable comparator | ACFGT_GREATER | ACREN_ENABLED | DMAEN_DISABLED //Disable DMA | ADC_SC2_REFSEL(REFSEL_EXT); //External Reference Master_Adc1_Config.STATUS3 = CAL_OFF | ADCO_SINGLE | AVGE_ENABLED | ADC_SC3_AVGS(AVGS_4); Master_Adc1_Config.PGA = 0; // Disable the PGA // Configure ADC as it will be used, but because ADC_SC1_ADCH is 31, // the ADC will be inactive. Channel 31 is just disable function. // There really is no channel 31. Master_Adc1_Config.STATUS1A = AIEN_ON | DIFF_SINGLE | ADC_SC1_ADCH(31); // Master_Adc_Config.STATUS1B = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(31); ADC_Config_Alt(ADC1_BASE_PTR, &Master_Adc1_Config); // config ADC // Calibrate the ADC in the configuration in which it will be used: ADC_Cal(ADC1_BASE_PTR); // do the calibration Master_Adc1_Config.STATUS2 = ACFE_DISABLED //disable comparator | ACFGT_GREATER | ACREN_ENABLED | DMAEN_DISABLED //Disable DMA | ADC_SC2_REFSEL(REFSEL_EXT); //External Reference Master_Adc1_Config.STATUS3 = CAL_OFF | ADCO_SINGLE; ADC_Config_Alt(ADC1_BASE_PTR, &Master_Adc1_Config); }
////Initialize ADC Function. Needs to be placed somewhere?? void AnalogInputPin::InitADCs() { // setup the initial ADC default configuration Master_Adc_Config.CONFIG1 = ADLPC_NORMAL // Normal power, (not low power) | ADC_CFG1_ADIV(ADIV_4) // Clock divider | ADLSMP_LONG // Take a long time to sample | ADC_CFG1_MODE(MODE_16) // 16 bit mode | ADC_CFG1_ADICLK(ADICLK_BUS); // use the bus clock Master_Adc_Config.CONFIG2 = MUXSEL_ADCB // use channel A | ADACKEN_DISABLED // Asynch clock disabled? | ADHSC_NORMAL // Asynch clock setting | ADC_CFG2_ADLSTS(ADLSTS_20) ; Master_Adc_Config.COMPARE1 = 0x1234u ; // can be anything Master_Adc_Config.COMPARE2 = 0x5678u ; // can be anything // since not using // compare feature Master_Adc_Config.STATUS2 = ADTRG_SW // Software triggered conversion | ACFE_DISABLED // Disable comparator (if enabled only registers as an anlog reading if it is greater than a certain value) | ACFGT_GREATER // comparator setting | ACREN_DISABLED // Compare Function Range disabled | DMAEN_DISABLED // Disable DMA | ADC_SC2_REFSEL(REFSEL_EXT); // external voltage reference Master_Adc_Config.STATUS3 = CAL_OFF // Calibration begins off | ADCO_SINGLE // Take a single reading | AVGE_ENABLED // Enable averaging | ADC_SC3_AVGS(AVGS_32); // Average 32 samples Master_Adc_Config.PGA = PGAEN_DISABLED // PGA disabled | PGACHP_NOCHOP // no chopping for PGA? | PGALP_NORMAL // Normal (not low power mode) | ADC_PGA_PGAG(PGAG_64); // PGA gain of 64 // Set up channel as all ones for configuration Master_Adc_Config.STATUS1A = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(31); Master_Adc_Config.STATUS1B = AIEN_OFF | DIFF_SINGLE | ADC_SC1_ADCH(31); // Configure ADC as it will be used, but becuase ADC_SC1_ADCH is 31, // the ADC will be inactive. Channel 31 is just disable function. // There really is no channel 31. ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config); // config ADC ADC_Config_Alt(ADC1_BASE_PTR, &Master_Adc_Config); // config ADC // Calibrate the ADC in the configuration in which it will be used: ADC_Cal(ADC1_BASE_PTR); // do the calibration ADC_Cal(ADC0_BASE_PTR); // do the calibration // The structure still has the desired configuration. So restore it. // Why restore it? The calibration makes some adjustments to the // configuration of the ADC. The are now undone: // config the ADC again to desired conditions ADC_Config_Alt(ADC1_BASE_PTR, &Master_Adc_Config); ADC_Config_Alt(ADC0_BASE_PTR, &Master_Adc_Config); //Load Encoder ADC Config (A bit different from Master) Encoder_Adc_Config = Master_Adc_Config; Encoder_Adc_Config.CONFIG1 = ADLPC_NORMAL // Normal power, (not low power) | ADC_CFG1_ADIV(ADIV_4) // Clock divider | ADLSMP_LONG // Take a long time to sample | ADC_CFG1_MODE(MODE_16) // 16 bit mode | ADC_CFG1_ADICLK(ADICLK_BUS); // use the bus clock Encoder_Adc_Config.STATUS3 = CAL_OFF // Calibration begins off | ADCO_SINGLE // Take a single reading | AVGE_ENABLED // Enable averaging | ADC_SC3_AVGS(AVGS_4); // Average 4 samples }