uint32_t adc_read_injected(uint32_t adc, uint8_t reg)
{
switch (reg) {
case 1:
return ADC_JDR1(adc);
case 2:
return ADC_JDR2(adc);
case 3:
return ADC_JDR3(adc);
case 4:
return ADC_JDR4(adc);
}
return 0;
}
void adc_init( void ) {
/* initialize buffer pointers with 0 (not set).
buffer null pointers will be ignored in interrupt
handler, which is important as there are no
buffers registered at the time the ADC trigger
interrupt is enabled.
*/
uint8_t channel;
#ifdef USE_AD1
for(channel = 0; channel < NB_ADC1_CHANNELS; channel++)
adc1_buffers[channel] = NULL;
adc_injected_channels[0] = &ADC_JDR1(ADC1);
adc_injected_channels[1] = &ADC_JDR2(ADC1);
adc_injected_channels[2] = &ADC_JDR3(ADC1);
adc_injected_channels[3] = &ADC_JDR4(ADC1);
#endif
#ifdef USE_AD2
for(channel = 0; channel < NB_ADC2_CHANNELS; channel++)
adc2_buffers[channel] = NULL;
adc_injected_channels[0] = &ADC_JDR1(ADC2);
adc_injected_channels[1] = &ADC_JDR2(ADC2);
adc_injected_channels[2] = &ADC_JDR3(ADC2);
adc_injected_channels[3] = &ADC_JDR4(ADC2);
#endif
adc_new_data_trigger = FALSE;
adc_channel_map[0] = BOARD_ADC_CHANNEL_1;
adc_channel_map[1] = BOARD_ADC_CHANNEL_2;
adc_channel_map[2] = BOARD_ADC_CHANNEL_3;
adc_channel_map[3] = BOARD_ADC_CHANNEL_4;
adc_init_rcc();
adc_init_irq();
// adc_init_single(ADCx, c1, c2, c3, c4)
#ifdef USE_AD1
adc_init_single(ADC1,
#ifdef USE_AD1_1
1,
#else
0,
#endif
#ifdef USE_AD1_2
1,
#else
0,
#endif
#ifdef USE_AD1_3
1,
#else
0,
#endif
#ifdef USE_AD1_4
1
#else
0
#endif
);
#endif // USE_AD1
#ifdef USE_AD2
adc_init_single(ADC2,
#ifdef USE_AD2_1
1,
#else
0,
#endif
#ifdef USE_AD2_2
1,
#else
0,
#endif
#ifdef USE_AD2_3
1,
#else
0,
#endif
#ifdef USE_AD2_4
1
#else
0
#endif
);
#endif // USE_AD2
}
void adc_isr(void)
#endif
{
uint8_t channel = 0;
uint16_t value = 0;
struct adc_buf * buf;
#if USE_ADC_WATCHDOG
if (adc_watchdog.cb != NULL) {
if (adc_awd(adc_watchdog.adc)) {
ADC_SR(adc_watchdog.adc) &= ~ADC_SR_AWD; // clear int flag
adc_watchdog.cb();
}
}
#endif
#if USE_AD1
// Clear Injected End Of Conversion
if (ADC_SR(ADC1) & ADC_SR_JEOC){
ADC_SR(ADC1) &= ~ADC_SR_JEOC;
for (channel = 0; channel < nb_adc1_channels; channel++) {
buf = adc1_buffers[channel];
if (buf) {
value = *(&ADC_JDR1(ADC1)+channel);
adc_push_sample(buf, value);
}
}
#if !USE_AD2 && !USE_AD3
adc_new_data_trigger = TRUE;
#endif
}
#endif
#if USE_AD2
if (ADC_SR(ADC2) & ADC_SR_JEOC){
ADC_SR(ADC2) &= ~ADC_SR_JEOC;
for (channel = 0; channel < nb_adc2_channels; channel++) {
buf = adc2_buffers[channel];
if (buf) {
value = *(&ADC_JDR1(ADC2)+channel);
adc_push_sample(buf, value);
}
}
#if !USE_AD3
adc_new_data_trigger = TRUE;
#endif
}
#endif
#if USE_AD3
if (ADC_SR(ADC3) & ADC_SR_JEOC){
ADC_SR(ADC3) &= ~ADC_SR_JEOC;
for (channel = 0; channel < nb_adc3_channels; channel++) {
buf = adc3_buffers[channel];
if (buf) {
value = *(&ADC_JDR1(ADC3)+channel);
adc_push_sample(buf, value);
}
}
adc_new_data_trigger = TRUE;
}
#endif
return;
}
