/***************************************************************************//** * @brief dds_set_phase *******************************************************************************/ void dds_set_phase(uint32_t chan, uint32_t phase) { uint64_t val64; uint32_t reg; dds_st.cached_phase[chan] = phase; dac_stop(); dac_read(ADI_REG_CHAN_CNTRL_2_IIOCHAN(chan), ®); reg &= ~ADI_DDS_INIT(~0); val64 = (uint64_t) phase * 0x10000ULL + (360000 / 2); do_div(&val64, 360000); reg |= ADI_DDS_INIT(val64); dac_write(ADI_REG_CHAN_CNTRL_2_IIOCHAN(chan), reg); dac_start_sync(0); }
/***************************************************************************//** * @brief dds_default_setup *******************************************************************************/ static int dds_default_setup(uint32_t chan, uint32_t phase, uint32_t freq, uint32_t scale) { uint64_t val64; uint32_t val; dds_st.cached_freq[chan] = freq; dds_st.cached_phase[chan] = phase; dds_st.cached_scale[chan] = scale; val64 = (u64) freq * 0xFFFFULL; do_div(val64, *dds_st.dac_clk); val = ADI_DDS_INCR(val64) | 1; val64 = (u64) phase * 0x10000ULL + (360000 / 2); do_div(val64, 360000); val |= ADI_DDS_INIT(val64); dac_write(ADI_REG_CHAN_CNTRL_1_IIOCHAN(chan), ADI_DDS_SCALE(scale)); dac_write(ADI_REG_CHAN_CNTRL_2_IIOCHAN(chan), val); return 0; }