void __init default_setup_apic_routing(void)
{
int version = apic_version[boot_cpu_physical_apicid];
if (num_possible_cpus() > 8) {
switch (boot_cpu_data.x86_vendor) {
case X86_VENDOR_INTEL:
if (!APIC_XAPIC(version)) {
def_to_bigsmp = 0;
break;
}
/* If P4 and above fall through */
case X86_VENDOR_AMD:
def_to_bigsmp = 1;
}
}
#ifdef CONFIG_X86_BIGSMP
/*
* This is used to switch to bigsmp mode when
* - There is no apic= option specified by the user
* - generic_apic_probe() has chosen apic_default as the sub_arch
* - we find more than 8 CPUs in acpi LAPIC listing with xAPIC support
*/
if (!cmdline_apic && apic == &apic_default)
generic_bigsmp_probe();
#endif
if (apic->setup_apic_routing)
apic->setup_apic_routing();
if (x86_platform.apic_post_init)
x86_platform.apic_post_init();
}
void __init default_setup_apic_routing(void)
{
int version = apic_version[boot_cpu_physical_apicid];
if (num_possible_cpus() > 8) {
switch (boot_cpu_data.x86_vendor) {
case X86_VENDOR_INTEL:
if (!APIC_XAPIC(version)) {
def_to_bigsmp = 0;
break;
}
case X86_VENDOR_AMD:
def_to_bigsmp = 1;
}
}
#ifdef CONFIG_X86_BIGSMP
if (!cmdline_apic && apic == &apic_default)
generic_bigsmp_probe();
#endif
if (apic->setup_apic_routing)
apic->setup_apic_routing();
}
void IOAPIC::SetupIDsFromMPC() {
union IO_APIC_reg_00 reg_00;
if(system->cpuid->vendor_code != VENDOR_INTEL || APIC_XAPIC(system->smp->apic_version[system->smp->boot_cpu_physical_apicid])) {
printk("xAPIC detected, skipping setting IO-APIC IDs\n");
return;
}
for (int apic = 0; apic < system->smp->nr_ioapics; apic++) {
reg_00.raw = ioapic_read(apic, 0);
int old_id = system->smp->mp_ioapics[apic].mpc_apicid;
if (old_id >= parent->GetPhysicalBroadcast()) {
printk("BIOS bug, IO-APIC#%d ID is %d in the MPC table, fixing up to %d\n",
apic, old_id, reg_00.bits.ID);
system->smp->mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
}
if (old_id != system->smp->mp_ioapics[apic].mpc_apicid)
for (int i = 0; i < system->smp->mp_irq_entries; i++)
if (system->smp->mp_irqs[i].mpc_dstapic == old_id)
system->smp->mp_irqs[i].mpc_dstapic = system->smp->mp_ioapics[apic].mpc_apicid;
printk( "Changing IO-APIC physical APIC ID to %d ...", system->smp->mp_ioapics[apic].mpc_apicid);
reg_00.bits.ID = system->smp->mp_ioapics[apic].mpc_apicid;
ioapic_write(apic, 0, reg_00.raw);
reg_00.raw = ioapic_read(apic, 0);
if (reg_00.bits.ID != system->smp->mp_ioapics[apic].mpc_apicid)
printk("could not set ID!\n");
else
printk(" ok.\n");
}
}
static void __devinit MP_processor_info (struct mpc_config_processor *m)
{
int ver, apicid;
physid_mask_t phys_cpu;
if (!(m->mpc_cpuflag & CPU_ENABLED))
return;
apicid = mpc_apic_id(m, translation_table[mpc_record]);
if (m->mpc_featureflag&(1<<0))
Dprintk(" Floating point unit present.\n");
if (m->mpc_featureflag&(1<<7))
Dprintk(" Machine Exception supported.\n");
if (m->mpc_featureflag&(1<<8))
Dprintk(" 64 bit compare & exchange supported.\n");
if (m->mpc_featureflag&(1<<9))
Dprintk(" Internal APIC present.\n");
if (m->mpc_featureflag&(1<<11))
Dprintk(" SEP present.\n");
if (m->mpc_featureflag&(1<<12))
Dprintk(" MTRR present.\n");
if (m->mpc_featureflag&(1<<13))
Dprintk(" PGE present.\n");
if (m->mpc_featureflag&(1<<14))
Dprintk(" MCA present.\n");
if (m->mpc_featureflag&(1<<15))
Dprintk(" CMOV present.\n");
if (m->mpc_featureflag&(1<<16))
Dprintk(" PAT present.\n");
if (m->mpc_featureflag&(1<<17))
Dprintk(" PSE present.\n");
if (m->mpc_featureflag&(1<<18))
Dprintk(" PSN present.\n");
if (m->mpc_featureflag&(1<<19))
Dprintk(" Cache Line Flush Instruction present.\n");
/* 20 Reserved */
if (m->mpc_featureflag&(1<<21))
Dprintk(" Debug Trace and EMON Store present.\n");
if (m->mpc_featureflag&(1<<22))
Dprintk(" ACPI Thermal Throttle Registers present.\n");
if (m->mpc_featureflag&(1<<23))
Dprintk(" MMX present.\n");
if (m->mpc_featureflag&(1<<24))
Dprintk(" FXSR present.\n");
if (m->mpc_featureflag&(1<<25))
Dprintk(" XMM present.\n");
if (m->mpc_featureflag&(1<<26))
Dprintk(" Willamette New Instructions present.\n");
if (m->mpc_featureflag&(1<<27))
Dprintk(" Self Snoop present.\n");
if (m->mpc_featureflag&(1<<28))
Dprintk(" HT present.\n");
if (m->mpc_featureflag&(1<<29))
Dprintk(" Thermal Monitor present.\n");
/* 30, 31 Reserved */
if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
Dprintk(" Bootup CPU\n");
boot_cpu_physical_apicid = m->mpc_apicid;
}
ver = m->mpc_apicver;
/*
* Validate version
*/
if (ver == 0x0) {
printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
"fixing up to 0x10. (tell your hw vendor)\n",
m->mpc_apicid);
ver = 0x10;
}
apic_version[m->mpc_apicid] = ver;
phys_cpu = apicid_to_cpu_present(apicid);
physids_or(phys_cpu_present_map, phys_cpu_present_map, phys_cpu);
if (num_processors >= NR_CPUS) {
printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
" Processor ignored.\n", NR_CPUS);
return;
}
if (num_processors >= maxcpus) {
printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
" Processor ignored.\n", maxcpus);
return;
}
cpu_set(num_processors, cpu_possible_map);
num_processors++;
/*
* Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
* but we need to work other dependencies like SMP_SUSPEND etc
* before this can be done without some confusion.
* if (CPU_HOTPLUG_ENABLED || num_processors > 8)
* - Ashok Raj <*****@*****.**>
*/
if (num_processors > 8) {
switch (boot_cpu_data.x86_vendor) {
case X86_VENDOR_INTEL:
if (!APIC_XAPIC(ver)) {
def_to_bigsmp = 0;
break;
}
/* If P4 and above fall through */
case X86_VENDOR_AMD:
def_to_bigsmp = 1;
}
}
bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
}
