HAL_BOOL
ar5211FillTxDesc(struct ath_hal *ah, struct ath_desc *ds,
u_int segLen, HAL_BOOL firstSeg, HAL_BOOL lastSeg,
const struct ath_desc *ds0)
{
struct ar5211_desc *ads = AR5211DESC(ds);
HALASSERT((segLen &~ AR_BufLen) == 0);
if (firstSeg) {
/*
* First descriptor, don't clobber xmit control data
* setup by ar5211SetupTxDesc.
*/
ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_More);
} else if (lastSeg) { /* !firstSeg && lastSeg */
/*
* Last descriptor in a multi-descriptor frame,
* copy the transmit parameters from the first
* frame for processing on completion.
*/
ads->ds_ctl0 = AR5211DESC_CONST(ds0)->ds_ctl0;
ads->ds_ctl1 = segLen;
} else { /* !firstSeg && !lastSeg */
/*
* Intermediate descriptor in a multi-descriptor frame.
*/
ads->ds_ctl0 = 0;
ads->ds_ctl1 = segLen | AR_More;
}
ads->ds_status0 = ads->ds_status1 = 0;
return AH_TRUE;
}
void
ar5211IntrReqTxDesc(struct ath_hal *ah, struct ath_desc *ds)
{
struct ar5211_desc *ads = AR5211DESC(ds);
ads->ds_ctl0 |= AR_TxInterReq;
}
void
ar5211GetTxDescLinkPtr(struct ath_hal *ah, void *ds, uint32_t **linkptr)
{
struct ar5211_desc *ads = AR5211DESC(ds);
*linkptr = &ads->ds_link;
}
void
ar5211GetTxDescLink(struct ath_hal *ah, void *ds, uint32_t *link)
{
struct ar5211_desc *ads = AR5211DESC(ds);
*link = ads->ds_link;
}
/*
* Process an RX descriptor, and return the status to the caller.
* Copy some hardware specific items into the software portion
* of the descriptor.
*
* NB: the caller is responsible for validating the memory contents
* of the descriptor (e.g. flushing any cached copy).
*/
HAL_STATUS
ar5211ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,
uint32_t pa, struct ath_desc *nds, uint64_t tsf,
struct ath_rx_status *rs)
{
struct ar5211_desc *ads = AR5211DESC(ds);
struct ar5211_desc *ands = AR5211DESC(nds);
if ((ads->ds_status1 & AR_Done) == 0)
return HAL_EINPROGRESS;
/*
* Given the use of a self-linked tail be very sure that the hw is
* done with this descriptor; the hw may have done this descriptor
* once and picked it up again...make sure the hw has moved on.
*/
if ((ands->ds_status1 & AR_Done) == 0 && OS_REG_READ(ah, AR_RXDP) == pa)
return HAL_EINPROGRESS;
rs->rs_datalen = ads->ds_status0 & AR_DataLen;
rs->rs_tstamp = MS(ads->ds_status1, AR_RcvTimestamp);
rs->rs_status = 0;
if ((ads->ds_status1 & AR_FrmRcvOK) == 0) {
if (ads->ds_status1 & AR_CRCErr)
rs->rs_status |= HAL_RXERR_CRC;
else if (ads->ds_status1 & AR_DecryptCRCErr)
rs->rs_status |= HAL_RXERR_DECRYPT;
else {
rs->rs_status |= HAL_RXERR_PHY;
rs->rs_phyerr = MS(ads->ds_status1, AR_PHYErr);
}
}
/* XXX what about KeyCacheMiss? */
rs->rs_rssi = MS(ads->ds_status0, AR_RcvSigStrength);
if (ads->ds_status1 & AR_KeyIdxValid)
rs->rs_keyix = MS(ads->ds_status1, AR_KeyIdx);
else
rs->rs_keyix = HAL_RXKEYIX_INVALID;
/* NB: caller expected to do rate table mapping */
rs->rs_rate = MS(ads->ds_status0, AR_RcvRate);
rs->rs_antenna = MS(ads->ds_status0, AR_RcvAntenna);
rs->rs_more = (ads->ds_status0 & AR_More) ? 1 : 0;
return HAL_OK;
}
/*
* Initialize for PS-Polls
*/
void
ar5211SetupPSPollDesc(struct ath_hal *ah, struct ath_desc *ds,
u_int rate, u_int retries)
{
struct ath_hal_5211 *ahp = AH5211(ah);
struct ar5211_desc *ads = AR5211DESC(ds);
/* Send PS-Polls at 6mbps. */
ads->ds_ctl0 = (rate << AR_XmitRate_S)
| AR_VEOL
| AR_ClearDestMask
| AR_Frm_PSPOLL
;
ads->ds_ctl1 = 0;
ads->ds_status0 = ads->ds_status1 = 0;
}
HAL_BOOL
ar5211SetupTxDesc(struct ath_hal *ah, struct ath_desc *ds,
u_int pktLen,
u_int hdrLen,
HAL_PKT_TYPE type,
u_int txPower,
u_int txRate0, u_int txTries0,
u_int keyIx,
u_int antMode,
u_int flags,
u_int rtsctsRate,
u_int rtsctsDuration,
u_int compicvLen,
u_int compivLen,
u_int comp)
{
struct ar5211_desc *ads = AR5211DESC(ds);
(void) hdrLen;
(void) txPower;
(void) rtsctsRate; (void) rtsctsDuration;
HALASSERT(txTries0 != 0);
HALASSERT(isValidPktType(type));
HALASSERT(isValidTxRate(txRate0));
/* XXX validate antMode */
ads->ds_ctl0 = (pktLen & AR_FrameLen)
| (txRate0 << AR_XmitRate_S)
| (antMode << AR_AntModeXmit_S)
| (flags & HAL_TXDESC_CLRDMASK ? AR_ClearDestMask : 0)
| (flags & HAL_TXDESC_INTREQ ? AR_TxInterReq : 0)
| (flags & HAL_TXDESC_RTSENA ? AR_RTSCTSEnable : 0)
| (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
;
ads->ds_ctl1 = (type << 26)
| (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0)
;
if (keyIx != HAL_TXKEYIX_INVALID) {
ads->ds_ctl1 |=
(keyIx << AR_EncryptKeyIdx_S) & AR_EncryptKeyIdx;
ads->ds_ctl0 |= AR_EncryptKeyValid;
}
return AH_TRUE;
#undef RATE
}
/*
* Initialize RX descriptor, by clearing the status and clearing
* the size. This is not strictly HW dependent, but we want the
* control and status words to be opaque above the hal.
*/
HAL_BOOL
ar5211SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds,
uint32_t size, u_int flags)
{
struct ar5211_desc *ads = AR5211DESC(ds);
ads->ds_ctl0 = 0;
ads->ds_ctl1 = size & AR_BufLen;
if (ads->ds_ctl1 != size) {
HALDEBUG(ah, HAL_DEBUG_ANY, "%s: buffer size %u too large\n",
__func__, size);
return AH_FALSE;
}
if (flags & HAL_RXDESC_INTREQ)
ads->ds_ctl1 |= AR_RxInterReq;
ads->ds_status0 = ads->ds_status1 = 0;
return AH_TRUE;
}
/*
* Processing of HW TX descriptor.
*/
HAL_STATUS
ar5211ProcTxDesc(struct ath_hal *ah,
struct ath_desc *ds, struct ath_tx_status *ts)
{
struct ar5211_desc *ads = AR5211DESC(ds);
if ((ads->ds_status1 & AR_Done) == 0)
return HAL_EINPROGRESS;
/* Update software copies of the HW status */
ts->ts_seqnum = MS(ads->ds_status1, AR_SeqNum);
ts->ts_tstamp = MS(ads->ds_status0, AR_SendTimestamp);
ts->ts_status = 0;
if ((ads->ds_status0 & AR_FrmXmitOK) == 0) {
if (ads->ds_status0 & AR_ExcessiveRetries)
ts->ts_status |= HAL_TXERR_XRETRY;
if (ads->ds_status0 & AR_Filtered)
ts->ts_status |= HAL_TXERR_FILT;
if (ads->ds_status0 & AR_FIFOUnderrun)
ts->ts_status |= HAL_TXERR_FIFO;
}
ts->ts_rate = MS(ads->ds_ctl0, AR_XmitRate);
ts->ts_rssi = MS(ads->ds_status1, AR_AckSigStrength);
ts->ts_shortretry = MS(ads->ds_status0, AR_ShortRetryCnt);
ts->ts_longretry = MS(ads->ds_status0, AR_LongRetryCnt);
ts->ts_virtcol = MS(ads->ds_status0, AR_VirtCollCnt);
ts->ts_antenna = 0; /* NB: don't know */
ts->ts_finaltsi = 0;
/*
* NB: the number of retries is one less than it should be.
* Also, 0 retries and 1 retry are both reported as 0 retries.
*/
if (ts->ts_shortretry > 0)
ts->ts_shortretry++;
if (ts->ts_longretry > 0)
ts->ts_longretry++;
return HAL_OK;
}
