ARM_Interpreter::ARM_Interpreter() {
state = new ARMul_State;
state->m_MemoryMap = NULL;
ARMul_EmulateInit();
memset(state, 0, sizeof(ARMul_State));
ARMul_NewState(state);
state->abort_model = 0;
state->cpu = (cpu_config_t*)&arm11_cpu_info;
state->bigendSig = LOW;
ARMul_SelectProcessor(state, ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
state->lateabtSig = LOW;
// Reset the core to initial state
ARMul_CoProInit(state);
ARMul_Reset(state);
state->NextInstr = RESUME; // NOTE: This will be overwritten by LoadContext
state->Emulate = 3;
state->pc = state->Reg[15] = 0x00000000;
state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack
state->servaddr = 0xFFFF0000;
}
ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) {
state = Common::make_unique<ARMul_State>();
ARMul_NewState(state.get());
ARMul_SelectProcessor(state.get(), ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
state->abort_model = ABORT_BASE_RESTORED;
state->bigendSig = LOW;
state->lateabtSig = LOW;
state->NirqSig = HIGH;
// Reset the core to initial state
ARMul_Reset(state.get());
state->Emulate = RUN;
// Switch to the desired privilege mode.
switch_mode(state.get(), initial_mode);
state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack
state->Reg[15] = 0x00000000;
}
ARM_Interpreter::ARM_Interpreter() {
m_state = new ARMul_State;
ARMul_EmulateInit();
ARMul_NewState(m_state);
m_state->abort_model = 0;
m_state->cpu = (cpu_config_t*)&s_arm11_cpu_info;
m_state->bigendSig = LOW;
ARMul_SelectProcessor(m_state, ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
m_state->lateabtSig = LOW;
mmu_init(m_state);
// Reset the core to initial state
ARMul_Reset(m_state);
m_state->NextInstr = 0;
m_state->Emulate = 3;
m_state->pc = m_state->Reg[15] = 0x00000000;
m_state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack
}
int
resetCPU(void* cpu)
{
unsigned int i, j;
ARMul_State* state = (ARMul_State*) cpu;
// test whether the supplied instance is an ARMul type?
gdblog_index = 0;
// reset registers in all modes
for (i = 0; i < 16; i++)
{
state->Reg[i] = 0;
for (j = 0; j < 7; j++)
state->RegBank[j][i] = 0;
}
for (i = 0; i < 7; i++)
state->Spsr[i] = 0;
ARMul_Reset(state);
return 0;
}
