static void
ath_hal_dumpqcu(FILE *fd, int what)
{
int i;
/* QCU registers */
fprintf(fd, "%-8s %08x %-8s %08x %-8s %08x\n"
, "Q_TXE", OS_REG_READ(ah, AR_Q_TXE)
, "Q_TXD", OS_REG_READ(ah, AR_Q_TXD)
, "Q_RDYTIMSHD", OS_REG_READ(ah, AR_Q_RDYTIMESHDN)
);
fprintf(fd, "Q_ONESHOTARM_SC %08x Q_ONESHOTARM_CC %08x\n"
, OS_REG_READ(ah, AR_Q_ONESHOTARM_SC)
, OS_REG_READ(ah, AR_Q_ONESHOTARM_CC)
);
for (i = 0; i < 10; i++)
fprintf(fd, "Q[%u] TXDP %08x CBR %08x RDYT %08x MISC %08x STS %08x\n"
, i
, OS_REG_READ(ah, AR_QTXDP(i))
, OS_REG_READ(ah, AR_QCBRCFG(i))
, OS_REG_READ(ah, AR_QRDYTIMECFG(i))
, OS_REG_READ(ah, AR_QMISC(i))
, OS_REG_READ(ah, AR_QSTS(i))
);
}
a_uint32_t ar5416NumTxPending(struct ath_hal *ah, a_uint32_t q)
{
a_uint32_t npend;
HALASSERT(q < AH_PRIVATE(ah)->ah_caps.halTotalQueues);
HALASSERT(AH5416(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
npend = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
if (npend == 0) {
/*
* Pending frame count (PFC) can momentarily go to zero
* while TXE remains asserted. In other words a PFC of
* zero is not sufficient to say that the queue has stopped.
*/
if (OS_REG_READ(ah, AR_Q_TXE) & (1 << q))
npend = 1;
}
#ifdef DEBUG
if (npend && (AH5416(ah)->ah_txq[q].tqi_type == HAL_TX_QUEUE_CAB)) {
if (OS_REG_READ(ah, AR_Q_RDYTIMESHDN) & (1 << q)) {
isrPrintf("RTSD on CAB queue\n");
/* Clear the ReadyTime shutdown status bits */
OS_REG_WRITE(ah, AR_Q_RDYTIMESHDN, 1 << q);
}
}
#endif
return npend;
}
u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
{
u32 npend;
npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
if (npend == 0) {
if (REG_READ(ah, AR_Q_TXE) & (1 << q))
npend = 1;
}
return npend;
}
/*
* Return the number of frames pending on the specified queue.
*/
uint32_t
ar5211NumTxPending(struct ath_hal *ah, u_int q)
{
uint32_t n;
HALASSERT(q < HAL_NUM_TX_QUEUES);
HALASSERT(AH5211(ah)->ah_txq[q].tqi_type != HAL_TX_QUEUE_INACTIVE);
n = OS_REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT_M;
/*
* Pending frame count (PFC) can momentarily go to zero
* while TXE remains asserted. In other words a PFC of
* zero is not sufficient to say that the queue has stopped.
*/
if (n == 0 && (OS_REG_READ(ah, AR_Q_TXE) & (1<<q)))
n = 1; /* arbitrarily pick 1 */
return n;
}
void
ar5416_ContTxMode(struct ath_hal *ah, void *ds, int mode)
{
static int qnum =0;
int i;
unsigned int qbits;
#if AH_DEBUG
struct ar5416_desc *ads = AR5416DESC(ds);
unsigned int val, val1, val2;
#endif
if(mode == 10) return;
if (mode==7) { // print status from the cont tx desc
#if AH_DEBUG
if (ads) {
val1 = ads->ds_txstatus0;
val2 = ads->ds_txstatus1;
HDPRINTF(ah, HAL_DBG_TXDESC, "s0(%x) s1(%x)\n",
(unsigned)val1, (unsigned)val2);
}
#endif
HDPRINTF(ah, HAL_DBG_TXDESC, "txe(%x) txd(%x)\n",
OS_REG_READ(ah, AR_Q_TXE),
OS_REG_READ(ah, AR_Q_TXD)
);
#if AH_DEBUG
for(i=0;i<HAL_NUM_TX_QUEUES; i++) {
val = OS_REG_READ(ah, AR_QTXDP(i));
val2 = OS_REG_READ(ah, AR_QSTS(i)) & AR_Q_STS_PEND_FR_CNT;
HDPRINTF(ah, HAL_DBG_TXDESC, "[%d] %x %d\n", i, val, val2);
}
#endif
return;
}
if (mode==8) { // set TXE for qnum
OS_REG_WRITE(ah, AR_Q_TXE, 1<<qnum);
return;
}
if (mode==9) {
return;
}
if (mode >= 1) { // initiate cont tx operation
/* Disable AGC to A2 */
#if !_MAVERICK_STA_
qnum = (int)ds;
#else
/* handle the x86_64 case - we know ds is 32-bit, so cast is OK */
qnum = (int)(uintptr_t)ds;
#endif
OS_REG_WRITE(ah, AR_PHY_TEST,
(OS_REG_READ(ah, AR_PHY_TEST) | PHY_AGC_CLR) );
OS_REG_WRITE(ah, 0x9864, OS_REG_READ(ah, 0x9864) | 0x7f000);
OS_REG_WRITE(ah, 0x9924, OS_REG_READ(ah, 0x9924) | 0x7f00fe);
OS_REG_WRITE(ah, AR_DIAG_SW,
(OS_REG_READ(ah, AR_DIAG_SW) | (AR_DIAG_FORCE_RX_CLEAR+AR_DIAG_IGNORE_VIRT_CS)) );
OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); // set receive disable
if (mode == 3 || mode == 4) {
int txcfg;
if (mode == 3) {
OS_REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 100);
OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 100);
OS_REG_WRITE(ah, AR_TIME_OUT, 2);
OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, 100);
}
OS_REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
OS_REG_WRITE(ah, AR_D_FPCTL, 0x10|qnum); // enable prefetch on qnum
txcfg = 5 | (6<<AR_FTRIG_S);
OS_REG_WRITE(ah, AR_TXCFG, txcfg);
OS_REG_WRITE(ah, AR_QMISC(qnum), // set QCU modes
AR_Q_MISC_DCU_EARLY_TERM_REQ
+AR_Q_MISC_FSP_ASAP
+AR_Q_MISC_CBR_INCR_DIS1
+AR_Q_MISC_CBR_INCR_DIS0
);
/* stop tx dma all all except qnum */
qbits = 0x3ff;
qbits &= ~(1<<qnum);
for (i=0; i<10; i++) {
if (i==qnum) continue;
OS_REG_WRITE(ah, AR_Q_TXD, 1<<i);
}
OS_REG_WRITE(ah, AR_Q_TXD, qbits);
/* clear and freeze MIB counters */
OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC);
OS_REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
OS_REG_WRITE(ah, AR_DMISC(qnum),
(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL << AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
+(AR_D_MISC_ARB_LOCKOUT_IGNORE)
+(AR_D_MISC_POST_FR_BKOFF_DIS)
+(AR_D_MISC_VIR_COL_HANDLING_IGNORE << AR_D_MISC_VIR_COL_HANDLING_S)
);
for(i=0; i<HAL_NUM_TX_QUEUES+2; i++) { // disconnect QCUs
if (i==qnum) continue;
OS_REG_WRITE(ah, AR_DQCUMASK(i), 0);
}
}
}
if (mode == 0) {
OS_REG_WRITE(ah, AR_PHY_TEST,
(OS_REG_READ(ah, AR_PHY_TEST) & ~PHY_AGC_CLR) );
OS_REG_WRITE(ah, AR_DIAG_SW,
(OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_FORCE_RX_CLEAR+AR_DIAG_IGNORE_VIRT_CS)) );
}
}
void
ar9300DumpRegs(FILE *fd, int what)
{
#define N(a) (sizeof(a) / sizeof(a[0]))
static const HAL_REG regs[] = {
/* NB: keep these sorted by address */
{ "CR", AR_CR },
{ "HPRXDP", AR_HP_RXDP },
{ "LPRXDP", AR_LP_RXDP },
{ "CFG", AR_CFG },
{ "IER", AR_IER },
{ "TXCFG", AR_TXCFG },
{ "RXCFG", AR_RXCFG },
{ "MIBC", AR_MIBC },
{ "TOPS", AR_TOPS },
{ "RXNPTO", AR_RXNPTO },
{ "TXNPTO", AR_TXNPTO },
{ "RPGTO", AR_RPGTO },
{ "MACMISC", AR_MACMISC },
{ "D_SIFS", AR_D_GBL_IFS_SIFS },
{ "D_SEQNUM", AR_D_SEQNUM },
{ "D_SLOT", AR_D_GBL_IFS_SLOT },
{ "D_EIFS", AR_D_GBL_IFS_EIFS },
{ "D_MISC", AR_D_GBL_IFS_MISC },
{ "D_TXPSE", AR_D_TXPSE },
{ "RC", AR9300_HOSTIF_OFFSET(HOST_INTF_RESET_CONTROL) },
// { "SCR", AR_SCR },
// { "INTPEND", AR_INTPEND },
// { "SFR", AR_SFR },
// { "PCICFG", AR_PCICFG },
// { "GPIOCR", AR_GPIOCR },
{ "SREV", AR9300_HOSTIF_OFFSET(HOST_INTF_SREV) },
{ "STA_ID0", AR_STA_ID0 },
{ "STA_ID1", AR_STA_ID1 },
{ "BSS_ID0", AR_BSS_ID0 },
{ "BSS_ID1", AR_BSS_ID1 },
{ "TIME_OUT", AR_TIME_OUT },
{ "RSSI_THR", AR_RSSI_THR },
{ "USEC", AR_USEC },
// { "BEACON", AR_BEACON },
// { "CFP_PER", AR_CFP_PERIOD },
// { "TIMER0", AR_TIMER0 },
// { "TIMER1", AR_TIMER1 },
// { "TIMER2", AR_TIMER2 },
// { "TIMER3", AR_TIMER3 },
// { "CFP_DUR", AR_CFP_DUR },
{ "RX_FILTR", AR_RX_FILTER },
{ "MCAST_0", AR_MCAST_FIL0 },
{ "MCAST_1", AR_MCAST_FIL1 },
{ "DIAG_SW", AR_DIAG_SW },
{ "TSF_L32", AR_TSF_L32 },
{ "TSF_U32", AR_TSF_U32 },
{ "TST_ADAC", AR_TST_ADDAC },
{ "DEF_ANT", AR_DEF_ANTENNA },
{ "LAST_TST", AR_LAST_TSTP },
{ "NAV", AR_NAV },
{ "RTS_OK", AR_RTS_OK },
{ "RTS_FAIL", AR_RTS_FAIL },
{ "ACK_FAIL", AR_ACK_FAIL },
{ "FCS_FAIL", AR_FCS_FAIL },
{ "BEAC_CNT", AR_BEACON_CNT },
#ifdef AH_SUPPORT_XR
{ "XRMODE", AR_XRMODE },
{ "XRDEL", AR_XRDEL },
{ "XRTO", AR_XRTO },
{ "XRCRP", AR_XRCRP },
{ "XRSTMP", AR_XRSTMP },
#endif /* AH_SUPPORT_XR */
{ "SLEEP1", AR_SLEEP1 },
{ "SLEEP2", AR_SLEEP2 },
// { "SLEEP3", AR_SLEEP3 },
{ "BSSMSKL", AR_BSSMSKL },
{ "BSSMSKU", AR_BSSMSKU },
{ "TPC", AR_TPC },
{ "TFCNT", AR_TFCNT },
{ "RFCNT", AR_RFCNT },
{ "RCCNT", AR_RCCNT },
{ "CCCNT", AR_CCCNT },
// { "NOACK", AR_NOACK },
{ "PHY_ERR", AR_PHY_ERR },
// { "QOSCTL", AR_QOS_CONTROL },
// { "QOSSEL", AR_QOS_SELECT },
// { "MISCMODE", AR_MISC_MODE },
// { "FILTOFDM", AR_FILTOFDM },
// { "FILTCCK", AR_FILTCCK },
// { "PHYCNT1", AR_PHYCNT1 },
// { "PHYCMSK1", AR_PHYCNTMASK1 },
// { "PHYCNT2", AR_PHYCNT2 },
// { "PHYCMSK2", AR_PHYCNTMASK2 },
};
int i;
u_int32_t v;
if (what & DUMP_BASIC) {
ath_hal_dumpregs(fd, regs, N(regs));
}
if (what & DUMP_INTERRUPT) {
/* Interrupt registers */
if (what & DUMP_BASIC)
fprintf(fd, "\n");
fprintf(fd, "IMR: %08x S0 %08x S1 %08x S2 %08x S3 %08x S4 %08x\n"
, OS_REG_READ(ah, AR_IMR)
, OS_REG_READ(ah, AR_IMR_S0)
, OS_REG_READ(ah, AR_IMR_S1)
, OS_REG_READ(ah, AR_IMR_S2)
, OS_REG_READ(ah, AR_IMR_S3)
, OS_REG_READ(ah, AR_IMR_S4)
);
fprintf(fd, "ISR: %08x S0 %08x S1 %08x S2 %08x S3 %08x S4 %08x\n"
, OS_REG_READ(ah, AR_ISR)
, OS_REG_READ(ah, AR_ISR_S0)
, OS_REG_READ(ah, AR_ISR_S1)
, OS_REG_READ(ah, AR_ISR_S2)
, OS_REG_READ(ah, AR_ISR_S3)
, OS_REG_READ(ah, AR_ISR_S4)
);
}
if (what & DUMP_QCU) {
/* QCU registers */
if (what & (DUMP_BASIC|DUMP_INTERRUPT))
fprintf(fd, "\n");
fprintf(fd, "%-8s %08x %-8s %08x %-8s %08x\n"
, "Q_TXE", OS_REG_READ(ah, AR_Q_TXE)
, "Q_TXD", OS_REG_READ(ah, AR_Q_TXD)
, "Q_RDYTIMSHD", OS_REG_READ(ah, AR_Q_RDYTIMESHDN)
);
fprintf(fd, "Q_ONESHOTARM_SC %08x Q_ONESHOTARM_CC %08x\n"
, OS_REG_READ(ah, AR_Q_ONESHOTARM_SC)
, OS_REG_READ(ah, AR_Q_ONESHOTARM_CC)
);
for (i = 0; i < 10; i++)
fprintf(fd, "Q[%u] TXDP %08x CBR %08x RDYT %08x MISC %08x STS %08x\n"
, i
, OS_REG_READ(ah, AR_QTXDP(i))
, OS_REG_READ(ah, AR_QCBRCFG(i))
, OS_REG_READ(ah, AR_QRDYTIMECFG(i))
, OS_REG_READ(ah, AR_QMISC(i))
, OS_REG_READ(ah, AR_QSTS(i))
);
}
if (what & DUMP_DCU) {
/* DCU registers */
if (what & (DUMP_BASIC|DUMP_INTERRUPT|DUMP_QCU))
fprintf(fd, "\n");
for (i = 0; i < 10; i++)
fprintf(fd, "D[%u] MASK %08x IFS %08x RTRY %08x CHNT %08x MISC %06x\n"
, i
, OS_REG_READ(ah, AR_DQCUMASK(i))
, OS_REG_READ(ah, AR_DLCL_IFS(i))
, OS_REG_READ(ah, AR_DRETRY_LIMIT(i))
, OS_REG_READ(ah, AR_DCHNTIME(i))
, OS_REG_READ(ah, AR_DMISC(i))
);
}
for (i = 0; i < 10; i++) {
u_int32_t f0 = OS_REG_READ(ah, AR_D_TXBLK_DATA((i<<8)|0x00));
u_int32_t f1 = OS_REG_READ(ah, AR_D_TXBLK_DATA((i<<8)|0x40));
u_int32_t f2 = OS_REG_READ(ah, AR_D_TXBLK_DATA((i<<8)|0x80));
u_int32_t f3 = OS_REG_READ(ah, AR_D_TXBLK_DATA((i<<8)|0xc0));
if (f0 || f1 || f2 || f3)
fprintf(fd,
"D[%u] XMIT MASK %08x %08x %08x %08x\n",
i, f0, f1, f2, f3);
}
if (what & DUMP_KEYCACHE)
ath_hal_dumpkeycache(fd, 128,
OS_REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_CRPT_MIC_ENABLE);
if (what & DUMP_BASEBAND) {
int reg;
if (what &~ DUMP_BASEBAND)
fprintf(fd, "\n");
for (reg = 0x9800; reg <= 0xa480; reg += 4) {
printf("%X %.8X\n", reg, OS_REG_READ(ah, reg));
}
#if 0
ath_hal_dumprange(fd, 0x9800, 0x987c);
ath_hal_dumprange(fd, 0x9900, 0x995c);
ath_hal_dumprange(fd, 0x9c00, 0x9c1c);
ath_hal_dumprange(fd, 0xa180, 0xa238);
#endif
}
if (what & DUMP_LA) {
int reg;
for (reg = AR_MAC_PCU_TRACE_REG_START, i = 0; reg < AR_MAC_PCU_TRACE_REG_END; reg += 16) {
printf("0x%X: 0x%.8X 0x%.8X 0x%.8X 0x%.8X\n", reg,
OS_REG_READ(ah, reg + 0),
OS_REG_READ(ah, reg + 4),
OS_REG_READ(ah, reg + 8),
OS_REG_READ(ah, reg + 12));
}
}
if (what & DUMP_DMADBG) {
int reg;
for (reg = AR_DMADBG_0, i = 0; reg <= AR_DMADBG_7; reg += 4) {
printf("0x%X: 0x%.8X\n", reg, OS_REG_READ(ah, reg));
}
}
#undef N
}
#include "ar9300/ar9300reg.h"
static const HAL_REGRANGE ar9300PublicRegs[] = {
/* NB: keep these sorted by address */
{ AR_CR, AR_IER },
{ AR_TXCFG, AR_RXCFG },
{ AR_MIBC, AR_MACMISC },
{ AR_Q0_TXDP, AR_QTXDP(9) },
{ AR_Q_TXE },
{ AR_Q_TXD },
{ AR_Q0_CBRCFG, AR_QCBRCFG(9) },
{ AR_Q0_RDYTIMECFG, AR_QRDYTIMECFG(9) },
{ AR_Q_ONESHOTARM_SC },
{ AR_Q_ONESHOTARM_CC },
{ AR_Q0_MISC, AR_QMISC(9) },
{ AR_Q0_STS, AR_QSTS(9) },
{ AR_Q_RDYTIMESHDN },
{ AR_D0_QCUMASK, AR_DQCUMASK(9) },
{ AR_D0_LCL_IFS, AR_DLCL_IFS(9) },
{ AR_D0_RETRY_LIMIT, AR_DRETRY_LIMIT(9) },
{ AR_D0_CHNTIME, AR_DCHNTIME(9) },
{ AR_D0_MISC, AR_DMISC(9) },
{ AR_D_SEQNUM },
{ AR_D_GBL_IFS_SIFS },
{ AR_D_GBL_IFS_SLOT },
{ AR_D_GBL_IFS_EIFS },
{ AR_D_GBL_IFS_MISC },
{ AR_D_TXPSE },
#ifdef notdef
{ AR_D_TXBLK_DATA(0), /* XXX?? */ },
#endif