static void cpu9260_nand_hw_init(void)
{
	unsigned long csa;

	/* Enable CS3 */
	csa = at91_sys_read(AT91_MATRIX_EBICSA);
	at91_sys_write(AT91_MATRIX_EBICSA,
		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);

	/* Configure SMC CS3 for NAND/SmartMedia */
#if defined(CONFIG_CPU9G20)
	at91_sys_write(AT91_SMC_SETUP(3),
		       AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
		       AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
	at91_sys_write(AT91_SMC_PULSE(3),
		       AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(4) |
		       AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(4));
	at91_sys_write(AT91_SMC_CYCLE(3),
		       AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
	at91_sys_write(AT91_SMC_MODE(3),
		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
		       AT91_SMC_EXNWMODE_DISABLE |
		       AT91_SMC_DBW_8 |
		       AT91_SMC_TDF_(3));
#elif defined(CONFIG_CPU9260)
	at91_sys_write(AT91_SMC_SETUP(3),
		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
	at91_sys_write(AT91_SMC_PULSE(3),
		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
	at91_sys_write(AT91_SMC_CYCLE(3),
		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
	at91_sys_write(AT91_SMC_MODE(3),
		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
		       AT91_SMC_EXNWMODE_DISABLE |
		       AT91_SMC_DBW_8 |
		       AT91_SMC_TDF_(2));
#endif

	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);

	/* Configure RDY/BSY */
	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);

	/* Enable NandFlash */
	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
Exemple #2
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static void set_smc_timings(const u8 chipselect, const u16 cycle,
			    const u16 setup, const u16 pulse,
			    const u16 data_float, int use_iordy)
{
	unsigned long mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
			     AT91_SMC_BAT_SELECT;

	/* disable or enable waiting for IORDY signal */
	if (use_iordy)
		mode |= AT91_SMC_EXNWMODE_READY;

	/* add data float cycles if needed */
	if (data_float)
		mode |= AT91_SMC_TDF_(data_float);

	at91_sys_write(AT91_SMC_MODE(chipselect), mode);

	/* setup timings in SMC */
	at91_sys_write(AT91_SMC_SETUP(chipselect), AT91_SMC_NWESETUP_(setup) |
						   AT91_SMC_NCS_WRSETUP_(0) |
						   AT91_SMC_NRDSETUP_(setup) |
						   AT91_SMC_NCS_RDSETUP_(0));
	at91_sys_write(AT91_SMC_PULSE(chipselect), AT91_SMC_NWEPULSE_(pulse) |
						   AT91_SMC_NCS_WRPULSE_(cycle) |
						   AT91_SMC_NRDPULSE_(pulse) |
						   AT91_SMC_NCS_RDPULSE_(cycle));
	at91_sys_write(AT91_SMC_CYCLE(chipselect), AT91_SMC_NWECYCLE_(cycle) |
						   AT91_SMC_NRDCYCLE_(cycle));
}
static void otc570_nand_hw_init(void)
{
	unsigned long csa;

	/* Enable CS3 */
	csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
	at91_sys_write(AT91_MATRIX_EBI0CSA,
		csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);

	/* Configure SMC CS3 for NAND/SmartMedia */
	at91_sys_write(AT91_SMC_SETUP(3),
		AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
		AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
	at91_sys_write(AT91_SMC_PULSE(3),
		AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
		AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
	at91_sys_write(AT91_SMC_CYCLE(3),
		AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
	at91_sys_write(AT91_SMC_MODE(3),
		AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
		AT91_SMC_EXNWMODE_DISABLE |
		AT91_SMC_DBW_8 |
		AT91_SMC_TDF_(2));

	/* Configure RDY/BSY */
	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);

	/* Enable NandFlash */
	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
Exemple #4
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static void afeb9260_nand_hw_init(void)
{
	unsigned long csa;

	/* Enable CS3 */
	csa = at91_sys_read(AT91_MATRIX_EBICSA);
	at91_sys_write(AT91_MATRIX_EBICSA,
		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);

	/* Configure SMC CS3 for NAND/SmartMedia */
	at91_sys_write(AT91_SMC_SETUP(3),
		       AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
		       AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
	at91_sys_write(AT91_SMC_PULSE(3),
		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
	at91_sys_write(AT91_SMC_CYCLE(3),
		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
	at91_sys_write(AT91_SMC_MODE(3),
		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
		       AT91_SMC_EXNWMODE_DISABLE |
		       AT91_SMC_DBW_8 |
		       AT91_SMC_TDF_(2));

	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);

	/* Configure RDY/BSY */
	at91_set_gpio_input(AT91_PIN_PC13, 1);

	/* Enable NandFlash */
	at91_set_gpio_output(AT91_PIN_PC14, 1);
}
Exemple #5
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void __init sam9_smc_configure(int cs, struct sam9_smc_config* config)
{
	
	at91_sys_write(AT91_SMC_SETUP(cs),
		  AT91_SMC_NWESETUP_(config->nwe_setup)
		| AT91_SMC_NCS_WRSETUP_(config->ncs_write_setup)
		| AT91_SMC_NRDSETUP_(config->nrd_setup)
		| AT91_SMC_NCS_RDSETUP_(config->ncs_read_setup)
	);

	
	at91_sys_write(AT91_SMC_PULSE(cs),
		  AT91_SMC_NWEPULSE_(config->nwe_pulse)
		| AT91_SMC_NCS_WRPULSE_(config->ncs_write_pulse)
                | AT91_SMC_NRDPULSE_(config->nrd_pulse)
		| AT91_SMC_NCS_RDPULSE_(config->ncs_read_pulse)
	);

	
	at91_sys_write(AT91_SMC_CYCLE(cs),
		  AT91_SMC_NWECYCLE_(config->write_cycle)
		| AT91_SMC_NRDCYCLE_(config->read_cycle)
	);

	
	at91_sys_write(AT91_SMC_MODE(cs),
		  config->mode
		| AT91_SMC_TDF_(config->tdf_cycles)
	);
}
Exemple #6
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void init_smc_ddr()
{
#if 0
	printf("leds should change now!\n");
  	at91_set_gpio_output(AT91_PIN_PA0, 1);
	at91_set_gpio_output(AT91_PIN_PA1, 0);

	vTaskDelay(2000);
	printf("leds should change now!\n");
	at91_set_gpio_value(AT91_PIN_PA0, 0);
	at91_set_gpio_value(AT91_PIN_PA1, 1);
#endif
  
/* Configure the EBI1 pins for the wr switch */
	int i;
	
	/* PC16..31: periphA as EBI1_D16..31 */
	for (i = AT91_PIN_PC16; i <= AT91_PIN_PC31; i++){
		at91_set_A_periph(i, 0);
	}
	/* PC2 and PC3 too: EBI1_A19 EBI1_A20 */
	at91_set_A_periph(AT91_PIN_PC2, 0);
	at91_set_A_periph(AT91_PIN_PC3, 0);
	
	
	/* FIXME: We should pull rst high for when it is programmed */

	/* Then, write the EBI1 configuration (NCS0 == 0x1000.0000) */
	at91_sys_write(AT91_SMC_SETUP(0),
				AT91_SMC_NWESETUP_(4) |
				AT91_SMC_NCS_WRSETUP_(2) |
				AT91_SMC_NRDSETUP_(4) |
				AT91_SMC_NCS_RDSETUP_(2));
	at91_sys_write(AT91_SMC_PULSE(0),
				AT91_SMC_NWEPULSE_(30) |
				AT91_SMC_NCS_WRPULSE_(34) |
				AT91_SMC_NRDPULSE_(30) |
				AT91_SMC_NCS_RDPULSE_(34));
	at91_sys_write(AT91_SMC_CYCLE(0),
				AT91_SMC_NWECYCLE_(40) |
				AT91_SMC_NRDCYCLE_(40));
	at91_sys_write(AT91_SMC_MODE(0),
				AT91_SMC_DBW_32 |
				AT91_SMC_TDF_(0) |
				AT91_SMC_READMODE |
				AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_FROZEN);
	

	
	
}
void __init at91_add_device_nand(struct at91_nand_data *data)
{
	unsigned long csa, mode;

	if (!data)
		return;

	csa = at91_sys_read(AT91_MATRIX_EBICSA);
	at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC);

	/* set the bus interface characteristics */
	at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
			| AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));

	at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(2) | AT91_SMC_NCS_WRPULSE_(5)
			| AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(5));

	at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));

	if (data->bus_width_16)
		mode = AT91_SMC_DBW_16;
	else
		mode = AT91_SMC_DBW_8;
	at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(1));

	/* enable pin */
	if (data->enable_pin)
		at91_set_gpio_output(data->enable_pin, 1);

	/* ready/busy pin */
	if (data->rdy_pin)
		at91_set_gpio_input(data->rdy_pin, 1);

	/* card detect pin */
	if (data->det_pin)
		at91_set_gpio_input(data->det_pin, 1);

	at91_set_A_periph(AT91_PIN_PC0, 0);		/* NANDOE */
	at91_set_A_periph(AT91_PIN_PC1, 0);		/* NANDWE */

	nand_data = *data;
	platform_device_register(&at91_nand_device);
}
Exemple #8
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static void __init ek_add_device_dm9000(void)
{
	/*
	 * Configure Chip-Select 2 on SMC for the DM9000.
	 * Note: These timings were calculated for MASTER_CLOCK = 100000000
	 *  according to the DM9000 timings.
	 */
	at91_sys_write(AT91_SMC_SETUP(2), AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) | AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
	at91_sys_write(AT91_SMC_PULSE(2), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) | AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
	at91_sys_write(AT91_SMC_CYCLE(2), AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
	at91_sys_write(AT91_SMC_MODE(2), AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));

	/* Configure Reset signal as output */
	at91_set_gpio_output(AT91_PIN_PC10, 0);

	/* Configure Interrupt pin as input, no pull-up */
	at91_set_gpio_input(AT91_PIN_PC11, 0);

	platform_device_register(&at91sam9261_dm9000_device);
}
static void at91sam9261ek_nand_hw_init(void)
{
	unsigned long csa;

	/* Enable CS3 */
	csa = at91_sys_read(AT91_MATRIX_EBICSA);
	at91_sys_write(AT91_MATRIX_EBICSA,
		       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);

	/* Configure SMC CS3 for NAND/SmartMedia */
	at91_sys_write(AT91_SMC_SETUP(3),
		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
	at91_sys_write(AT91_SMC_PULSE(3),
		       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
	at91_sys_write(AT91_SMC_CYCLE(3),
		       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
	at91_sys_write(AT91_SMC_MODE(3),
		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
		       AT91_SMC_EXNWMODE_DISABLE |
#ifdef CFG_NAND_DBW_16
		       AT91_SMC_DBW_16 |
#else /* CFG_NAND_DBW_8 */
		       AT91_SMC_DBW_8 |
#endif
		       AT91_SMC_TDF_(2));

	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);

	/* Configure RDY/BSY */
	at91_set_gpio_input(AT91_PIN_PC15, 1);

	/* Enable NandFlash */
	at91_set_gpio_output(AT91_PIN_PC14, 1);

	at91_set_A_periph(AT91_PIN_PC0, 0);	/* NANDOE */
	at91_set_A_periph(AT91_PIN_PC1, 0);	/* NANDWE */
}
Exemple #10
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static __init void cap9adk_add_device_nor(void)
{
	unsigned long csa;

	csa = at91_sys_read(AT91_MATRIX_EBICSA);
	at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);

	/* set the bus interface characteristics */
	at91_sys_write(AT91_SMC_SETUP(0), AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2)
			| AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2));

	at91_sys_write(AT91_SMC_PULSE(0), AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10)
			| AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10));

	at91_sys_write(AT91_SMC_CYCLE(0), AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));

	at91_sys_write(AT91_SMC_MODE(0), AT91_SMC_READMODE | AT91_SMC_WRITEMODE
			| AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE
			| AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));

	platform_device_register(&cap9adk_nor_flash);
}
Exemple #11
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static void at91cap9_nor_hw_init(void)
{
    unsigned long csa;

    /* Ensure EBI supply is 3.3V */
    csa = at91_sys_read(AT91_MATRIX_EBICSA);
    at91_sys_write(AT91_MATRIX_EBICSA,
                   csa | AT91_MATRIX_EBI_VDDIOMSEL_3_3V);
    /* Configure SMC CS0 for parallel flash */
    at91_sys_write(AT91_SMC_SETUP(0),
                   AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(2) |
                   AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(2));
    at91_sys_write(AT91_SMC_PULSE(0),
                   AT91_SMC_NWEPULSE_(8) | AT91_SMC_NCS_WRPULSE_(10) |
                   AT91_SMC_NRDPULSE_(8) | AT91_SMC_NCS_RDPULSE_(10));
    at91_sys_write(AT91_SMC_CYCLE(0),
                   AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
    at91_sys_write(AT91_SMC_MODE(0),
                   AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
                   AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_BAT_WRITE |
                   AT91_SMC_DBW_16 | AT91_SMC_TDF_(1));
}
static void at91sam9261ek_dm9000_hw_init(void)
{
	/* Configure SMC CS2 for DM9000 */
	at91_sys_write(AT91_SMC_SETUP(2),
		       AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
		       AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
	at91_sys_write(AT91_SMC_PULSE(2),
		       AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) |
		       AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
	at91_sys_write(AT91_SMC_CYCLE(2),
		       AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
	at91_sys_write(AT91_SMC_MODE(2),
		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
		       AT91_SMC_EXNWMODE_DISABLE |
		       AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
		       AT91_SMC_TDF_(1));

	/* Configure Reset signal as output */
	at91_set_gpio_output(AT91_PIN_PC10, 0);

	/* Configure Interrupt pin as input, no pull-up */
	at91_set_gpio_input(AT91_PIN_PC11, 0);
}
Exemple #13
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static void at91cap9_nand_hw_init(void)
{
    unsigned long csa;

    /* Enable CS3 */
    csa = at91_sys_read(AT91_MATRIX_EBICSA);
    at91_sys_write(AT91_MATRIX_EBICSA,
                   csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA |
                   AT91_MATRIX_EBI_VDDIOMSEL_3_3V);

    /* Configure SMC CS3 for NAND/SmartMedia */
    at91_sys_write(AT91_SMC_SETUP(3),
                   AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(1) |
                   AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(1));
    at91_sys_write(AT91_SMC_PULSE(3),
                   AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(6) |
                   AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(6));
    at91_sys_write(AT91_SMC_CYCLE(3),
                   AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
    at91_sys_write(AT91_SMC_MODE(3),
                   AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
                   AT91_SMC_EXNWMODE_DISABLE |
#ifdef CFG_NAND_DBW_16
                   AT91_SMC_DBW_16 |
#else /* CFG_NAND_DBW_8 */
                   AT91_SMC_DBW_8 |
#endif
                   AT91_SMC_TDF_(1));

    at91_sys_write(AT91_PMC_PCER, 1 << AT91CAP9_ID_PIOABCD);

    /* RDY/BSY is not connected */

    /* Enable NandFlash */
    at91_set_gpio_output(AT91_PIN_PD15, 1);
}
Exemple #14
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/*
 * initialize the som-9g20 for apcc.
 */
static void apcc_init(void)
{
    unsigned int cnt = 10000;

    { /* initialize PCK1 - this is output to the FPGA as clock reference.
       * select PLLA as clock source (18.432 * 42) and div by 32
       * 24.192 mHz.
       */
	at91_sys_write(AT91_PMC_PCKR(1), AT91_PMC_CSS_PLLA | AT91_PMC_PRES_32);

	/* Enable PCK1 output */
	at91_sys_write(AT91_PMC_SCER, AT91_PMC_PCK1);

	/* Wait for PCK1 to come ready or timeout */
	while (cnt-- > 0) {
	    volatile unsigned long scsr = at91_sys_read(AT91_PMC_SCSR);
	    if ((scsr & AT91_PMC_PCK1RDY) != 0) {
		break;
	    }
	}

	/* configure PB31 to be used as PCK1 */
	at91_set_A_periph(AT91_PIN_PB31, 0);
    }

    { /* initialize sensys fpga */

	/*
	 * Configure CS0 (Chip Select 0) for FPGA (SMC @ FFFFEC00)
	 *
	 * SETUP - 0x1F3F1F3F
	 * PULSE - 0x403F403F
	 * CYCLE - 0x013E013E
	 * MODE  - 0x000F0003
	 */
	at91_sys_write(AT91_SMC_SETUP(0),
		       AT91_SMC_NWESETUP_(4) | AT91_SMC_NCS_WRSETUP_(4) |
		       AT91_SMC_NRDSETUP_(4) | AT91_SMC_NCS_RDSETUP_(4));

	at91_sys_write(AT91_SMC_PULSE(0),
		       AT91_SMC_NWEPULSE_(20) | AT91_SMC_NCS_WRPULSE_(20) |
		       AT91_SMC_NRDPULSE_(22) | AT91_SMC_NCS_RDPULSE_(22));

	at91_sys_write(AT91_SMC_CYCLE(0),
		       AT91_SMC_NWECYCLE_(35) | AT91_SMC_NRDCYCLE_(29));

	at91_sys_write(AT91_SMC_MODE(0),
		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
		       AT91_SMC_EXNWMODE_DISABLE |
		       AT91_SMC_DBW_8 |
		       AT91_SMC_TDF_(1));
    }

    {
	/* to conserve power, disable the AtoD of phy. 
	 */
        at91_set_gpio_output(AT91_PIN_PA22, 1);
    }

#ifdef CONFIG_HW_WATCHDOG
    {	/* set up watchdog port */
        at91_set_gpio_output(AT91_PIN_PB18, 1);
	WATCHDOG_RESET();
    }
#endif
}
void __naked __bare_init board_init_lowlevel(void)
{
	u32 r;
	int i;

	at91_sys_write(AT91_WDT_MR, CONFIG_SYS_WDTC_WDMR_VAL);

	/* configure PIOx as EBI0 D[16-31] */
#ifdef CONFIG_ARCH_AT91SAM9263
	__raw_writel(CONFIG_SYS_PIOD_PDR_VAL1, AT91_BASE_PIOD + PIO_PDR);
	__raw_writel(CONFIG_SYS_PIOD_PPUDR_VAL, AT91_BASE_PIOD + PIO_PUDR);
	__raw_writel(CONFIG_SYS_PIOD_PPUDR_VAL, AT91_BASE_PIOD + PIO_ASR);
#else
	__raw_writel(CONFIG_SYS_PIOC_PDR_VAL1, AT91_BASE_PIOC + PIO_PDR);
	__raw_writel(CONFIG_SYS_PIOC_PPUDR_VAL, AT91_BASE_PIOC + PIO_PUDR);
#endif

#if defined(AT91_MATRIX_EBI0CSA)
	at91_sys_write(AT91_MATRIX_EBI0CSA, CONFIG_SYS_MATRIX_EBI0CSA_VAL);
#else /* AT91_MATRIX_EBICSA */
	at91_sys_write(AT91_MATRIX_EBICSA, CONFIG_SYS_MATRIX_EBICSA_VAL);
#endif

	/* flash */
	at91_sys_write(AT91_SMC_MODE(0), CONFIG_SYS_SMC0_MODE0_VAL);

	at91_sys_write(AT91_SMC_CYCLE(0), CONFIG_SYS_SMC0_CYCLE0_VAL);

	at91_sys_write(AT91_SMC_PULSE(0), CONFIG_SYS_SMC0_PULSE0_VAL);

	at91_sys_write(AT91_SMC_SETUP(0), CONFIG_SYS_SMC0_SETUP0_VAL);

	/*
	 * PMC Check if the PLL is already initialized
	 */
	r = at91_sys_read(AT91_PMC_MCKR);
	if (r & AT91_PMC_CSS)
		goto end;

	/*
	 * Enable the Main Oscillator
	 */
	at91_sys_write(AT91_CKGR_MOR, CONFIG_SYS_MOR_VAL);

	do {
		r = at91_sys_read(AT91_PMC_SR);
	} while (!(r & AT91_PMC_MOSCS));

	/*
	 * PLLAR: x MHz for PCK
	 */
	at91_sys_write(AT91_CKGR_PLLAR, CONFIG_SYS_PLLAR_VAL);

	do {
		r = at91_sys_read(AT91_PMC_SR);
	} while (!(r & AT91_PMC_LOCKA));

	/*
	 * PCK/x = MCK Master Clock from SLOW
	 */
	at91_sys_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR1_VAL);

	pmc_check_mckrdy();

	/*
	 * PCK/x = MCK Master Clock from PLLA
	 */
	at91_sys_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL);

	pmc_check_mckrdy();

	/*
	 * Init SDRAM
	 */

	/*
	 * SDRAMC Check if Refresh Timer Counter is already initialized
	 */
	r = at91_sys_read(AT91_SDRAMC_TR);
	if (r)
		goto end;

	/* SDRAMC_MR : Normal Mode */
	at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);

	/* SDRAMC_TR - Refresh Timer register */
	at91_sys_write(AT91_SDRAMC_TR, CONFIG_SYS_SDRC_TR_VAL1);

	/* SDRAMC_CR - Configuration register*/
	at91_sys_write(AT91_SDRAMC_CR, CONFIG_SYS_SDRC_CR_VAL);

	/* Memory Device Type */
	at91_sys_write(AT91_SDRAMC_MDR, CONFIG_SYS_SDRC_MDR_VAL);

	/* SDRAMC_MR : Precharge All */
	at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE);

	/* access SDRAM */
	access_sdram();

	/* SDRAMC_MR : refresh */
	at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_REFRESH);

	/* access SDRAM 8 times */
	for (i = 0; i < 8; i++)
		access_sdram();

	/* SDRAMC_MR : Load Mode Register */
	at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_LMR);

	/* access SDRAM */
	access_sdram();

	/* SDRAMC_MR : Normal Mode */
	at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);

	/* access SDRAM */
	access_sdram();

	/* SDRAMC_TR : Refresh Timer Counter */
	at91_sys_write(AT91_SDRAMC_TR, CONFIG_SYS_SDRC_TR_VAL2);

	/* access SDRAM */
	access_sdram();

	/* User reset enable*/
	at91_sys_write(AT91_RSTC_MR, CONFIG_SYS_RSTC_RMR_VAL);

#ifdef CONFIG_SYS_MATRIX_MCFG_REMAP
	/* MATRIX_MCFG - REMAP all masters */
	at91_sys_write(AT91_MATRIX_MCFG0, 0x1FF);
#endif

end:
	board_init_lowlevel_return();
}