static TIMER_CALLBACK( pr8210_bit_callback ) { attotime duration = ATTOTIME_IN_MSEC(30); const device_config *laserdisc = ptr; UINT8 bitsleft = param >> 16; UINT8 data = param; /* if we have bits, process */ if (bitsleft != 0) { /* assert the line and set a timer for deassertion */ laserdisc_line_w(laserdisc, LASERDISC_LINE_CONTROL, ASSERT_LINE); timer_set(machine, ATTOTIME_IN_USEC(250), ptr, 0, pr8210_bit_off_callback); /* space 0 bits apart by 1msec, and 1 bits by 2msec */ duration = attotime_mul(ATTOTIME_IN_MSEC(1), (data & 0x80) ? 2 : 1); data <<= 1; bitsleft--; } /* if we're out of bits, queue up the next command */ else if (bitsleft == 0 && pr8210_command_buffer_in != pr8210_command_buffer_out) { data = pr8210_command_buffer[pr8210_command_buffer_out++ % ARRAY_LENGTH(pr8210_command_buffer)]; bitsleft = 12; } timer_adjust_oneshot(pr8210_bit_timer, duration, (bitsleft << 16) | data); }
static void wd33c93_xferinfo_cmd( void ) { /* make the buffer available right away */ scsi_data.regs[WD_AUXILIARY_STATUS] |= ASR_DBR; scsi_data.regs[WD_AUXILIARY_STATUS] |= ASR_CIP; /* the command will be completed once the data is transferred */ timer_set( ATTOTIME_IN_MSEC(1), NULL, 0, wd33c93_deassert_cip ); }
static MACHINE_START( cidelsa ) { cidelsa_state *state = (cidelsa_state *)machine->driver_data; /* reset the CPU */ state->cdp1802_mode = CDP1802_MODE_RESET; timer_set(machine, ATTOTIME_IN_MSEC(200), NULL, 0, set_cpu_mode); /* register for state saving */ state_save_register_global(machine, state->cdp1802_mode); }
void pc_keyb_set_clock(int on) { on = on ? 1 : 0; if (pc_keyb.on != on) { if (!on) timer_adjust_oneshot(pc_keyb.timer, ATTOTIME_IN_MSEC(5), 0); else { if ( pc_keyb.self_test ) { /* The self test of the keyboard takes some time. 2 msec seems to work. */ /* This still needs to verified against a real keyboard. */ timer_adjust_oneshot(pc_keyb.timer, ATTOTIME_IN_MSEC( 2 ), 0); } else { timer_reset(pc_keyb.timer, attotime_never); pc_keyb.self_test = 0; } } pc_keyb.on = on; } }
static void sslam_play(const device_config *device, int track, int data) { int status = okim6295_r(device,0); if (data < 0x80) { if (track) { if (sslam_track != data) { sslam_track = data; sslam_bar = 1; if (status & 0x08) okim6295_w(device,0,0x40); okim6295_w(device,0,(0x80 | data)); okim6295_w(device,0,0x81); timer_adjust_periodic(music_timer, ATTOTIME_IN_MSEC(4), 0, ATTOTIME_IN_HZ(250)); /* 250Hz for smooth sequencing */ } } else { if ((status & 0x01) == 0) { okim6295_w(device,0,(0x80 | data)); okim6295_w(device,0,0x11); } else if ((status & 0x02) == 0) { okim6295_w(device,0,(0x80 | data)); okim6295_w(device,0,0x21); } else if ((status & 0x04) == 0) { okim6295_w(device,0,(0x80 | data)); okim6295_w(device,0,0x41); } } } else { /* use above 0x80 to turn off channels */ if (track) { timer_enable(music_timer,0); sslam_track = 0; sslam_melody = 0; sslam_bar = 0; } data &= 0x7f; okim6295_w(device,0,data); } }
void intelflash_write(int chip, UINT32 address, UINT32 data) { struct flash_chip *c; if( chip >= FLASH_CHIPS_MAX ) { logerror( "intelflash_write: invalid chip %d\n", chip ); return; } c = &chips[ chip ]; // logerror( "intelflash_write( %d, %08x, %08x )\n", chip, address, data ); switch( c->flash_mode ) { case FM_NORMAL: case FM_READSTATUS: case FM_READID: case FM_READAMDID3: switch( data & 0xff ) { case 0xf0: case 0xff: // reset chip mode c->flash_mode = FM_NORMAL; break; case 0x90: // read ID c->flash_mode = FM_READID; break; case 0x40: case 0x10: // program c->flash_mode = FM_WRITEPART1; break; case 0x50: // clear status reg c->status = 0x80; c->flash_mode = FM_READSTATUS; break; case 0x20: // block erase c->flash_mode = FM_CLEARPART1; break; case 0x60: // set master lock c->flash_mode = FM_SETMASTER; break; case 0x70: // read status c->flash_mode = FM_READSTATUS; break; case 0xaa: // AMD ID select part 1 if( ( address & 0xfff ) == 0x555 ) { c->flash_mode = FM_READAMDID1; } break; default: logerror( "Unknown flash mode byte %x\n", data & 0xff ); break; } break; case FM_READAMDID1: if( ( address & 0xffff ) == 0x2aa && ( data & 0xff ) == 0x55 ) { c->flash_mode = FM_READAMDID2; } else if( ( address & 0xffff ) == 0x2aaa && ( data & 0xff ) == 0x55 ) { c->flash_mode = FM_READAMDID2; } else { logerror( "unexpected %08x=%02x in FM_READAMDID1\n", address, data & 0xff ); c->flash_mode = FM_NORMAL; } break; case FM_READAMDID2: if( ( address & 0xffff ) == 0x555 && ( data & 0xff ) == 0x90 ) { c->flash_mode = FM_READAMDID3; } else if( ( address & 0xffff ) == 0x5555 && ( data & 0xff ) == 0x90 ) { c->flash_mode = FM_READAMDID3; } else if( ( address & 0xffff ) == 0x555 && ( data & 0xff ) == 0x80 ) { c->flash_mode = FM_ERASEAMD1; } else if( ( address & 0xffff ) == 0x5555 && ( data & 0xff ) == 0x80 ) { c->flash_mode = FM_ERASEAMD1; } else if( ( address & 0xffff ) == 0x555 && ( data & 0xff ) == 0xa0 ) { c->flash_mode = FM_BYTEPROGRAM; } else if( ( address & 0xffff ) == 0x5555 && ( data & 0xff ) == 0xa0 ) { c->flash_mode = FM_BYTEPROGRAM; } else if( ( address & 0xffff ) == 0x555 && ( data & 0xff ) == 0xf0 ) { c->flash_mode = FM_NORMAL; } else if( ( address & 0xffff ) == 0x5555 && ( data & 0xff ) == 0xf0 ) { c->flash_mode = FM_NORMAL; } else { logerror( "unexpected %08x=%02x in FM_READAMDID2\n", address, data & 0xff ); c->flash_mode = FM_NORMAL; } break; case FM_ERASEAMD1: if( ( address & 0xfff ) == 0x555 && ( data & 0xff ) == 0xaa ) { c->flash_mode = FM_ERASEAMD2; } else { logerror( "unexpected %08x=%02x in FM_ERASEAMD1\n", address, data & 0xff ); } break; case FM_ERASEAMD2: if( ( address & 0xffff ) == 0x2aa && ( data & 0xff ) == 0x55 ) { c->flash_mode = FM_ERASEAMD3; } else if( ( address & 0xffff ) == 0x2aaa && ( data & 0xff ) == 0x55 ) { c->flash_mode = FM_ERASEAMD3; } else { logerror( "unexpected %08x=%02x in FM_ERASEAMD2\n", address, data & 0xff ); } break; case FM_ERASEAMD3: if( ( address & 0xfff ) == 0x555 && ( data & 0xff ) == 0x10 ) { // chip erase memset( c->flash_memory, 0xff, c->size); c->status = 1 << 3; c->flash_mode = FM_ERASEAMD4; timer_adjust_oneshot( c->timer, ATTOTIME_IN_SEC( 17 ), 0 ); } else if( ( data & 0xff ) == 0x30 ) { // sector erase // clear the 4k/64k block containing the current address to all 0xffs switch( c->bits ) { case 8: { UINT8 *flash_memory = (UINT8 *)c->flash_memory; if (c->sector_is_4k) { memset( &flash_memory[ address & ~0xfff ], 0xff, 4 * 1024 ); c->erase_sector = address & ~0xfff; timer_adjust_oneshot( c->timer, ATTOTIME_IN_MSEC( 125 ), 0 ); } else { memset( &flash_memory[ address & ~0xffff ], 0xff, 64 * 1024 ); c->erase_sector = address & ~0xffff; timer_adjust_oneshot( c->timer, ATTOTIME_IN_SEC( 1 ), 0 ); } } break; case 16: { UINT16 *flash_memory = (UINT16 *)c->flash_memory; if (c->sector_is_4k) { memset( &flash_memory[ address & ~0x7ff ], 0xff, 4 * 1024 ); c->erase_sector = address & ~0x7ff; timer_adjust_oneshot( c->timer, ATTOTIME_IN_MSEC( 125 ), 0 ); } else { memset( &flash_memory[ address & ~0x7fff ], 0xff, 64 * 1024 ); c->erase_sector = address & ~0x7fff; timer_adjust_oneshot( c->timer, ATTOTIME_IN_SEC( 1 ), 0 ); } } break; } c->status = 1 << 3; c->flash_mode = FM_ERASEAMD4; } else { logerror( "unexpected %08x=%02x in FM_ERASEAMD3\n", address, data & 0xff ); } break; case FM_BYTEPROGRAM: switch( c->bits ) { case 8: { UINT8 *flash_memory = (UINT8 *)c->flash_memory; flash_memory[ address ] = data; } break; default: logerror( "FM_BYTEPROGRAM not supported when c->bits == %d\n", c->bits ); break; } c->flash_mode = FM_NORMAL; break; case FM_WRITEPART1: switch( c->bits ) { case 8: { UINT8 *flash_memory = (UINT8 *)c->flash_memory; flash_memory[ address ] = data; } break; case 16: { UINT16 *flash_memory = (UINT16 *)c->flash_memory; flash_memory[ address ] = data; } break; default: logerror( "FM_WRITEPART1 not supported when c->bits == %d\n", c->bits ); break; } c->status = 0x80; c->flash_mode = FM_READSTATUS; break; case FM_CLEARPART1: if( ( data & 0xff ) == 0xd0 ) { // clear the 64k block containing the current address to all 0xffs switch( c->bits ) { case 8: { UINT8 *flash_memory = (UINT8 *)c->flash_memory; memset( &flash_memory[ address & ~0xffff ], 0xff, 64 * 1024 ); } break; case 16: { UINT16 *flash_memory = (UINT16 *)c->flash_memory; memset( &flash_memory[ address & ~0x7fff ], 0xff, 64 * 1024 ); } break; default: logerror( "FM_CLEARPART1 not supported when c->bits == %d\n", c->bits ); break; } c->status = 0x00; c->flash_mode = FM_READSTATUS; timer_adjust_oneshot( c->timer, ATTOTIME_IN_SEC( 1 ), 0 ); break; } else { logerror( "unexpected %02x in FM_CLEARPART1\n", data & 0xff ); } break; case FM_SETMASTER: switch( data & 0xff ) { case 0xf1: c->flash_master_lock = 1; break; case 0xd0: c->flash_master_lock = 0; break; default: logerror( "unexpected %08x=%02x in FM_SETMASTER:\n", address, data & 0xff ); break; } c->flash_mode = FM_NORMAL; break; } }
static void wd33c93_selectxfer_cmd( void ) { UINT8 unit = wd33c93_getunit(); UINT8 newstatus; /* see if we can select that device */ if ( devices[unit] ) { if ( scsi_data.regs[WD_COMMAND_PHASE] < 0x45 ) { /* device is available */ int xfercount; int phase; /* do the request */ SCSISetCommand( devices[unit], &scsi_data.regs[WD_CDB_1], 12 ); SCSIExecCommand( devices[unit], &xfercount ); SCSIGetPhase( devices[unit], &phase ); /* set transfer count */ if ( wd33c93_get_xfer_count() > TEMP_INPUT_LEN ) { logerror( "WD33C93: Transfer count too big. Please increase TEMP_INPUT_LEN (size=%d)\n", wd33c93_get_xfer_count() ); wd33c93_set_xfer_count( TEMP_INPUT_LEN ); } switch( phase ) { case SCSI_PHASE_DATAIN: scsi_data.read_pending = 1; break; } } if ( scsi_data.read_pending ) { int len = TEMP_INPUT_LEN; if ( wd33c93_get_xfer_count() < len ) len = wd33c93_get_xfer_count(); memset( &scsi_data.temp_input[0], 0, TEMP_INPUT_LEN ); wd33c93_read_data( len, &scsi_data.temp_input[0] ); scsi_data.temp_input_pos = 0; scsi_data.read_pending = 0; } scsi_data.regs[WD_TARGET_LUN] = 0; scsi_data.regs[WD_CONTROL] |= CTRL_EDI; scsi_data.regs[WD_COMMAND_PHASE] = 0x60; /* signal transfer ready */ newstatus = CSR_SEL_XFER_DONE; /* if allowed disconnect, queue a service request */ if ( scsi_data.identify & 0x40 ) { /* queue disconnect message in */ scsi_data.busphase = PHS_MESS_IN; /* queue up a service request out in the future */ timer_set( ATTOTIME_IN_MSEC(50), NULL, 0, wd33c93_service_request ); } } else { /* device is not available */ newstatus = CSR_TIMEOUT; wd33c93_set_xfer_count( 0 ); } /* complete the command */ wd33c93_complete_cmd(newstatus); }
void intelfsh_device::write_full(UINT32 address, UINT32 data) { // logerror( "intelflash_write( %d, %08x, %08x )\n", chip, address, data ); switch( m_flash_mode ) { case FM_NORMAL: case FM_READSTATUS: case FM_READID: case FM_READAMDID3: switch( data & 0xff ) { case 0xf0: case 0xff: // reset chip mode m_flash_mode = FM_NORMAL; break; case 0x90: // read ID m_flash_mode = FM_READID; break; case 0x40: case 0x10: // program m_flash_mode = FM_WRITEPART1; break; case 0x50: // clear status reg m_status = 0x80; m_flash_mode = FM_READSTATUS; break; case 0x20: // block erase m_flash_mode = FM_CLEARPART1; break; case 0x60: // set master lock m_flash_mode = FM_SETMASTER; break; case 0x70: // read status m_flash_mode = FM_READSTATUS; break; case 0xaa: // AMD ID select part 1 if( ( address & 0xfff ) == 0x555 ) { m_flash_mode = FM_READAMDID1; } break; default: logerror( "Unknown flash mode byte %x\n", data & 0xff ); break; } break; case FM_READAMDID1: if( ( address & 0xffff ) == 0x2aa && ( data & 0xff ) == 0x55 ) { m_flash_mode = FM_READAMDID2; } else if( ( address & 0xffff ) == 0x2aaa && ( data & 0xff ) == 0x55 ) { m_flash_mode = FM_READAMDID2; } else { logerror( "unexpected %08x=%02x in FM_READAMDID1\n", address, data & 0xff ); m_flash_mode = FM_NORMAL; } break; case FM_READAMDID2: if( ( address & 0xffff ) == 0x555 && ( data & 0xff ) == 0x90 ) { m_flash_mode = FM_READAMDID3; } else if( ( address & 0xffff ) == 0x5555 && ( data & 0xff ) == 0x90 ) { m_flash_mode = FM_READAMDID3; } else if( ( address & 0xffff ) == 0x555 && ( data & 0xff ) == 0x80 ) { m_flash_mode = FM_ERASEAMD1; } else if( ( address & 0xffff ) == 0x5555 && ( data & 0xff ) == 0x80 ) { m_flash_mode = FM_ERASEAMD1; } else if( ( address & 0xffff ) == 0x555 && ( data & 0xff ) == 0xa0 ) { m_flash_mode = FM_BYTEPROGRAM; } else if( ( address & 0xffff ) == 0x5555 && ( data & 0xff ) == 0xa0 ) { m_flash_mode = FM_BYTEPROGRAM; } else if( ( address & 0xffff ) == 0x555 && ( data & 0xff ) == 0xf0 ) { m_flash_mode = FM_NORMAL; } else if( ( address & 0xffff ) == 0x5555 && ( data & 0xff ) == 0xf0 ) { m_flash_mode = FM_NORMAL; } else { logerror( "unexpected %08x=%02x in FM_READAMDID2\n", address, data & 0xff ); m_flash_mode = FM_NORMAL; } break; case FM_ERASEAMD1: if( ( address & 0xfff ) == 0x555 && ( data & 0xff ) == 0xaa ) { m_flash_mode = FM_ERASEAMD2; } else { logerror( "unexpected %08x=%02x in FM_ERASEAMD1\n", address, data & 0xff ); } break; case FM_ERASEAMD2: if( ( address & 0xffff ) == 0x2aa && ( data & 0xff ) == 0x55 ) { m_flash_mode = FM_ERASEAMD3; } else if( ( address & 0xffff ) == 0x2aaa && ( data & 0xff ) == 0x55 ) { m_flash_mode = FM_ERASEAMD3; } else { logerror( "unexpected %08x=%02x in FM_ERASEAMD2\n", address, data & 0xff ); } break; case FM_ERASEAMD3: if( ( address & 0xfff ) == 0x555 && ( data & 0xff ) == 0x10 ) { // chip erase for (offs_t offs = 0; offs < m_config.m_size; offs++) m_addrspace[0]->write_byte(offs, 0xff); m_status = 1 << 3; m_flash_mode = FM_ERASEAMD4; if (m_config.m_sector_is_4k) { timer_adjust_oneshot( m_timer, ATTOTIME_IN_SEC( 1 ), 0 ); } else { timer_adjust_oneshot( m_timer, ATTOTIME_IN_SEC( 16 ), 0 ); } } else if( ( data & 0xff ) == 0x30 ) { // sector erase // clear the 4k/64k block containing the current address to all 0xffs UINT32 base = address * ((m_config.m_bits == 16) ? 2 : 1); if (m_config.m_sector_is_4k) { for (offs_t offs = 0; offs < 4 * 1024; offs++) m_addrspace[0]->write_byte((base & ~0xfff) + offs, 0xff); m_erase_sector = address & ((m_config.m_bits == 16) ? ~0x7ff : ~0xfff); timer_adjust_oneshot( m_timer, ATTOTIME_IN_MSEC( 125 ), 0 ); } else { for (offs_t offs = 0; offs < 64 * 1024; offs++) m_addrspace[0]->write_byte((base & ~0xffff) + offs, 0xff); m_erase_sector = address & ((m_config.m_bits == 16) ? ~0x7fff : ~0xffff); timer_adjust_oneshot( m_timer, ATTOTIME_IN_SEC( 1 ), 0 ); } m_status = 1 << 3; m_flash_mode = FM_ERASEAMD4; } else { logerror( "unexpected %08x=%02x in FM_ERASEAMD3\n", address, data & 0xff ); } break; case FM_BYTEPROGRAM: switch( m_config.m_bits ) { case 8: { m_addrspace[0]->write_byte(address, data); } break; default: logerror( "FM_BYTEPROGRAM not supported when m_bits == %d\n", m_config.m_bits ); break; } m_flash_mode = FM_NORMAL; break; case FM_WRITEPART1: switch( m_config.m_bits ) { case 8: { m_addrspace[0]->write_byte(address, data); } break; case 16: { m_addrspace[0]->write_word(address * 2, data); } break; default: logerror( "FM_WRITEPART1 not supported when m_bits == %d\n", m_config.m_bits ); break; } m_status = 0x80; m_flash_mode = FM_READSTATUS; break; case FM_CLEARPART1: if( ( data & 0xff ) == 0xd0 ) { // clear the 64k block containing the current address to all 0xffs UINT32 base = address * ((m_config.m_bits == 16) ? 2 : 1); for (offs_t offs = 0; offs < 64 * 1024; offs++) m_addrspace[0]->write_byte((base & ~0xffff) + offs, 0xff); m_status = 0x00; m_flash_mode = FM_READSTATUS; timer_adjust_oneshot( m_timer, ATTOTIME_IN_SEC( 1 ), 0 ); break; } else { logerror( "unexpected %02x in FM_CLEARPART1\n", data & 0xff ); } break; case FM_SETMASTER: switch( data & 0xff ) { case 0xf1: m_flash_master_lock = true; break; case 0xd0: m_flash_master_lock = false; break; default: logerror( "unexpected %08x=%02x in FM_SETMASTER:\n", address, data & 0xff ); break; } m_flash_mode = FM_NORMAL; break; } }