/*******************************************************************************
*
* bcm1250TimerBase - return a pointer to the SCD base address register of
* the specified timer
*
* RETURNS: address of a timer's base register, NULL if a bogus timer is requested
*
*/
LOCAL char * bcm1250TimerBase
(
int unit
)
{
switch (unit)
{
case BCM1250_TIMER_0:
return (char *)PHYS_TO_K1(A_SCD_TIMER_BASE(0));
case BCM1250_TIMER_1:
return (char *)PHYS_TO_K1(A_SCD_TIMER_BASE(1));
case BCM1250_TIMER_2:
return (char *)PHYS_TO_K1(A_SCD_TIMER_BASE(2));
case BCM1250_TIMER_3:
return (char *)PHYS_TO_K1(A_SCD_TIMER_BASE(3));
}
return NULL;
}
struct hcfResource r4KTimerDevResources[] = {
{"regBase", HCF_RES_INT, {(void *)0} },
{"minClkRate",HCF_RES_INT, {(void *)SYS_CLK_RATE_MIN} },
{"maxClkRate",HCF_RES_INT, {(void *)SYS_CLK_RATE_MAX} },
/* Fix the cpuClkRate for Loongson 3A by yinwx, 20100518
The COUNTER Reg increase by 2 clk periods, we must use 2 to divide !! */
{"cpuClkRate", HCF_RES_INT/*HCF_RES_ADDR*/, {(void *) (LS3A_FREQ / 2)/*(vxbR4KTimerFrequencyGet)*/} }
};
#define r4TimerDevNum NELEMENTS(r4KTimerDevResources)
#ifdef DRV_TIMER_SB1
struct hcfResource sb1TimerDevResources0 [] = {
#if defined(SB1_CPU_1)
{"regBase", HCF_RES_INT, {(void *) PHYS_TO_K1(A_SCD_TIMER_BASE(1))} },
#else /* default to timer 0 */
{"regBase", HCF_RES_INT, {(void *) PHYS_TO_K1(A_SCD_TIMER_BASE(0))} },
#endif
{"minClkRate",HCF_RES_INT, {(void *)AUX_CLK_RATE_MIN} },
{"maxClkRate",HCF_RES_INT, {(void *) AUX_CLK_RATE_MAX} },
#ifdef _SIMULATOR_
{"cpuClkRate", HCF_RES_INT, {(void *) 10000} }
#else
{"cpuClkRate", HCF_RES_INT, {(void *) 1000000} }
#endif
};
#define sb1TimerDevNum0 NELEMENTS(sb1TimerDevResources0)
#endif /* DRV_TIMER_SB1 */
#if 0
