/**Function*************************************************************
Synopsis [Starts the process of returning values for internal nodes.]
Description [Should be called when pCex is available, before probing
any object for its value using Gia_ManCounterExampleValueLookup().]
SideEffects []
SeeAlso []
***********************************************************************/
void Gia_ManCounterExampleValueStart( Gia_Man_t * pGia, Abc_Cex_t * pCex )
{
Gia_Obj_t * pObj, * pObjRi, * pObjRo;
int Val0, Val1, nObjs, i, k, iBit = 0;
assert( Gia_ManRegNum(pGia) > 0 ); // makes sense only for sequential AIGs
assert( pGia->pData2 == NULL ); // if this fail, there may be a memory leak
// allocate memory to store simulation bits for internal nodes
pGia->pData2 = ABC_CALLOC( unsigned, Abc_BitWordNum( (pCex->iFrame + 1) * Gia_ManObjNum(pGia) ) );
// the register values in the counter-example should be zero
Gia_ManForEachRo( pGia, pObj, k )
assert( Abc_InfoHasBit(pCex->pData, iBit++) == 0 );
// iterate through the timeframes
nObjs = Gia_ManObjNum(pGia);
for ( i = 0; i <= pCex->iFrame; i++ )
{
// no need to set constant-0 node
// set primary inputs according to the counter-example
Gia_ManForEachPi( pGia, pObj, k )
if ( Abc_InfoHasBit(pCex->pData, iBit++) )
Abc_InfoSetBit( (unsigned *)pGia->pData2, nObjs * i + Gia_ObjId(pGia, pObj) );
// compute values for each node
Gia_ManForEachAnd( pGia, pObj, k )
{
Val0 = Abc_InfoHasBit( (unsigned *)pGia->pData2, nObjs * i + Gia_ObjFaninId0p(pGia, pObj) );
Val1 = Abc_InfoHasBit( (unsigned *)pGia->pData2, nObjs * i + Gia_ObjFaninId1p(pGia, pObj) );
if ( (Val0 ^ Gia_ObjFaninC0(pObj)) & (Val1 ^ Gia_ObjFaninC1(pObj)) )
Abc_InfoSetBit( (unsigned *)pGia->pData2, nObjs * i + Gia_ObjId(pGia, pObj) );
}
// derive values for combinational outputs
Gia_ManForEachCo( pGia, pObj, k )
{
Val0 = Abc_InfoHasBit( (unsigned *)pGia->pData2, nObjs * i + Gia_ObjFaninId0p(pGia, pObj) );
if ( Val0 ^ Gia_ObjFaninC0(pObj) )
Abc_InfoSetBit( (unsigned *)pGia->pData2, nObjs * i + Gia_ObjId(pGia, pObj) );
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Cec_ManHandleSpecialCases( Gia_Man_t * p, Cec_ParCec_t * pPars )
{
Gia_Obj_t * pObj1, * pObj2;
Gia_Obj_t * pDri1, * pDri2;
int i;
abctime clk = Abc_Clock();
Gia_ManSetPhase( p );
Gia_ManForEachPo( p, pObj1, i )
{
pObj2 = Gia_ManPo( p, ++i );
// check if they different on all-0 pattern
// (for example, when they have the same driver but complemented)
if ( Gia_ObjPhase(pObj1) != Gia_ObjPhase(pObj2) )
{
Abc_Print( 1, "Networks are NOT EQUIVALENT. Output %d trivially differs (different phase). ", i/2 );
Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
pPars->iOutFail = i/2;
Cec_ManTransformPattern( p, i/2, NULL );
return 0;
}
// get the drivers
pDri1 = Gia_ObjFanin0(pObj1);
pDri2 = Gia_ObjFanin0(pObj2);
// drivers are different PIs
if ( Gia_ObjIsPi(p, pDri1) && Gia_ObjIsPi(p, pDri2) && pDri1 != pDri2 )
{
Abc_Print( 1, "Networks are NOT EQUIVALENT. Output %d trivially differs (different PIs). ", i/2 );
Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
pPars->iOutFail = i/2;
Cec_ManTransformPattern( p, i/2, NULL );
// if their compl attributes are the same - one should be complemented
assert( Gia_ObjFaninC0(pObj1) == Gia_ObjFaninC0(pObj2) );
Abc_InfoSetBit( p->pCexComb->pData, Gia_ObjCioId(pDri1) );
return 0;
}
// one of the drivers is a PI; another is a constant 0
if ( (Gia_ObjIsPi(p, pDri1) && Gia_ObjIsConst0(pDri2)) ||
(Gia_ObjIsPi(p, pDri2) && Gia_ObjIsConst0(pDri1)) )
{
Abc_Print( 1, "Networks are NOT EQUIVALENT. Output %d trivially differs (PI vs. constant). ", i/2 );
Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
pPars->iOutFail = i/2;
Cec_ManTransformPattern( p, i/2, NULL );
// the compl attributes are the same - the PI should be complemented
assert( Gia_ObjFaninC0(pObj1) == Gia_ObjFaninC0(pObj2) );
if ( Gia_ObjIsPi(p, pDri1) )
Abc_InfoSetBit( p->pCexComb->pData, Gia_ObjCioId(pDri1) );
else
Abc_InfoSetBit( p->pCexComb->pData, Gia_ObjCioId(pDri2) );
return 0;
}
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Saves the input pattern with the given number.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Cec_ManTransformPattern( Gia_Man_t * p, int iOut, int * pValues )
{
int i;
assert( p->pCexComb == NULL );
p->pCexComb = Abc_CexAlloc( 0, Gia_ManCiNum(p), 1 );
p->pCexComb->iPo = iOut;
for ( i = 0; i < Gia_ManCiNum(p); i++ )
if ( pValues && pValues[i] )
Abc_InfoSetBit( p->pCexComb->pData, i );
}
/**Function*************************************************************
Synopsis [Derive a new counter-example.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Cex_t * Saig_ManCexRemap( Aig_Man_t * p, Aig_Man_t * pAbs, Abc_Cex_t * pCexAbs )
{
Abc_Cex_t * pCex;
Aig_Obj_t * pObj;
int i, f;
if ( !Saig_ManVerifyCex( pAbs, pCexAbs ) )
printf( "Saig_ManCexRemap(): The initial counter-example is invalid.\n" );
// else
// printf( "Saig_ManCexRemap(): The initial counter-example is correct.\n" );
// start the counter-example
pCex = Abc_CexAlloc( Aig_ManRegNum(p), Saig_ManPiNum(p), pCexAbs->iFrame+1 );
pCex->iFrame = pCexAbs->iFrame;
pCex->iPo = pCexAbs->iPo;
// copy the bit data
for ( f = 0; f <= pCexAbs->iFrame; f++ )
{
Saig_ManForEachPi( pAbs, pObj, i )
{
if ( i == Saig_ManPiNum(p) )
break;
if ( Abc_InfoHasBit( pCexAbs->pData, pCexAbs->nRegs + pCexAbs->nPis * f + i ) )
Abc_InfoSetBit( pCex->pData, pCex->nRegs + pCex->nPis * f + i );
}
}
// verify the counter example
if ( !Saig_ManVerifyCex( p, pCex ) )
{
printf( "Saig_ManCexRemap(): Counter-example is invalid.\n" );
Abc_CexFree( pCex );
pCex = NULL;
}
else
{
Abc_Print( 1, "Counter-example verification is successful.\n" );
Abc_Print( 1, "Output %d of miter \"%s\" was asserted in frame %d. \n", pCex->iPo, p->pName, pCex->iFrame );
}
return pCex;
}
/**Function*************************************************************
Synopsis [Run the SAT solver on the unrolled instance.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void * Inter_ManGetCounterExample( Aig_Man_t * pAig, int nFrames, int fVerbose )
{
int nConfLimit = 1000000;
Abc_Cex_t * pCtrex = NULL;
Aig_Man_t * pFrames;
sat_solver * pSat;
Cnf_Dat_t * pCnf;
int status;
clock_t clk = clock();
Vec_Int_t * vCiIds;
// create timeframes
assert( Saig_ManPoNum(pAig) == 1 );
pFrames = Inter_ManFramesBmc( pAig, nFrames );
// derive CNF
pCnf = Cnf_Derive( pFrames, 0 );
Cnf_DataTranformPolarity( pCnf, 0 );
vCiIds = Cnf_DataCollectPiSatNums( pCnf, pFrames );
Aig_ManStop( pFrames );
// convert into SAT solver
pSat = (sat_solver *)Cnf_DataWriteIntoSolver( pCnf, 1, 0 );
Cnf_DataFree( pCnf );
if ( pSat == NULL )
{
printf( "Counter-example generation in command \"int\" has failed.\n" );
printf( "Use command \"bmc2\" to produce a valid counter-example.\n" );
Vec_IntFree( vCiIds );
return NULL;
}
// simplify the problem
status = sat_solver_simplify(pSat);
if ( status == 0 )
{
Vec_IntFree( vCiIds );
sat_solver_delete( pSat );
return NULL;
}
// solve the miter
status = sat_solver_solve( pSat, NULL, NULL, (ABC_INT64_T)nConfLimit, (ABC_INT64_T)0, (ABC_INT64_T)0, (ABC_INT64_T)0 );
// if the problem is SAT, get the counterexample
if ( status == l_True )
{
int i, * pModel = Sat_SolverGetModel( pSat, vCiIds->pArray, vCiIds->nSize );
pCtrex = Abc_CexAlloc( Saig_ManRegNum(pAig), Saig_ManPiNum(pAig), nFrames );
pCtrex->iFrame = nFrames - 1;
pCtrex->iPo = 0;
for ( i = 0; i < Vec_IntSize(vCiIds); i++ )
if ( pModel[i] )
Abc_InfoSetBit( pCtrex->pData, Saig_ManRegNum(pAig) + i );
ABC_FREE( pModel );
}
// free the sat_solver
sat_solver_delete( pSat );
Vec_IntFree( vCiIds );
// verify counter-example
status = Saig_ManVerifyCex( pAig, pCtrex );
if ( status == 0 )
printf( "Inter_ManGetCounterExample(): Counter-example verification has FAILED.\n" );
// report the results
if ( fVerbose )
{
ABC_PRT( "Total ctrex generation time", clock() - clk );
}
return pCtrex;
}