/**Function*************************************************************
Synopsis [Cycles the circuit to create a new initial state.]
Description [Simulates the circuit with random input for the given
number of timeframes to get a better initial state.]
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkCycleInitState( Abc_Ntk_t * pNtk, int nFrames, int fVerbose )
{
Abc_Obj_t * pObj;
int i, f;
assert( Abc_NtkIsStrash(pNtk) );
srand( 0x12341234 );
// initialize the values
Abc_ObjSetXsim( Abc_AigConst1(pNtk), XVS1 );
Abc_NtkForEachPi( pNtk, pObj, i )
Abc_ObjSetXsim( pObj, Abc_XsimRand2() );
Abc_NtkForEachLatch( pNtk, pObj, i )
Abc_ObjSetXsim( Abc_ObjFanout0(pObj), Abc_LatchIsInit1(pObj)? XVS1 : XVS0 );
// simulate for the given number of timeframes
for ( f = 0; f < nFrames; f++ )
{
Abc_AigForEachAnd( pNtk, pObj, i )
Abc_ObjSetXsim( pObj, Abc_XsimAnd(Abc_ObjGetXsimFanin0(pObj), Abc_ObjGetXsimFanin1(pObj)) );
Abc_NtkForEachCo( pNtk, pObj, i )
Abc_ObjSetXsim( pObj, Abc_ObjGetXsimFanin0(pObj) );
// assign input values
Abc_NtkForEachPi( pNtk, pObj, i )
Abc_ObjSetXsim( pObj, Abc_XsimRand2() );
// transfer the latch values
Abc_NtkForEachLatch( pNtk, pObj, i )
Abc_ObjSetXsim( Abc_ObjFanout0(pObj), Abc_ObjGetXsim(Abc_ObjFanin0(pObj)) );
}
// set the final values
Abc_NtkForEachLatch( pNtk, pObj, i )
pObj->pData = (void *)Abc_ObjGetXsim(Abc_ObjFanout0(pObj));
}
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Bus_ManReadInOutLoads( Bus_Man_t * p )
{
if ( Abc_FrameReadMaxLoad() )
{
Abc_Obj_t * pObj; int i;
float MaxLoad = Abc_FrameReadMaxLoad();
Abc_NtkForEachCo( p->pNtk, pObj, i )
Bus_SclObjSetCin( pObj, MaxLoad );
// printf( "Default output load is specified (%f ff).\n", MaxLoad );
}
if ( Abc_FrameReadDrivingCell() )
{
int iCell = Abc_SclCellFind( p->pLib, Abc_FrameReadDrivingCell() );
if ( iCell == -1 )
printf( "Cannot find the default PI driving cell (%s) in the library.\n", Abc_FrameReadDrivingCell() );
else
{
// printf( "Default PI driving cell is specified (%s).\n", Abc_FrameReadDrivingCell() );
p->pPiDrive = SC_LibCell( p->pLib, iCell );
assert( p->pPiDrive != NULL );
assert( p->pPiDrive->n_inputs == 1 );
// printf( "Default input driving cell is specified (%s).\n", p->pPiDrive->pName );
}
}
}
/**Function*************************************************************
Synopsis [Performs X-valued simulation of the sequential network.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkXValueSimulate( Abc_Ntk_t * pNtk, int nFrames, int fInputs, int fVerbose )
{
Abc_Obj_t * pObj;
int i, f;
assert( Abc_NtkIsStrash(pNtk) );
srand( 0x12341234 );
// start simulation
Abc_ObjSetXsim( Abc_AigConst1(pNtk), XVS1 );
if ( fInputs )
{
Abc_NtkForEachPi( pNtk, pObj, i )
Abc_ObjSetXsim( pObj, XVSX );
Abc_NtkForEachLatch( pNtk, pObj, i )
Abc_ObjSetXsim( Abc_ObjFanout0(pObj), Abc_LatchInit(pObj) );
}
else
{
Abc_NtkForEachPi( pNtk, pObj, i )
Abc_ObjSetXsim( pObj, Abc_XsimRand2() );
Abc_NtkForEachLatch( pNtk, pObj, i )
Abc_ObjSetXsim( Abc_ObjFanout0(pObj), XVSX );
}
// simulate and print the result
fprintf( stdout, "Frame : Inputs : Latches : Outputs\n" );
for ( f = 0; f < nFrames; f++ )
{
Abc_AigForEachAnd( pNtk, pObj, i )
Abc_ObjSetXsim( pObj, Abc_XsimAnd(Abc_ObjGetXsimFanin0(pObj), Abc_ObjGetXsimFanin1(pObj)) );
Abc_NtkForEachCo( pNtk, pObj, i )
Abc_ObjSetXsim( pObj, Abc_ObjGetXsimFanin0(pObj) );
// print out
fprintf( stdout, "%2d : ", f );
Abc_NtkForEachPi( pNtk, pObj, i )
Abc_XsimPrint( stdout, Abc_ObjGetXsim(pObj) );
fprintf( stdout, " : " );
Abc_NtkForEachLatch( pNtk, pObj, i )
Abc_XsimPrint( stdout, Abc_ObjGetXsim(Abc_ObjFanout0(pObj)) );
fprintf( stdout, " : " );
Abc_NtkForEachPo( pNtk, pObj, i )
Abc_XsimPrint( stdout, Abc_ObjGetXsim(pObj) );
fprintf( stdout, "\n" );
// assign input values
if ( fInputs )
Abc_NtkForEachPi( pNtk, pObj, i )
Abc_ObjSetXsim( pObj, XVSX );
else
Abc_NtkForEachPi( pNtk, pObj, i )
Abc_ObjSetXsim( pObj, Abc_XsimRand2() );
// transfer the latch values
Abc_NtkForEachLatch( pNtk, pObj, i )
Abc_ObjSetXsim( Abc_ObjFanout0(pObj), Abc_ObjGetXsim(Abc_ObjFanin0(pObj)) );
}
}
/**Function*************************************************************
Synopsis [Derives GIA manager using special pins to denote box boundaries.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Gia_Man_t * Abc_NtkTestPinDeriveGia( Abc_Ntk_t * pNtk, int fWhiteBoxOnly, int fVerbose )
{
Gia_Man_t * pTemp;
Gia_Man_t * pGia = NULL;
Vec_Ptr_t * vNodes;
Abc_Obj_t * pObj, * pFanin;
int i, k, iPinLit = 0;
// prepare logic network
assert( Abc_NtkIsLogic(pNtk) );
Abc_NtkToAig( pNtk );
// construct GIA
Abc_NtkFillTemp( pNtk );
pGia = Gia_ManStart( Abc_NtkObjNumMax(pNtk) );
Gia_ManHashAlloc( pGia );
// create primary inputs
Abc_NtkForEachCi( pNtk, pObj, i )
pObj->iTemp = Gia_ManAppendCi(pGia);
// create internal nodes in a topologic order from white boxes
vNodes = Abc_NtkDfs( pNtk, 0 );
Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pObj, i )
{
// input side
if ( !fWhiteBoxOnly || Abc_NodeIsWhiteBox(pObj) )
{
// create special pintype for this node
iPinLit = Gia_ManAppendPinType( pGia, 1 );
// create input pins
Abc_ObjForEachFanin( pObj, pFanin, k )
pFanin->iTemp = Gia_ManAppendAnd( pGia, pFanin->iTemp, iPinLit );
}
// perform GIA construction
pObj->iTemp = Abc_NtkTestTimNodeStrash( pGia, pObj );
// output side
if ( !fWhiteBoxOnly || Abc_NodeIsWhiteBox(pObj) )
{
// create special pintype for this node
iPinLit = Gia_ManAppendPinType( pGia, 1 );
// create output pins
pObj->iTemp = Gia_ManAppendAnd( pGia, pObj->iTemp, iPinLit );
}
}
Vec_PtrFree( vNodes );
// create primary outputs
Abc_NtkForEachCo( pNtk, pObj, i )
pObj->iTemp = Gia_ManAppendCo( pGia, Abc_ObjFanin0(pObj)->iTemp );
// finalize GIA
Gia_ManHashStop( pGia );
Gia_ManSetRegNum( pGia, 0 );
// clean up GIA
pGia = Gia_ManCleanup( pTemp = pGia );
Gia_ManStop( pTemp );
return pGia;
}
/**Function*************************************************************
Synopsis [Tranfers names to the old network.]
Description [Assumes that the new nodes are attached using pObj->pCopy.]
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkTrasferNames( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkNew )
{
Abc_Obj_t * pObj;
int i;
assert( Abc_NtkPiNum(pNtk) == Abc_NtkPiNum(pNtkNew) );
assert( Abc_NtkPoNum(pNtk) == Abc_NtkPoNum(pNtkNew) );
assert( Abc_NtkBoxNum(pNtk) == Abc_NtkBoxNum(pNtkNew) );
assert( Nm_ManNumEntries(pNtk->pManName) > 0 );
assert( Nm_ManNumEntries(pNtkNew->pManName) == 0 );
// copy the CI/CO/box names
Abc_NtkForEachCi( pNtk, pObj, i )
Abc_ObjAssignName( pObj->pCopy, Abc_ObjName(Abc_ObjFanout0Ntk(pObj)), NULL );
Abc_NtkForEachCo( pNtk, pObj, i )
Abc_ObjAssignName( pObj->pCopy, Abc_ObjName(Abc_ObjFanin0Ntk(pObj)), NULL );
Abc_NtkForEachBox( pNtk, pObj, i )
Abc_ObjAssignName( pObj->pCopy, Abc_ObjName(pObj), NULL );
}
/**Function*************************************************************
Synopsis [Converts the network from the AIG manager into ABC.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Hop_Man_t * Abc_NtkToMini( Abc_Ntk_t * pNtk )
{
Hop_Man_t * pMan;
Abc_Obj_t * pObj;
int i;
// create the manager
pMan = Hop_ManStart();
// transfer the pointers to the basic nodes
Abc_AigConst1(pNtk)->pCopy = (Abc_Obj_t *)Hop_ManConst1(pMan);
Abc_NtkForEachCi( pNtk, pObj, i )
pObj->pCopy = (Abc_Obj_t *)Hop_ObjCreatePi(pMan);
// perform the conversion of the internal nodes (assumes DFS ordering)
Abc_NtkForEachNode( pNtk, pObj, i )
pObj->pCopy = (Abc_Obj_t *)Hop_And( pMan, (Hop_Obj_t *)Abc_ObjChild0Copy(pObj), (Hop_Obj_t *)Abc_ObjChild1Copy(pObj) );
// create the POs
Abc_NtkForEachCo( pNtk, pObj, i )
Hop_ObjCreatePo( pMan, (Hop_Obj_t *)Abc_ObjChild0Copy(pObj) );
Hop_ManCleanup( pMan );
return pMan;
}
Vec_Ptr_t * Abc_NtkTestTimCollectCone( Abc_Ntk_t * pNtk, Abc_Obj_t * pObj )
{
Vec_Ptr_t * vCone = Vec_PtrAlloc( 1000 );
if ( pObj != NULL )
{
// collect for one node
assert( Abc_ObjIsNode(pObj) );
assert( !Abc_NodeIsTravIdCurrent( pObj ) );
Abc_NtkTestTimCollectCone_rec( pObj, vCone );
// remove the node because it is a white box
Vec_PtrPop( vCone );
}
else
{
// collect for all COs
Abc_Obj_t * pObj;
int i;
Abc_NtkForEachCo( pNtk, pObj, i )
Abc_NtkTestTimCollectCone_rec( Abc_ObjFanin0(pObj), vCone );
}
return vCone;
}
ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis []
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Vec_Ptr_t * Abc_NtkAssignIDs( Abc_Ntk_t * pNtk )
{
Vec_Ptr_t * vNodes;
Abc_Obj_t * pObj;
int i;
vNodes = Abc_NtkDfs( pNtk, 0 );
Abc_NtkCleanCopy( pNtk );
Abc_NtkForEachCi( pNtk, pObj, i )
pObj->iTemp = i;
Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pObj, i )
pObj->iTemp = Abc_NtkCiNum(pNtk) + i;
Abc_NtkForEachCo( pNtk, pObj, i )
pObj->iTemp = Abc_NtkCiNum(pNtk) + Vec_PtrSize(vNodes) + i;
return vNodes;
}
Mini_Aig_t * Abc_NtkToMiniAig( Abc_Ntk_t * pNtk )
{
Mini_Aig_t * p;
Abc_Obj_t * pObj;
int i;
assert( Abc_NtkIsStrash(pNtk) );
// create the manager
p = Mini_AigStart();
// create mapping from MiniAIG into ABC objects
Abc_NtkCleanCopy( pNtk );
Abc_AigConst1(pNtk)->iTemp = Mini_AigLitConst1();
// create primary inputs
Abc_NtkForEachCi( pNtk, pObj, i )
pObj->iTemp = Mini_AigCreatePi(p);
// create internal nodes
Abc_NtkForEachNode( pNtk, pObj, i )
pObj->iTemp = Mini_AigAnd( p, Abc_NodeFanin0Copy2(pObj), Abc_NodeFanin1Copy2(pObj) );
// create primary outputs
Abc_NtkForEachCo( pNtk, pObj, i )
pObj->iTemp = Mini_AigCreatePo( p, Abc_NodeFanin0Copy2(pObj) );
// set registers
Mini_AigSetRegNum( p, Abc_NtkLatchNum(pNtk) );
return p;
}
/**Function*************************************************************
Synopsis [Sets the final nodes to point to the original nodes.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkTransferPointers( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkAig )
{
Abc_Obj_t * pObj;
Ivy_Obj_t * pObjIvy, * pObjFraig;
int i;
pObj = Abc_AigConst1(pNtk);
pObj->pCopy = Abc_AigConst1(pNtkAig);
Abc_NtkForEachCi( pNtk, pObj, i )
pObj->pCopy = Abc_NtkCi(pNtkAig, i);
Abc_NtkForEachCo( pNtk, pObj, i )
pObj->pCopy = Abc_NtkCo(pNtkAig, i);
Abc_NtkForEachLatch( pNtk, pObj, i )
pObj->pCopy = Abc_NtkBox(pNtkAig, i);
Abc_NtkForEachNode( pNtk, pObj, i )
{
pObjIvy = (Ivy_Obj_t *)pObj->pCopy;
if ( pObjIvy == NULL )
continue;
pObjFraig = Ivy_ObjEquiv( pObjIvy );
if ( pObjFraig == NULL )
continue;
pObj->pCopy = Abc_EdgeToNode( pNtkAig, Ivy_Regular(pObjFraig)->TravId );
pObj->pCopy = Abc_ObjNotCond( pObj->pCopy, Ivy_IsComplement(pObjFraig) );
}
ABC_NAMESPACE_IMPL_START
// For description of Binary BLIF format, refer to "abc/src/aig/bbl/bblif.h"
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Fnction*************************************************************
Synopsis [Construct manager from the ABC network.]
Description [In the ABC network each object has a unique integer ID.
This ID is used when we construct objects of the BBLIF manager
corresponding to each object of the ABC network. The objects can be
added to the manager in any order (although below they are added in the
topological order), but by the time fanin/fanout connections are created,
corresponding objects are already constructed. In the end the checking
procedure is called.]
SideEffects []
SeeAlso []
***********************************************************************/
Bbl_Man_t * Bbl_ManFromAbc( Abc_Ntk_t * pNtk )
{
Bbl_Man_t * p;
Vec_Ptr_t * vNodes;
Abc_Obj_t * pObj, * pFanin;
int i, k;
assert( Abc_NtkIsSopLogic(pNtk) );
// start the data manager
p = Bbl_ManStart( Abc_NtkName(pNtk) );
// collect internal nodes to be added
vNodes = Abc_NtkDfs( pNtk, 0 );
// create combinational inputs
Abc_NtkForEachCi( pNtk, pObj, i )
Bbl_ManCreateObject( p, BBL_OBJ_CI, Abc_ObjId(pObj), 0, NULL );
// create internal nodes
Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pObj, i )
Bbl_ManCreateObject( p, BBL_OBJ_NODE, Abc_ObjId(pObj), Abc_ObjFaninNum(pObj), (char *)pObj->pData );
// create combinational outputs
Abc_NtkForEachCo( pNtk, pObj, i )
Bbl_ManCreateObject( p, BBL_OBJ_CO, Abc_ObjId(pObj), 1, NULL );
// create fanin/fanout connections for internal nodes
Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pObj, i )
Abc_ObjForEachFanin( pObj, pFanin, k )
Bbl_ManAddFanin( p, Abc_ObjId(pObj), Abc_ObjId(pFanin) );
// create fanin/fanout connections for combinational outputs
Abc_NtkForEachCo( pNtk, pObj, i )
Abc_ObjForEachFanin( pObj, pFanin, k )
Bbl_ManAddFanin( p, Abc_ObjId(pObj), Abc_ObjId(pFanin) );
Vec_PtrFree( vNodes );
// sanity check
Bbl_ManCheck( p );
return p;
}
