ABC_NAMESPACE_IMPL_START
////////////////////////////////////////////////////////////////////////
/// DECLARATIONS ///
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
/// FUNCTION DEFINITIONS ///
////////////////////////////////////////////////////////////////////////
/**Function*************************************************************
Synopsis [Checks if latches form self-loop.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_NtkLatchIsSelfFeed_rec( Abc_Obj_t * pLatch, Abc_Obj_t * pLatchRoot )
{
Abc_Obj_t * pFanin;
assert( Abc_ObjIsLatch(pLatch) );
if ( pLatch == pLatchRoot )
return 1;
pFanin = Abc_ObjFanin0(Abc_ObjFanin0(pLatch));
if ( !Abc_ObjIsBo(pFanin) || !Abc_ObjIsLatch(Abc_ObjFanin0(pFanin)) )
return 0;
return Abc_NtkLatchIsSelfFeed_rec( Abc_ObjFanin0(pFanin), pLatch );
}
/**Function*************************************************************
Synopsis [Checks if latches form self-loop.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
int Abc_NtkLatchIsSelfFeed( Abc_Obj_t * pLatch )
{
Abc_Obj_t * pFanin;
assert( Abc_ObjIsLatch(pLatch) );
pFanin = Abc_ObjFanin0(Abc_ObjFanin0(pLatch));
if ( !Abc_ObjIsBo(pFanin) || !Abc_ObjIsLatch(Abc_ObjFanin0(pFanin)) )
return 0;
return Abc_NtkLatchIsSelfFeed_rec( Abc_ObjFanin0(pFanin), pLatch );
}
/**Function*************************************************************
Synopsis [Tranfers names to the old network.]
Description [Assumes that the new nodes are attached using pObj->pCopy.]
SideEffects []
SeeAlso []
***********************************************************************/
void Abc_NtkTrasferNamesNoLatches( Abc_Ntk_t * pNtk, Abc_Ntk_t * pNtkNew )
{
Abc_Obj_t * pObj;
int i;
assert( Abc_NtkPiNum(pNtk) == Abc_NtkPiNum(pNtkNew) );
assert( Abc_NtkPoNum(pNtk) == Abc_NtkPoNum(pNtkNew) );
assert( Nm_ManNumEntries(pNtk->pManName) > 0 );
assert( Nm_ManNumEntries(pNtkNew->pManName) == 0 );
// copy the CI/CO/box name and skip latches and theirs inputs/outputs
Abc_NtkForEachCi( pNtk, pObj, i )
if ( Abc_ObjFaninNum(pObj) == 0 || !Abc_ObjIsLatch(Abc_ObjFanin0(pObj)) )
Abc_ObjAssignName( pObj->pCopy, Abc_ObjName(Abc_ObjFanout0Ntk(pObj)), NULL );
Abc_NtkForEachCo( pNtk, pObj, i )
if ( Abc_ObjFanoutNum(pObj) == 0 || !Abc_ObjIsLatch(Abc_ObjFanout0(pObj)) )
Abc_ObjAssignName( pObj->pCopy, Abc_ObjName(Abc_ObjFanin0Ntk(pObj)), NULL );
Abc_NtkForEachBox( pNtk, pObj, i )
if ( !Abc_ObjIsLatch(pObj) )
Abc_ObjAssignName( pObj->pCopy, Abc_ObjName(pObj), NULL );
}
// generate edges
Vec_PtrForEachEntry( vNodes, pNode, i )
{
if ( Abc_ObjIsLatch(pNode) )
continue;
Abc_ObjForEachFanin( pNode, pFanin, k )
{
if ( Abc_ObjIsLatch(pFanin) )
continue;
fCompl = 0;
if ( Abc_NtkIsStrash(pNtk) )
fCompl = Abc_ObjFaninC(pNode, k);
// generate the edge from this node to the next
fprintf( pFile, "Node%d", pNode->Id );
fprintf( pFile, " -> " );
fprintf( pFile, "Node%d", pFanin->Id );
fprintf( pFile, " [style = %s", fCompl? "dotted" : "bold" );
// fprintf( pFile, ", label = \"%c\"", 'a' + k );
fprintf( pFile, "]" );
fprintf( pFile, ";\n" );
}
}
/**Function*************************************************************
Synopsis [Prints initial state information.]
Description [Prints distribution of 0,1,and X initial states.]
SideEffects []
SeeAlso []
***********************************************************************/
static inline int
Abc_FlowRetime_ObjFirstNonLatchBox( Abc_Obj_t * pOrigObj, Abc_Obj_t ** pResult ) {
int lag = 0;
Abc_Ntk_t *pNtk;
*pResult = pOrigObj;
pNtk = Abc_ObjNtk( pOrigObj );
Abc_NtkIncrementTravId( pNtk );
while( Abc_ObjIsBo(*pResult) || Abc_ObjIsLatch(*pResult) || Abc_ObjIsBi(*pResult) ) {
assert(Abc_ObjFaninNum(*pResult));
*pResult = Abc_ObjFanin0(*pResult);
if (Abc_NodeIsTravIdCurrent(*pResult))
return -1;
Abc_NodeSetTravIdCurrent(*pResult);
if (Abc_ObjIsLatch(*pResult)) ++lag;
}
return lag;
}
/**Function*************************************************************
Synopsis [Converts combinational AIG with latches into sequential AIG.]
Description [The const/PI/PO nodes are duplicated. The internal
nodes are duplicated in the topological order. The dangling nodes
are not duplicated. The choice nodes are duplicated.]
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkAigToSeq( Abc_Ntk_t * pNtk )
{
Abc_Ntk_t * pNtkNew;
Abc_Obj_t * pObj, * pFaninNew;
Vec_Int_t * vInitValues;
Abc_InitType_t Init;
int i, k, RetValue;
// make sure it is an AIG without self-feeding latches
assert( Abc_NtkIsStrash(pNtk) );
assert( Abc_NtkIsDfsOrdered(pNtk) );
if ( RetValue = Abc_NtkRemoveSelfFeedLatches(pNtk) )
printf( "Modified %d self-feeding latches. The result will not verify.\n", RetValue );
assert( Abc_NtkCountSelfFeedLatches(pNtk) == 0 );
// start the network
pNtkNew = Abc_NtkAlloc( ABC_NTK_SEQ, ABC_FUNC_AIG, 1 );
// duplicate the name and the spec
pNtkNew->pName = Extra_UtilStrsav(pNtk->pName);
pNtkNew->pSpec = Extra_UtilStrsav(pNtk->pSpec);
// map the constant nodes
Abc_NtkCleanCopy( pNtk );
Abc_AigConst1(pNtk)->pCopy = Abc_AigConst1(pNtkNew);
// copy all objects, except the latches and constant
Vec_PtrFill( pNtkNew->vObjs, Abc_NtkObjNumMax(pNtk), NULL );
Vec_PtrWriteEntry( pNtkNew->vObjs, 0, Abc_AigConst1(pNtk)->pCopy );
Abc_NtkForEachObj( pNtk, pObj, i )
{
if ( i == 0 || Abc_ObjIsLatch(pObj) )
continue;
pObj->pCopy = Abc_ObjAlloc( pNtkNew, pObj->Type );
pObj->pCopy->Id = pObj->Id; // the ID is the same for both
pObj->pCopy->fPhase = pObj->fPhase; // used to work with choices
pObj->pCopy->Level = pObj->Level; // used for upper bound on clock cycle
Vec_PtrWriteEntry( pNtkNew->vObjs, pObj->pCopy->Id, pObj->pCopy );
pNtkNew->nObjs++;
}
pNtkNew->nObjCounts[ABC_OBJ_NODE] = pNtk->nObjCounts[ABC_OBJ_NODE];
// create PI/PO and their names
Abc_NtkForEachPi( pNtk, pObj, i )
{
Vec_PtrPush( pNtkNew->vPis, pObj->pCopy );
Vec_PtrPush( pNtkNew->vCis, pObj->pCopy );
Abc_ObjAssignName( pObj->pCopy, Abc_ObjName(pObj), NULL );
}
/**Function*************************************************************
Synopsis [Reads initial state in BENCH format.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
void Io_ReadBenchInit( Abc_Ntk_t * pNtk, char * pFileName )
{
char pBuffer[1000];
FILE * pFile;
char * pToken;
Abc_Obj_t * pObj;
int Num;
pFile = fopen( pFileName, "r" );
if ( pFile == NULL )
{
printf( "Io_ReadBenchInit(): Failed to open file \"%s\".\n", pFileName );
return;
}
while ( fgets( pBuffer, 999, pFile ) )
{
pToken = strtok( pBuffer, " \n\t\r" );
// find the latch output
Num = Nm_ManFindIdByName( pNtk->pManName, pToken, ABC_OBJ_BO );
if ( Num < 0 )
{
printf( "Io_ReadBenchInit(): Cannot find register with output %s.\n", pToken );
continue;
}
pObj = Abc_ObjFanin0( Abc_NtkObj( pNtk, Num ) );
if ( !Abc_ObjIsLatch(pObj) )
{
printf( "Io_ReadBenchInit(): The signal is not a register output %s.\n", pToken );
continue;
}
// assign the new init state
pToken = strtok( NULL, " \n\t\r" );
if ( pToken[0] == '0' )
Abc_LatchSetInit0( pObj );
else if ( pToken[0] == '1' )
Abc_LatchSetInit1( pObj );
else if ( pToken[0] == '2' )
Abc_LatchSetInitDc( pObj );
else
{
printf( "Io_ReadBenchInit(): The signal %s has unknown initial value (%s).\n",
Abc_ObjName(Abc_ObjFanout0(pObj)), pToken );
continue;
}
}
fclose( pFile );
}
/**Function*************************************************************
Synopsis [Starts a new network using existing network as a model.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Abc_Ntk_t * Abc_NtkStartFromNoLatches( Abc_Ntk_t * pNtk, Abc_NtkType_t Type, Abc_NtkFunc_t Func )
{
Abc_Ntk_t * pNtkNew;
Abc_Obj_t * pObj;
int i;
if ( pNtk == NULL )
return NULL;
assert( Type != ABC_NTK_NETLIST );
// start the network
pNtkNew = Abc_NtkAlloc( Type, Func, 1 );
// duplicate the name and the spec
pNtkNew->pName = Extra_UtilStrsav(pNtk->pName);
pNtkNew->pSpec = Extra_UtilStrsav(pNtk->pSpec);
// clean the node copy fields
Abc_NtkCleanCopy( pNtk );
// map the constant nodes
if ( Abc_NtkIsStrash(pNtk) && Abc_NtkIsStrash(pNtkNew) )
Abc_AigConst1(pNtk)->pCopy = Abc_AigConst1(pNtkNew);
// clone CIs/CIs/boxes
Abc_NtkForEachPi( pNtk, pObj, i )
Abc_NtkDupObj( pNtkNew, pObj, 1 );
Abc_NtkForEachPo( pNtk, pObj, i )
Abc_NtkDupObj( pNtkNew, pObj, 1 );
Abc_NtkForEachAssert( pNtk, pObj, i )
Abc_NtkDupObj( pNtkNew, pObj, 1 );
Abc_NtkForEachBox( pNtk, pObj, i )
{
if ( Abc_ObjIsLatch(pObj) )
continue;
Abc_NtkDupBox(pNtkNew, pObj, 1);
}
// transfer the names
// Abc_NtkTrasferNamesNoLatches( pNtk, pNtkNew );
Abc_ManTimeDup( pNtk, pNtkNew );
// check that the CI/CO/latches are copied correctly
assert( Abc_NtkPiNum(pNtk) == Abc_NtkPiNum(pNtkNew) );
assert( Abc_NtkPoNum(pNtk) == Abc_NtkPoNum(pNtkNew) );
return pNtkNew;
}
Abc_NtkForEachObj( pNtk, pObj, i )
{
// skip constants, PIs, and latches
if ( Abc_ObjFaninNum(pObj) == 0 || Abc_ObjIsLatch(pObj) )
continue;
// process the first fanin
Vec_IntClear( vInitValues );
pFaninNew = Abc_NodeAigToSeq( pObj->pCopy, pObj, 0, vInitValues );
Abc_ObjAddFanin( pObj->pCopy, pFaninNew );
// store the initial values
Vec_IntForEachEntry( vInitValues, Init, k )
Seq_NodeInsertFirst( pObj->pCopy, 0, Init );
// skip single-input nodes
if ( Abc_ObjFaninNum(pObj) == 1 )
continue;
// process the second fanin
Vec_IntClear( vInitValues );
pFaninNew = Abc_NodeAigToSeq( pObj->pCopy, pObj, 1, vInitValues );
Abc_ObjAddFanin( pObj->pCopy, pFaninNew );
// store the initial values
Vec_IntForEachEntry( vInitValues, Init, k )
Seq_NodeInsertFirst( pObj->pCopy, 1, Init );
}
/**Function*************************************************************
Synopsis [Load the network into manager.]
Description []
SideEffects []
SeeAlso []
***********************************************************************/
Map_Man_t * Abc_NtkToMap( Abc_Ntk_t * pNtk, double DelayTarget, int fRecovery, float * pSwitching, int fVerbose )
{
Map_Man_t * pMan;
Map_Node_t * pNodeMap;
Vec_Ptr_t * vNodes;
Abc_Obj_t * pNode, * pFanin, * pPrev;
int i;
assert( Abc_NtkIsStrash(pNtk) );
// start the mapping manager and set its parameters
pMan = Map_ManCreate( Abc_NtkPiNum(pNtk) + Abc_NtkLatchNum(pNtk) - pNtk->nBarBufs, Abc_NtkPoNum(pNtk) + Abc_NtkLatchNum(pNtk) - pNtk->nBarBufs, fVerbose );
if ( pMan == NULL )
return NULL;
Map_ManSetAreaRecovery( pMan, fRecovery );
Map_ManSetOutputNames( pMan, Abc_NtkCollectCioNames(pNtk, 1) );
Map_ManSetDelayTarget( pMan, (float)DelayTarget );
Map_ManSetInputArrivals( pMan, Abc_NtkMapCopyCiArrival(pNtk, Abc_NtkGetCiArrivalTimes(pNtk)) );
Map_ManSetOutputRequireds( pMan, Abc_NtkMapCopyCoRequired(pNtk, Abc_NtkGetCoRequiredTimes(pNtk)) );
// create PIs and remember them in the old nodes
Abc_NtkCleanCopy( pNtk );
Abc_AigConst1(pNtk)->pCopy = (Abc_Obj_t *)Map_ManReadConst1(pMan);
Abc_NtkForEachCi( pNtk, pNode, i )
{
if ( i == Abc_NtkCiNum(pNtk) - pNtk->nBarBufs )
break;
pNodeMap = Map_ManReadInputs(pMan)[i];
pNode->pCopy = (Abc_Obj_t *)pNodeMap;
if ( pSwitching )
Map_NodeSetSwitching( pNodeMap, pSwitching[pNode->Id] );
}
// load the AIG into the mapper
vNodes = Abc_AigDfsMap( pNtk );
Vec_PtrForEachEntry( Abc_Obj_t *, vNodes, pNode, i )
{
if ( Abc_ObjIsLatch(pNode) )
{
pFanin = Abc_ObjFanin0(pNode);
pNodeMap = Map_NodeBuf( pMan, Map_NotCond( Abc_ObjFanin0(pFanin)->pCopy, (int)Abc_ObjFaninC0(pFanin) ) );
Abc_ObjFanout0(pNode)->pCopy = (Abc_Obj_t *)pNodeMap;
continue;
}
assert( Abc_ObjIsNode(pNode) );
// add the node to the mapper
pNodeMap = Map_NodeAnd( pMan,
Map_NotCond( Abc_ObjFanin0(pNode)->pCopy, (int)Abc_ObjFaninC0(pNode) ),
Map_NotCond( Abc_ObjFanin1(pNode)->pCopy, (int)Abc_ObjFaninC1(pNode) ) );
assert( pNode->pCopy == NULL );
// remember the node
pNode->pCopy = (Abc_Obj_t *)pNodeMap;
if ( pSwitching )
Map_NodeSetSwitching( pNodeMap, pSwitching[pNode->Id] );
// set up the choice node
if ( Abc_AigNodeIsChoice( pNode ) )
for ( pPrev = pNode, pFanin = (Abc_Obj_t *)pNode->pData; pFanin; pPrev = pFanin, pFanin = (Abc_Obj_t *)pFanin->pData )
{
Map_NodeSetNextE( (Map_Node_t *)pPrev->pCopy, (Map_Node_t *)pFanin->pCopy );
Map_NodeSetRepr( (Map_Node_t *)pFanin->pCopy, (Map_Node_t *)pNode->pCopy );
}
}
assert( Map_ManReadBufNum(pMan) == pNtk->nBarBufs );
Vec_PtrFree( vNodes );
// set the primary outputs in the required phase
Abc_NtkForEachCo( pNtk, pNode, i )
{
if ( i == Abc_NtkCoNum(pNtk) - pNtk->nBarBufs )
break;
Map_ManReadOutputs(pMan)[i] = Map_NotCond( (Map_Node_t *)Abc_ObjFanin0(pNode)->pCopy, (int)Abc_ObjFaninC0(pNode) );
}
return pMan;
}
