void Ana_Set_Reg(kal_uint32 offset, kal_uint32 value, kal_uint32 mask) { volatile kal_uint32 address = (offset); volatile kal_uint32 *Analog_Register = (volatile kal_uint32 *)address; volatile kal_uint32 val_tmp; AudDrv_ANA_Clk_On(); val_tmp = READ_REGISTER_UINT32(Analog_Register); val_tmp &= (~mask); val_tmp |= (value&mask); mt65xx_reg_sync_writel(val_tmp,Analog_Register); AudDrv_ANA_Clk_Off(); //Back Ana Reg Ana_Backup_Reg(address,val_tmp); if(Ana_Check_Backup_Memory(offset)==0){ xlog_printk(ANDROID_LOG_INFO, "Sound","Fail to backup Ana Register @Offset=0x%x\n",offset); } /* *Analog_Register &= (~mask); dsb(); *Analog_Register |= (value&mask); dsb(); */ }
static int mtk_pcm_dl1_open(struct snd_pcm_substream *substream) { int ret = 0; struct snd_pcm_runtime *runtime = substream->runtime; PRINTK_AUDDRV("mtk_pcm_dl1_open\n"); AfeControlSramLock(); if (GetSramState() == SRAM_STATE_FREE) { mtk_pcm_dl1_hardware.buffer_bytes_max = GetPLaybackSramFullSize(); mPlaybackSramState = SRAM_STATE_PLAYBACKFULL; SetSramState(mPlaybackSramState); } else { mtk_pcm_dl1_hardware.buffer_bytes_max = GetPLaybackDramSize(); mPlaybackSramState = SRAM_STATE_PLAYBACKDRAM; } AfeControlSramUnLock(); if (mPlaybackSramState == SRAM_STATE_PLAYBACKDRAM) { AudDrv_Emi_Clk_On(); } printk("mtk_pcm_dl1_hardware.buffer_bytes_max = %zu mPlaybackSramState = %d\n", mtk_pcm_dl1_hardware.buffer_bytes_max, mPlaybackSramState); runtime->hw = mtk_pcm_dl1_hardware; AudDrv_ANA_Clk_On(); AudDrv_Clk_On(); memcpy((void *)(&(runtime->hw)), (void *)&mtk_pcm_dl1_hardware , sizeof(struct snd_pcm_hardware)); pMemControl = Get_Mem_ControlT(Soc_Aud_Digital_Block_MEM_DL1); ret = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &constraints_sample_rates); if (ret < 0) { printk("snd_pcm_hw_constraint_integer failed\n"); } if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { printk("SNDRV_PCM_STREAM_PLAYBACK mtkalsa_dl1playback_constraints\n"); } else { printk("SNDRV_PCM_STREAM_CAPTURE mtkalsa_dl1playback_constraints\n"); } if (ret < 0) { printk("ret < 0 mtk_soc_pcm_dl1_close\n"); mtk_soc_pcm_dl1_close(substream); return ret; } //PRINTK_AUDDRV("mtk_pcm_dl1_open return\n"); return 0; }
void AudDrv_HDMI_Clk_On(void) { PRINTK_AUD_CLK("+AudDrv_HDMI_Clk_On, Aud_I2S_Clk_cntr:%d \n", Aud_HDMI_Clk_cntr); if (Aud_HDMI_Clk_cntr == 0) { AudDrv_ANA_Clk_On(); AudDrv_Clk_On(); } Aud_HDMI_Clk_cntr++; }
kal_uint32 Ana_Get_Reg(kal_uint32 offset) { volatile kal_uint32 *value , ret =0; UINT32 address = (offset); AudDrv_ANA_Clk_On(); value = (volatile kal_uint32 *)(address); ret = *value; AudDrv_ANA_Clk_Off(); return ret; }
static int mtk_voice_bt_pcm_open(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; int err = 0; int ret = 0; AudDrv_ANA_Clk_On(); AudDrv_Clk_On(); pr_debug("mtk_voice_bt_pcm_open\n"); if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { pr_err("%s with SNDRV_PCM_STREAM_CAPTURE\n", __func__); runtime->rate = 16000; return 0; } runtime->hw = mtk_pcm_hardware; memcpy((void *)(&(runtime->hw)), (void *)&mtk_pcm_hardware, sizeof(struct snd_pcm_hardware)); ret = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &constraints_sample_rates); ret = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); if (ret < 0) pr_err("snd_pcm_hw_constraint_integer failed\n"); /* print for hw pcm information */ pr_debug("mtk_voice_bt_pcm_open runtime rate = %d channels = %d\n", runtime->rate, runtime->channels); runtime->hw.info |= SNDRV_PCM_INFO_INTERLEAVED; runtime->hw.info |= SNDRV_PCM_INFO_NONINTERLEAVED; if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { pr_debug("SNDRV_PCM_STREAM_PLAYBACK mtkalsa_voice_bt_constraints\n"); runtime->rate = 16000; } if (err < 0) { pr_err("mtk_voice_bt_close\n"); mtk_voice_bt_close(substream); return err; } pr_debug("mtk_voice_bt_pcm_open return\n"); return 0; }
static int mtk_voice_bt1_prepare(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtimeStream = substream->runtime; pr_debug("mtk_alsa_prepare rate = %d channels = %d period_size = %lu\n", runtimeStream->rate, runtimeStream->channels, runtimeStream->period_size); if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { pr_err("%s with SNDRV_PCM_STREAM_CAPTURE\n", __func__); return 0; } AudDrv_ANA_Clk_On(); AudDrv_Clk_On(); /* here start digital part */ SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I02, Soc_Aud_InterConnectionOutput_O17); SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I02, Soc_Aud_InterConnectionOutput_O18); SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I14, Soc_Aud_InterConnectionOutput_O02); SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I21, Soc_Aud_InterConnectionOutput_O08); if (GetMemoryPathEnable(Soc_Aud_Digital_Block_DAI_BT) == false) { /* set merge interface */ SetMemoryPathEnable(Soc_Aud_Digital_Block_DAI_BT, true); } else SetMemoryPathEnable(Soc_Aud_Digital_Block_DAI_BT, true); /* now use samplerate 8000 */ SetModemSpeechDAIBTAttribute(runtimeStream->rate); SetDaiBtEnable(true); voice_bt1Pcm.mPcmModeWidebandSel = (runtimeStream->rate == 8000) ? Soc_Aud_PCM_MODE_PCM_MODE_8K : Soc_Aud_PCM_MODE_PCM_MODE_16K; voice_bt1Pcm.mAsyncFifoSel = Soc_Aud_BYPASS_SRC_SLAVE_USE_ASYNC_FIFO; SetModemPcmConfig(MODEM_1, voice_bt1Pcm); SetModemPcmEnable(MODEM_1, true); EnableAfe(true); voice_bt_Status = true; return 0; }
static int mtk_bt_dai_pcm_open(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; int ret = 0; printk("mtk_bt_dai_pcm_open\n"); Bt_Dai_Control_context = Get_Mem_ControlT(Soc_Aud_Digital_Block_MEM_DAI); runtime->hw = mtk_btdai_hardware; memcpy((void *)(&(runtime->hw)), (void *)&mtk_btdai_hardware , sizeof(struct snd_pcm_hardware)); ret = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &bt_dai_constraints_sample_rates); ret = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); if (ret < 0) { printk("snd_pcm_hw_constraint_integer failed\n"); } AudDrv_ANA_Clk_On(); AudDrv_Clk_On(); //print for hw pcm information printk("mtk_bt_dai_pcm_open runtime rate = %d channels = %d \n", runtime->rate, runtime->channels); runtime->hw.info |= SNDRV_PCM_INFO_INTERLEAVED; runtime->hw.info |= SNDRV_PCM_INFO_NONINTERLEAVED; if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { printk("SNDRV_PCM_STREAM_CAPTURE \n"); } else { return -1; } if (ret < 0) { printk("mtk_bt_dai_pcm_close\n"); mtk_bt_dai_pcm_close(substream); return ret; } printk("mtk_bt_dai_pcm_open return\n"); return 0; }
static int mtk_mrgrx_awb_pcm_open(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; int ret = 0; printk("mtk_mrgrx_awb_pcm_open\n"); Mrgrx_AWB_Control_context = Get_Mem_ControlT(Soc_Aud_Digital_Block_MEM_AWB); runtime->hw = mtk_mgrrx_awb_hardware; memcpy((void *)(&(runtime->hw)), (void *)&mtk_mgrrx_awb_hardware , sizeof(struct snd_pcm_hardware)); ret = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &mrgrx_awb_constraints_sample_rates); ret = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); if (ret < 0) { printk("snd_pcm_hw_constraint_integer failed\n"); } printk("mtk_mrgrx_awb_pcm_open runtime rate = %d channels = %d \n", runtime->rate, runtime->channels); if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { printk("SNDRV_PCM_STREAM_CAPTURE \n"); } else { return -1; } // here open audio clocks AudDrv_ANA_Clk_On(); AudDrv_Clk_On(); AudDrv_Emi_Clk_On(); if (ret < 0) { printk("mtk_mrgrx_awb_pcm_close\n"); mtk_mrgrx_awb_pcm_close(substream); return ret; } printk("mtk_mrgrx_awb_pcm_open return\n"); return 0; }
static int mtk_pcm_mrgrx_open(struct snd_pcm_substream *substream) { struct snd_pcm_runtime *runtime = substream->runtime; int ret = 0; AudDrv_ANA_Clk_On(); AudDrv_Clk_On(); printk("mtk_pcm_mrgrx_open\n"); runtime->hw = mtk_mrgrx_hardware; memcpy((void *)(&(runtime->hw)), (void *)&mtk_mrgrx_hardware , sizeof(struct snd_pcm_hardware)); ret = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &mrgrx_constraints_sample_rates); ret = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS); if (ret < 0) { printk("snd_pcm_hw_constraint_integer failed\n"); } printk("mtk_pcm_mrgrx_open runtime rate = %d channels = %d substream->pcm->device = %d\n", runtime->rate, runtime->channels, substream->pcm->device); if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { printk("SNDRV_PCM_STREAM_PLAYBACK mtkalsa_mrgrx_playback_constraints\n"); } else { } if (ret < 0) { printk("mtk_pcm_mrgrx_close\n"); mtk_pcm_mrgrx_close(substream); return ret; } SetFMEnableFlag(true); printk("mtk_pcm_mrgrx_open return\n"); return 0; }
static int mtk_voice_bt_pm_ops_resume(struct device *device) { bool b_modem1_speech_on; bool b_modem2_speech_on; AudDrv_ANA_Clk_On(); AudDrv_Clk_On(); /* should enable clk for access reg */ b_modem1_speech_on = (bool) (Afe_Get_Reg(PCM2_INTF_CON) & 0x1); b_modem2_speech_on = (bool) (Afe_Get_Reg(PCM_INTF_CON) & 0x1); AudDrv_Clk_Off(); AudDrv_ANA_Clk_Off(); if (b_modem1_speech_on == true || b_modem2_speech_on == true) { #ifdef CONFIG_MTK_CLKMGR clkmux_sel(MT_MUX_AUDINTBUS, 1, "AUDIO"); /* mainpll */ #endif return 0; } return 0; }
/* supend and resume function */ static int mtk_voice_bt_pm_ops_suspend(struct device *device) { /* if now in phone call state, not suspend!! */ bool b_modem1_speech_on; bool b_modem2_speech_on; AudDrv_ANA_Clk_On(); AudDrv_Clk_On(); /* should enable clk for access reg */ b_modem1_speech_on = (bool) (Afe_Get_Reg(PCM2_INTF_CON) & 0x1); b_modem2_speech_on = (bool) (Afe_Get_Reg(PCM_INTF_CON) & 0x1); AudDrv_Clk_Off(); AudDrv_ANA_Clk_Off(); if (b_modem1_speech_on == true || b_modem2_speech_on == true) { #ifdef CONFIG_MTK_CLKMGR clkmux_sel(MT_MUX_AUDINTBUS, 0, "AUDIO"); /* select 26M */ #endif return 0; } return 0; }
static int mtk_pcm_hdmi_open(struct snd_pcm_substream *substream) { int ret = 0; struct snd_pcm_runtime *runtime = substream->runtime; pr_debug("%s\n", __func__); AudDrv_ANA_Clk_On(); AudDrv_Emi_Clk_On(); AudDrv_Clk_On(); runtime->hw = mtk_hdmi_hardware; pMemControl = Get_Mem_ControlT(Soc_Aud_Digital_Block_MEM_HDMI); memcpy((void *)(&(runtime->hw)), (void *)&mtk_hdmi_hardware, sizeof(struct snd_pcm_hardware)); ret = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &constraints_sample_rates); if (ret < 0) { PRINTK_AUD_HDMI("snd_pcm_hw_constraint_integer failed\n"); return ret; } /* print for hw pcm information */ pr_debug("%s, runtime->rate = %d, channels = %d, substream->pcm->device = %d\n", __func__, runtime->rate, runtime->channels, substream->pcm->device); runtime->hw.info |= SNDRV_PCM_INFO_INTERLEAVED; runtime->hw.info |= SNDRV_PCM_INFO_NONINTERLEAVED; runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID; PRINTK_AUD_HDMI("mtk_pcm_hdmi_open return\n"); return 0; }
void Ana_Log_Print(void) { AudDrv_ANA_Clk_On(); AudDrv_ANA_Clk_Off(); pr_debug("-Ana_Log_Print\n"); }
void Ana_Log_Print(void) { AudDrv_ANA_Clk_On(); printk("AFE_UL_DL_CON0 = 0x%x\n", Ana_Get_Reg(AFE_UL_DL_CON0)); printk("AFE_DL_SRC2_CON0_H = 0x%x\n", Ana_Get_Reg(AFE_DL_SRC2_CON0_H)); printk("AFE_DL_SRC2_CON0_L = 0x%x\n", Ana_Get_Reg(AFE_DL_SRC2_CON0_L)); printk("AFE_DL_SDM_CON0 = 0x%x\n", Ana_Get_Reg(AFE_DL_SDM_CON0)); printk("AFE_DL_SDM_CON1 = 0x%x\n", Ana_Get_Reg(AFE_DL_SDM_CON1)); printk("AFE_UL_SRC0_CON0_H = 0x%x\n", Ana_Get_Reg(AFE_UL_SRC0_CON0_H)); printk("AFE_UL_SRC0_CON0_L = 0x%x\n", Ana_Get_Reg(AFE_UL_SRC0_CON0_L)); printk("AFE_UL_SRC1_CON0_H = 0x%x\n", Ana_Get_Reg(AFE_UL_SRC1_CON0_H)); printk("AFE_UL_SRC1_CON0_L = 0x%x\n", Ana_Get_Reg(AFE_UL_SRC1_CON0_L)); printk("PMIC_AFE_TOP_CON0 = 0x%x\n", Ana_Get_Reg(PMIC_AFE_TOP_CON0)); printk("AFE_AUDIO_TOP_CON0 = 0x%x\n", Ana_Get_Reg(AFE_AUDIO_TOP_CON0)); printk("PMIC_AFE_TOP_CON0 = 0x%x\n", Ana_Get_Reg(PMIC_AFE_TOP_CON0)); printk("AFE_DL_SRC_MON0 = 0x%x\n", Ana_Get_Reg(AFE_DL_SRC_MON0)); printk("AFE_DL_SDM_TEST0 = 0x%x\n", Ana_Get_Reg(AFE_DL_SDM_TEST0)); printk("AFE_MON_DEBUG0 = 0x%x\n", Ana_Get_Reg(AFE_MON_DEBUG0)); printk("AFUNC_AUD_CON0 = 0x%x\n", Ana_Get_Reg(AFUNC_AUD_CON0)); printk("AFUNC_AUD_CON1 = 0x%x\n", Ana_Get_Reg(AFUNC_AUD_CON1)); printk("AFUNC_AUD_CON2 = 0x%x\n", Ana_Get_Reg(AFUNC_AUD_CON2)); printk("AFUNC_AUD_CON3 = 0x%x\n", Ana_Get_Reg(AFUNC_AUD_CON3)); printk("AFUNC_AUD_CON4 = 0x%x\n", Ana_Get_Reg(AFUNC_AUD_CON4)); printk("AFUNC_AUD_MON0 = 0x%x\n", Ana_Get_Reg(AFUNC_AUD_MON0)); printk("AFUNC_AUD_MON1 = 0x%x\n", Ana_Get_Reg(AFUNC_AUD_MON1)); printk("AUDRC_TUNE_MON0 = 0x%x\n", Ana_Get_Reg(AUDRC_TUNE_MON0)); printk("AFE_UP8X_FIFO_CFG0 = 0x%x\n", Ana_Get_Reg(AFE_UP8X_FIFO_CFG0)); printk("AFE_UP8X_FIFO_LOG_MON0 = 0x%x\n", Ana_Get_Reg(AFE_UP8X_FIFO_LOG_MON0)); printk("AFE_UP8X_FIFO_LOG_MON1 = 0x%x\n", Ana_Get_Reg(AFE_UP8X_FIFO_LOG_MON1)); printk("AFE_DL_DC_COMP_CFG0 = 0x%x\n", Ana_Get_Reg(AFE_DL_DC_COMP_CFG0)); printk("AFE_DL_DC_COMP_CFG1 = 0x%x\n", Ana_Get_Reg(AFE_DL_DC_COMP_CFG1)); printk("AFE_DL_DC_COMP_CFG2 = 0x%x\n", Ana_Get_Reg(AFE_DL_DC_COMP_CFG2)); printk("AFE_PMIC_NEWIF_CFG0 = 0x%x\n", Ana_Get_Reg(AFE_PMIC_NEWIF_CFG0)); printk("AFE_PMIC_NEWIF_CFG1 = 0x%x\n", Ana_Get_Reg(AFE_PMIC_NEWIF_CFG1)); printk("AFE_PMIC_NEWIF_CFG2 = 0x%x\n", Ana_Get_Reg(AFE_PMIC_NEWIF_CFG2)); printk("AFE_PMIC_NEWIF_CFG3 = 0x%x\n", Ana_Get_Reg(AFE_PMIC_NEWIF_CFG3)); printk("AFE_SGEN_CFG0 = 0x%x\n", Ana_Get_Reg(AFE_SGEN_CFG0)); printk("AFE_SGEN_CFG1 = 0x%x\n", Ana_Get_Reg(AFE_SGEN_CFG1)); printk("AFE_VOW_TOP = 0x%x\n", Ana_Get_Reg(AFE_VOW_TOP)); printk("AFE_VOW_CFG0 = 0x%x\n", Ana_Get_Reg(AFE_VOW_CFG0)); printk("AFE_VOW_CFG1 = 0x%x\n", Ana_Get_Reg(AFE_VOW_CFG1)); printk("AFE_VOW_CFG2 = 0x%x\n", Ana_Get_Reg(AFE_VOW_CFG2)); printk("AFE_VOW_CFG3 = 0x%x\n", Ana_Get_Reg(AFE_VOW_CFG3)); printk("AFE_VOW_CFG4 = 0x%x\n", Ana_Get_Reg(AFE_VOW_CFG4)); printk("AFE_VOW_CFG5 = 0x%x\n", Ana_Get_Reg(AFE_VOW_CFG5)); printk("AFE_VOW_MON0 = 0x%x\n", Ana_Get_Reg(AFE_VOW_MON0)); printk("AFE_VOW_MON1 = 0x%x\n", Ana_Get_Reg(AFE_VOW_MON1)); printk("AFE_VOW_MON2 = 0x%x\n", Ana_Get_Reg(AFE_VOW_MON2)); printk("AFE_VOW_MON3 = 0x%x\n", Ana_Get_Reg(AFE_VOW_MON3)); printk("AFE_VOW_MON4 = 0x%x\n", Ana_Get_Reg(AFE_VOW_MON4)); printk("AFE_VOW_MON5 = 0x%x\n", Ana_Get_Reg(AFE_VOW_MON5)); printk("AFE_DCCLK_CFG0 = 0x%x\n", Ana_Get_Reg(AFE_DCCLK_CFG0)); printk("AFE_DCCLK_CFG1 = 0x%x\n", Ana_Get_Reg(AFE_DCCLK_CFG1)); printk("TOP_CON = 0x%x\n", Ana_Get_Reg(TOP_CON)); printk("TOP_STATUS = 0x%x\n", Ana_Get_Reg(TOP_STATUS)); printk("TOP_CKPDN_CON0 = 0x%x\n", Ana_Get_Reg(TOP_CKPDN_CON0)); printk("TOP_CKPDN_CON1 = 0x%x\n", Ana_Get_Reg(TOP_CKPDN_CON1)); printk("TOP_CKPDN_CON2 = 0x%x\n", Ana_Get_Reg(TOP_CKPDN_CON2)); printk("TOP_CKPDN_CON3 = 0x%x\n", Ana_Get_Reg(TOP_CKPDN_CON3)); printk("TOP_CKSEL_CON0 = 0x%x\n", Ana_Get_Reg(TOP_CKSEL_CON0)); printk("TOP_CKSEL_CON1 = 0x%x\n", Ana_Get_Reg(TOP_CKSEL_CON1)); printk("TOP_CKSEL_CON2 = 0x%x\n", Ana_Get_Reg(TOP_CKSEL_CON2)); printk("TOP_CKDIVSEL_CON = 0x%x\n", Ana_Get_Reg(TOP_CKDIVSEL_CON)); printk("TOP_CKHWEN_CON = 0x%x\n", Ana_Get_Reg(TOP_CKHWEN_CON)); printk("TOP_CKTST_CON0 = 0x%x\n", Ana_Get_Reg(TOP_CKTST_CON0)); printk("TOP_CKTST_CON1 = 0x%x\n", Ana_Get_Reg(TOP_CKTST_CON1)); printk("TOP_CKTST_CON2 = 0x%x\n", Ana_Get_Reg(TOP_CKTST_CON2)); printk("TOP_CLKSQ = 0x%x\n", Ana_Get_Reg(TOP_CLKSQ)); printk("TOP_RST_CON0 = 0x%x\n", Ana_Get_Reg(TOP_RST_CON0)); printk("ZCD_CON0 = 0x%x\n", Ana_Get_Reg(ZCD_CON0)); printk("ZCD_CON1 = 0x%x\n", Ana_Get_Reg(ZCD_CON1)); printk("ZCD_CON2 = 0x%x\n", Ana_Get_Reg(ZCD_CON2)); printk("ZCD_CON3 = 0x%x\n", Ana_Get_Reg(ZCD_CON3)); printk("ZCD_CON4 = 0x%x\n", Ana_Get_Reg(ZCD_CON4)); printk("ZCD_CON5 = 0x%x\n", Ana_Get_Reg(ZCD_CON5)); printk("LDO_CON1 = 0x%x\n", Ana_Get_Reg(LDO_CON1)); printk("LDO_CON2 = 0x%x\n", Ana_Get_Reg(LDO_CON2)); printk("LDO_VCON1 = 0x%x\n", Ana_Get_Reg(LDO_VCON1)); printk("SPK_CON0 = 0x%x\n", Ana_Get_Reg(SPK_CON0)); printk("SPK_CON1 = 0x%x\n", Ana_Get_Reg(SPK_CON1)); printk("SPK_CON2 = 0x%x\n", Ana_Get_Reg(SPK_CON2)); printk("SPK_CON3 = 0x%x\n", Ana_Get_Reg(SPK_CON3)); printk("SPK_CON4 = 0x%x\n", Ana_Get_Reg(SPK_CON4)); printk("SPK_CON5 = 0x%x\n", Ana_Get_Reg(SPK_CON5)); printk("SPK_CON6 = 0x%x\n", Ana_Get_Reg(SPK_CON6)); printk("SPK_CON7 = 0x%x\n", Ana_Get_Reg(SPK_CON7)); printk("SPK_CON8 = 0x%x\n", Ana_Get_Reg(SPK_CON8)); printk("SPK_CON9 = 0x%x\n", Ana_Get_Reg(SPK_CON9)); printk("SPK_CON10 = 0x%x\n", Ana_Get_Reg(SPK_CON10)); printk("SPK_CON11 = 0x%x\n", Ana_Get_Reg(SPK_CON11)); printk("SPK_CON12 = 0x%x\n", Ana_Get_Reg(SPK_CON12)); printk("SPK_CON13 = 0x%x\n", Ana_Get_Reg(SPK_CON13)); printk("SPK_CON14 = 0x%x\n", Ana_Get_Reg(SPK_CON14)); printk("SPK_CON15 = 0x%x\n", Ana_Get_Reg(SPK_CON15)); printk("SPK_CON16 = 0x%x\n", Ana_Get_Reg(SPK_CON16)); printk("SPK_ANA_CON0 = 0x%x\n", Ana_Get_Reg(SPK_ANA_CON0)); printk("SPK_ANA_CON1 = 0x%x\n", Ana_Get_Reg(SPK_ANA_CON1)); printk("SPK_ANA_CON3 = 0x%x\n", Ana_Get_Reg(SPK_ANA_CON3)); printk("AUDDEC_ANA_CON0 = 0x%x\n", Ana_Get_Reg(AUDDEC_ANA_CON0)); printk("AUDDEC_ANA_CON1 = 0x%x\n", Ana_Get_Reg(AUDDEC_ANA_CON1)); printk("AUDDEC_ANA_CON2 = 0x%x\n", Ana_Get_Reg(AUDDEC_ANA_CON2)); printk("AUDDEC_ANA_CON3 = 0x%x\n", Ana_Get_Reg(AUDDEC_ANA_CON3)); printk("AUDDEC_ANA_CON4 = 0x%x\n", Ana_Get_Reg(AUDDEC_ANA_CON4)); printk("AUDDEC_ANA_CON5 = 0x%x\n", Ana_Get_Reg(AUDDEC_ANA_CON5)); printk("AUDDEC_ANA_CON6 = 0x%x\n", Ana_Get_Reg(AUDDEC_ANA_CON6)); printk("AUDDEC_ANA_CON7 = 0x%x\n", Ana_Get_Reg(AUDDEC_ANA_CON7)); printk("AUDDEC_ANA_CON8 = 0x%x\n", Ana_Get_Reg(AUDDEC_ANA_CON8)); printk("AUDENC_ANA_CON0 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON0)); printk("AUDENC_ANA_CON1 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON1)); printk("AUDENC_ANA_CON2 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON2)); printk("AUDENC_ANA_CON3 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON3)); printk("AUDENC_ANA_CON4 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON4)); printk("AUDENC_ANA_CON5 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON5)); printk("AUDENC_ANA_CON6 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON6)); printk("AUDENC_ANA_CON7 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON7)); printk("AUDENC_ANA_CON8 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON8)); printk("AUDENC_ANA_CON9 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON9)); printk("AUDENC_ANA_CON11 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON11)); printk("AUDENC_ANA_CON12 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON12)); printk("AUDENC_ANA_CON13 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON13)); printk("AUDENC_ANA_CON14 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON14)); printk("AUDENC_ANA_CON15 = 0x%x\n", Ana_Get_Reg(AUDENC_ANA_CON15)); printk("AUDNCP_CLKDIV_CON0 = 0x%x\n", Ana_Get_Reg(AUDNCP_CLKDIV_CON0)); printk("AUDNCP_CLKDIV_CON1 = 0x%x\n", Ana_Get_Reg(AUDNCP_CLKDIV_CON1)); printk("AUDNCP_CLKDIV_CON2 = 0x%x\n", Ana_Get_Reg(AUDNCP_CLKDIV_CON2)); printk("AUDNCP_CLKDIV_CON3 = 0x%x\n", Ana_Get_Reg(AUDNCP_CLKDIV_CON3)); printk("AUDNCP_CLKDIV_CON4 = 0x%x\n", Ana_Get_Reg(AUDNCP_CLKDIV_CON4)); printk("TOP_CKPDN_CON0 = 0x%x\n", Ana_Get_Reg(TOP_CKPDN_CON0)); printk("GPIO_MODE3 = 0x%x\n", Ana_Get_Reg(GPIO_MODE3)); printk("AFE_VOW_POSDIV_CFG0 = 0x%x\n", Ana_Get_Reg(AFE_VOW_POSDIV_CFG0)); AudDrv_ANA_Clk_Off(); printk("-Ana_Log_Print \n"); }
void Ana_Log_Print(void) { AudDrv_ANA_Clk_On(); pr_warn("ABB_AFE_CON0 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON0)); pr_warn("ABB_AFE_CON1 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON1)); pr_warn("ABB_AFE_CON2 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON2)); pr_warn("ABB_AFE_CON3 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON3)); pr_warn("ABB_AFE_CON4 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON4)); pr_warn("ABB_AFE_CON5 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON5)); pr_warn("ABB_AFE_CON6 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON6)); pr_warn("ABB_AFE_CON7 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON7)); pr_warn("ABB_AFE_CON8 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON8)); pr_warn("ABB_AFE_CON9 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON9)); pr_warn("ABB_AFE_CON10 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON10)); pr_warn("ABB_AFE_CON11 = 0x%x\n", Ana_Get_Reg(ABB_AFE_CON11)); pr_warn("ABB_AFE_STA0 = 0x%x\n", Ana_Get_Reg(ABB_AFE_STA0)); pr_warn("ABB_AFE_STA1 = 0x%x\n", Ana_Get_Reg(ABB_AFE_STA1)); pr_warn("ABB_AFE_STA2 = 0x%x\n", Ana_Get_Reg(ABB_AFE_STA2)); pr_warn("ABB_AFE_UP8X_FIFO_CFG0 = 0x%x\n", Ana_Get_Reg(ABB_AFE_UP8X_FIFO_CFG0)); pr_warn("ABB_AFE_UP8X_FIFO_LOG_MON0 = 0x%x\n", Ana_Get_Reg(ABB_AFE_UP8X_FIFO_LOG_MON0)); pr_warn("ABB_AFE_UP8X_FIFO_LOG_MON1 = 0x%x\n", Ana_Get_Reg(ABB_AFE_UP8X_FIFO_LOG_MON1)); pr_warn("ABB_AFE_PMIC_NEWIF_CFG0 = 0x%x\n", Ana_Get_Reg(ABB_AFE_PMIC_NEWIF_CFG0)); pr_warn("ABB_AFE_PMIC_NEWIF_CFG1 = 0x%x\n", Ana_Get_Reg(ABB_AFE_PMIC_NEWIF_CFG1)); pr_warn("ABB_AFE_PMIC_NEWIF_CFG2 = 0x%x\n", Ana_Get_Reg(ABB_AFE_PMIC_NEWIF_CFG2)); pr_warn("ABB_AFE_PMIC_NEWIF_CFG3 = 0x%x\n", Ana_Get_Reg(ABB_AFE_PMIC_NEWIF_CFG3)); pr_warn("ABB_AFE_TOP_CON0 = 0x%x\n", Ana_Get_Reg(ABB_AFE_TOP_CON0)); pr_warn("ABB_AFE_MON_DEBUG0 = 0x%x\n", Ana_Get_Reg(ABB_AFE_MON_DEBUG0)); pr_warn("SPK_CON0 = 0x%x\n", Ana_Get_Reg(SPK_CON0)); pr_warn("SPK_CON1 = 0x%x\n", Ana_Get_Reg(SPK_CON1)); pr_warn("SPK_CON2 = 0x%x\n", Ana_Get_Reg(SPK_CON2)); pr_warn("SPK_CON6 = 0x%x\n", Ana_Get_Reg(SPK_CON6)); pr_warn("SPK_CON7 = 0x%x\n", Ana_Get_Reg(SPK_CON7)); pr_warn("SPK_CON8 = 0x%x\n", Ana_Get_Reg(SPK_CON8)); pr_warn("SPK_CON9 = 0x%x\n", Ana_Get_Reg(SPK_CON9)); pr_warn("SPK_CON10 = 0x%x\n", Ana_Get_Reg(SPK_CON10)); pr_warn("SPK_CON11 = 0x%x\n", Ana_Get_Reg(SPK_CON11)); pr_warn("SPK_CON12 = 0x%x\n", Ana_Get_Reg(SPK_CON12)); pr_warn("CID = 0x%x\n", Ana_Get_Reg(CID)); pr_warn("TOP_CKPDN0 = 0x%x\n", Ana_Get_Reg(TOP_CKPDN0)); pr_warn("TOP_CKPDN0_SET = 0x%x\n", Ana_Get_Reg(TOP_CKPDN0_SET)); pr_warn("TOP_CKPDN0_CLR = 0x%x\n", Ana_Get_Reg(TOP_CKPDN0_CLR)); pr_warn("TOP_CKPDN1 = 0x%x\n", Ana_Get_Reg(TOP_CKPDN1)); pr_warn("TOP_CKPDN1_SET = 0x%x\n", Ana_Get_Reg(TOP_CKPDN1_SET)); pr_warn("TOP_CKPDN1_CLR = 0x%x\n", Ana_Get_Reg(TOP_CKPDN1_CLR)); pr_warn("TOP_CKPDN2 = 0x%x\n", Ana_Get_Reg(TOP_CKPDN2)); pr_warn("TOP_CKPDN2_SET = 0x%x\n", Ana_Get_Reg(TOP_CKPDN2_SET)); pr_warn("TOP_CKPDN2_CLR = 0x%x\n", Ana_Get_Reg(TOP_CKPDN2_CLR)); pr_warn("TOP_CKCON1 = 0x%x\n", Ana_Get_Reg(TOP_CKCON1)); pr_warn("AUDTOP_CON0 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON0)); pr_warn("AUDTOP_CON1 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON1)); pr_warn("AUDTOP_CON2 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON2)); pr_warn("AUDTOP_CON3 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON3)); pr_warn("AUDTOP_CON4 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON4)); pr_warn("AUDTOP_CON5 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON5)); pr_warn("AUDTOP_CON6 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON6)); pr_warn("AUDTOP_CON7 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON7)); pr_warn("AUDTOP_CON8 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON8)); pr_warn("AUDTOP_CON9 = 0x%x\n", Ana_Get_Reg(AUDTOP_CON9)); AudDrv_ANA_Clk_Off(); pr_warn("-Ana_Log_Print\n"); }
static int Audio_hdmi_SideGen_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { pr_debug("%s()\n", __func__); if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(HDMI_SIDEGEN)) { pr_err("return -EINVAL\n"); return -EINVAL; } #ifdef _TDM_8CH_SGEN_TEST mHdmi_sidegen_control = ucontrol->value.integer.value[0]; if (mHdmi_sidegen_control) { uint32 samplerate = 44100; uint32 HDMIchaanel = 8; uint32 MclkDiv = 0; /* Enable Audio Driver Clock */ AudDrv_ANA_Clk_On(); AudDrv_Clk_On(); AudDrv_Emi_Clk_On(); /* Enable APLL */ EnableApll(samplerate, true); EnableApllTuner(samplerate, true); /* HDMI I2S clock setting */ MclkDiv = SetCLkMclk(Soc_Aud_HDMI_MCK, samplerate); SetCLkHdmiBclk(MclkDiv, samplerate, 2, 32); /* enable mclk divider */ EnableSpdifDivPower(AUDIO_APLL_SPDIF_DIV, true); /* enable bck divider */ EnableHDMIDivPower(AUDIO_APLL_HDMI_BCK_DIV, true); /* turn on hdmi clk */ SetHdmiClkOn(); /* Set Mem buffer */ SetHDMIAddress(); copysinewavetohdmi(8); /* config hdmi irq */ SetIrqMcuCounter(Soc_Aud_IRQ_MCU_MODE_IRQ5_MCU_MODE, 44100); /* config hdmi interface */ SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_HDMI, AFE_WLEN_16_BIT); /* now fix 16bit */ SetHdmiTdm1Config(44100, AFE_DATA_WLEN_32BIT); SetHdmiTdm2Config(44100); SetHDMIChannels(HDMIchaanel); /* config hdmi connection */ SetHDMIConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I30, Soc_Aud_InterConnectionOutput_O30); SetHDMIConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I31, Soc_Aud_InterConnectionOutput_O31); SetHDMIConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I30, Soc_Aud_InterConnectionOutput_O32); SetHDMIConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I31, Soc_Aud_InterConnectionOutput_O33); SetHDMIConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I30, Soc_Aud_InterConnectionOutput_O34); SetHDMIConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I31, Soc_Aud_InterConnectionOutput_O35); SetHDMIConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I30, Soc_Aud_InterConnectionOutput_O36); SetHDMIConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I31, Soc_Aud_InterConnectionOutput_O37); /* Enable hdmi Memory Path */ SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_HDMI, true); /* enable irq */ SetIrqEnable(Soc_Aud_IRQ_MCU_MODE_IRQ5_MCU_MODE, true); /* enable hdmi out */ SetHDMIEnable(true); /* enable afe */ EnableAfe(true); /* enable TDM */ SetTDMEnable(HDMIchaanel); } else { uint32 HDMIchaanel = 8; SetTDMEnable(false); SetHDMIEnable(false); SetIrqEnable(Soc_Aud_IRQ_MCU_MODE_IRQ5_MCU_MODE, false); SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_HDMI, false); EnableAfe(false); SetHdmiPcmInterConnection(Soc_Aud_InterCon_DisConnect, HDMIchaanel); SetHdmiClkOff(); EnableSpdifDivPower(AUDIO_APLL_SPDIF_DIV, false); EnableHDMIDivPower(AUDIO_APLL_HDMI_BCK_DIV, false); AudDrv_Emi_Clk_Off(); AudDrv_Clk_Off(); AudDrv_ANA_Clk_Off(); } #endif return 0; }