C++ (Cpp) AudDrv_APLL1Tuner_Clk_On Exemples

Exemple #1

Fichier : mt_soc_pcm_fmtx.c Projet : 4Fwolf/signal75-kernel-3.10.61

static int Audio_fmtx_hdoutput_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
    printk("%s()\n", __func__);
    if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(fmtx_HD_output))
    {
        printk("return -EINVAL\n");
        return -EINVAL;
    }
    fmtx_hdoutput_control = ucontrol->value.integer.value[0];
    if (fmtx_hdoutput_control)
    {
        // set APLL clock setting
        EnableApll1(true);
        EnableApll2(true);
        EnableI2SDivPower(AUDIO_APLL1_DIV0, true);
        EnableI2SDivPower(AUDIO_APLL2_DIV0, true);
        AudDrv_APLL1Tuner_Clk_On();
        AudDrv_APLL2Tuner_Clk_On();
    }
    else
    {
        // set APLL clock setting
        EnableApll1(false);
        EnableApll2(false);
        EnableI2SDivPower(AUDIO_APLL1_DIV0, false);
        EnableI2SDivPower(AUDIO_APLL2_DIV0, false);
        AudDrv_APLL1Tuner_Clk_Off();
        AudDrv_APLL2Tuner_Clk_Off();
    }
    return 0;
}

Exemple #2

Fichier : mt_soc_pcm_dl1_i2s0Dl1.c Projet : SelfImp/m75

static int Audio_I2S0dl1_hdoutput_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
    pr_debug("%s()\n", __func__);
    if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(I2S0dl1_HD_output))
    {
        printk("return -EINVAL\n");
        return -EINVAL;
    }
    mI2S0dl1_hdoutput_control = ucontrol->value.integer.value[0];
// Flyme{ [email protected] No need to set these registers, because "Audio_i2s0_hd_Switch" will setup them
#if 0
    if (mI2S0dl1_hdoutput_control)
    {
        // set APLL clock setting
        EnableApll1(true);
        EnableApll2(true);
        EnableI2SDivPower(AUDIO_APLL1_DIV0, true);
        EnableI2SDivPower(AUDIO_APLL2_DIV0, true);
        AudDrv_APLL1Tuner_Clk_On();
        AudDrv_APLL2Tuner_Clk_On();
    }
    else
    {
        // set APLL clock setting
        EnableApll1(false);
        EnableApll2(false);
        EnableI2SDivPower(AUDIO_APLL1_DIV0, false);
        EnableI2SDivPower(AUDIO_APLL2_DIV0, false);
        AudDrv_APLL1Tuner_Clk_Off();
        AudDrv_APLL2Tuner_Clk_Off();
    }
#endif
// }
    return 0;
}

Exemple #3

Fichier : mt_soc_pcm_dl1_i2s0Dl1.c Projet : AudioGod/MediaTek-HelioX10-Kernel

static int Audio_I2S0dl1_hdoutput_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
    printk("%s()\n", __func__);
    if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(I2S0dl1_HD_output))
    {
        printk("return -EINVAL\n");
        return -EINVAL;
    }

    mI2S0dl1_hdoutput_control = ucontrol->value.integer.value[0];

    if (GetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_HDMI) == true )
    {
        printk("return HDMI enabled\n");
    
        return 0;
    }  

    if (mI2S0dl1_hdoutput_control)
    {
        // set APLL clock setting
        AudDrv_Clk_On();
        EnableApll1(true);
        EnableApll2(true);
        EnableI2SDivPower(AUDIO_APLL1_DIV0, true);
        EnableI2SDivPower(AUDIO_APLL2_DIV0, true);
        AudDrv_APLL1Tuner_Clk_On();
        AudDrv_APLL2Tuner_Clk_On();
    }
    else
    {  
        // set APLL clock setting
        EnableApll1(false);
        EnableApll2(false);
        EnableI2SDivPower(AUDIO_APLL1_DIV0, false);
        EnableI2SDivPower(AUDIO_APLL2_DIV0, false);
        AudDrv_APLL1Tuner_Clk_Off();
        AudDrv_APLL2Tuner_Clk_Off();
        AudDrv_Clk_Off();
    }
    return 0;
}

Exemple #4

Fichier : mt_soc_pcm_dl1_i2s0.c Projet : AudioGod/MediaTek-HelioX10-Kernel

static int Audio_i2s0_hdoutput_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
    printk("+%s()\n", __func__);
    if (ucontrol->value.enumerated.item[0] > ARRAY_SIZE(i2s0_HD_output))
    {
        printk("return -EINVAL\n");
        return -EINVAL;
    }
    AudDrv_Clk_On();

    if ( (ucontrol->value.integer.value[0] == true) &&(mi2s0_hdoutput_control == false) )
    {
        printk("%s(), mi2s0_hdoutput_control=%d, enable APLL!!!!\n", __func__, mi2s0_hdoutput_control);
        // set APLL clock setting
        EnableApll1(true);
        EnableApll2(true);
        EnableI2SDivPower(AUDIO_APLL1_DIV0, true);
        EnableI2SDivPower(AUDIO_APLL2_DIV0, true);
        AudDrv_APLL1Tuner_Clk_On();
        AudDrv_APLL2Tuner_Clk_On();
    }
    else if( (ucontrol->value.integer.value[0] == false) &&(mi2s0_hdoutput_control == true) )
    {
        printk("%s(), mi2s0_hdoutput_control=%d, disable APLL!!!!\n", __func__, mi2s0_hdoutput_control);
        // set APLL clock setting
        EnableApll1(false);
        EnableApll2(false);
        EnableI2SDivPower(AUDIO_APLL1_DIV0, false);
        EnableI2SDivPower(AUDIO_APLL2_DIV0, false);
        AudDrv_APLL1Tuner_Clk_Off();
        AudDrv_APLL2Tuner_Clk_Off();
    }

    mi2s0_hdoutput_control = ucontrol->value.integer.value[0];
    printk("%s(), mi2s0_hdoutput_control=%d\n", __func__, mi2s0_hdoutput_control);

    AudDrv_Clk_Off();
    printk("-%s(), mi2s0_hdoutput_control=%d\n", __func__, mi2s0_hdoutput_control);
    return 0;
}