static void initialize_dbgu(void) { unsigned int baudrate = 115200; at91_dbgu_hw_init(); if (pmc_check_mck_h32mxdiv()) usart_init(BAUDRATE(MASTER_CLOCK / 2, baudrate)); else usart_init(BAUDRATE(MASTER_CLOCK, baudrate)); }
static void initialize_dbgu(void) { unsigned int baudrate = 115200; at91_dbgu_hw_init(); usart_init(BAUDRATE(MASTER_CLOCK / 2, baudrate)); }
/*-----------------------------------------------------------------------------*/ void PopulateCOMSettings(HWND hDlg) { char szBuffer[MAXLEN_TEMPSTR]; WORD wCount, wPosition; // Fill baud combo box and make initial selection FillComboBox(GetDlgItem(hDlg, IDC_BPS_COMBO), szBaud, BaudTable, sizeof(BaudTable) / sizeof(BaudTable[0]), BAUDRATE(TTYInfo)); // Fill data bits combo box and make initial selection for (wCount = 5; wCount < 9; wCount++) { wsprintf(szBuffer, "%d", wCount); wPosition = LOWORD(SendDlgItemMessage(hDlg, IDC_DATABITS_COMBO, CB_ADDSTRING, 0, (LPARAM)(LPSTR)szBuffer)); if (wCount == BYTESIZE(TTYInfo)) { SendDlgItemMessage(hDlg, IDC_DATABITS_COMBO, CB_SETCURSEL, (WPARAM)wPosition, 0L); } } // Fill parity combo box and make initial selection FillComboBox(GetDlgItem(hDlg, IDC_PARITY_COMBO), szParity, ParityTable, sizeof(ParityTable) / sizeof(ParityTable[0]), PARITY(TTYInfo)); // Fill stop bits combo box and make initial selection FillComboBox(GetDlgItem(hDlg, IDC_STOPBITS_COMBO), szStopBits, StopBitsTable, sizeof(StopBitsTable) / sizeof(StopBitsTable[0]), STOPBITS(TTYInfo)); }
static void initialize_dbgu(void) { /* Configure DBGU pin */ /* {"RXD", AT91C_PIN_PB(14), 0, PIO_DEFAULT, PIO_PERIPH_A}, */ /* {"TXD", AT91C_PIN_PB(15), 0, PIO_DEFAULT, PIO_PERIPH_A}, */ writel(((0x01 << 14) | (0x01 << 15)), AT91C_BASE_PIOB + PIO_ASR(0)); writel(((0x01 << 14) | (0x01 << 15)), AT91C_BASE_PIOB + PIO_PDR(0)); writel((1 << AT91C_ID_PIOB), (PMC_PCER + AT91C_BASE_PMC)); dbgu_init(BAUDRATE(MASTER_CLOCK, 115200)); }
/*-----------------------------------------------------------------------------*/ void UpdateTTYInfo(HWND hDlg) { GetDlgItemText(hDlg, IDC_COMPORT_COMBO, gszPort, sizeof(gszPort)); BAUDRATE(TTYInfo) = GetdwTTYITem(hDlg, IDC_BPS_COMBO, szBaud, BaudTable, sizeof(BaudTable) / sizeof(BaudTable[0])); PARITY(TTYInfo) = GetbTTYITem(hDlg, IDC_PARITY_COMBO, szParity, ParityTable, sizeof(ParityTable) / sizeof(ParityTable[0])); STOPBITS(TTYInfo) = GetbTTYITem(hDlg, IDC_STOPBITS_COMBO, szStopBits, StopBitsTable, sizeof(StopBitsTable) / sizeof(StopBitsTable[0])); BYTESIZE(TTYInfo) = GetDlgItemInt(hDlg, IDC_DATABITS_COMBO, NULL, FALSE); }
/*-----------------------------------------------------------------------------*/ void InitTTYInfo() { // Initialize general TTY info COMDEV(TTYInfo) = NULL; CONNECTED(TTYInfo) = FALSE; PORT(TTYInfo) = '0'; // setting to 0 since we know nothing about // the current COM port configuration BAUDRATE(TTYInfo) = CBR_9600; BYTESIZE(TTYInfo) = 8; PARITY(TTYInfo) = NOPARITY; STOPBITS(TTYInfo) = ONESTOPBIT; InitFont(); ClearTTYContents(); }
static void initialize_dbgu(void) { /* const struct pio_desc dbgu_pins[] = { {"RXD", AT91C_PIN_PA(9), 0, PIO_DEFAULT, PIO_PERIPH_A}, {"TXD", AT91C_PIN_PA(10), 0, PIO_DEFAULT, PIO_PERIPH_A}, {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, }; */ /* Configure the dbgu pins */ writel(((0x01 << 9) | (0x01 << 10)), AT91C_BASE_PIOA + PIO_ASR(0)); writel(((0x01 << 9) | (0x01 << 10)), AT91C_BASE_PIOA + PIO_PDR(0)); writel((1 << AT91C_ID_PIOA), (PMC_PCER + AT91C_BASE_PMC)); dbgu_init(BAUDRATE(MASTER_CLOCK, 115200)); }
static void initialize_dbgu(void) { /* const struct pio_desc dbgu_pins[] = { {"RXD", AT91C_PIN_PA(9), 0, PIO_DEFAULT, PIO_PERIPH_A}, {"TXD", AT91C_PIN_PA(10), 0, PIO_DEFAULT, PIO_PERIPH_A}, {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, }; */ /* Configure the dbgu pins */ writel(((0x01 << 9) | (0x01 << 10)), AT91C_BASE_PIOA + PIO_ASR); writel(((0x01 << 9) | (0x01 << 10)), AT91C_BASE_PIOA + PIO_PDR); pmc_enable_periph_clock(AT91C_ID_PIOA); usart_init(BAUDRATE(MASTER_CLOCK, 115200)); }
static int SetPortAttr (int baudrate,int databit, const char *stopbit, char parity) { bzero (&termios_new, sizeof (termios_new)); cfmakeraw (&termios_new); termios_new.c_cflag = BAUDRATE (baudrate); /* set baudrate */ termios_new.c_cflag |= CLOCAL | CREAD; /* | CRTSCTS */ SetDataBit (databit); SetParityCheck (parity); SetStopBit (stopbit); termios_new.c_oflag = 0; termios_new.c_lflag |= 0; termios_new.c_oflag &= ~OPOST; termios_new.c_cc[VTIME] = 1; /* unit: 1/10 second. */ termios_new.c_cc[VMIN] = 1; /* minimal characters for reading */ tcflush (fd, TCIFLUSH); return (tcsetattr (fd, TCSANOW, &termios_new)); }
// Connects to, sets up and configures (if virgin) port. void commConnect() { DCB dcb; HMENU hMenu; // Make sure we're not connected if (!CONNECTED(TTYInfo)) { // Menu hMenu = GetMenu(ghWndMain); // get the menu handle EnableMenuItem(hMenu, ID_FILE_CONNECT, MF_GRAYED | MF_DISABLED); // disable the connect menu EnableMenuItem(hMenu, ID_FILE_DISCONNECT, MF_ENABLED); // enable the disconnect menu EnableMenuItem(hMenu, ID_EDIT_SETTINGS, MF_GRAYED | MF_DISABLED); // disable the TTY menu COMDEV(TTYInfo) = CreateFile(gszPort, GENERIC_READ | GENERIC_WRITE, 0, NULL, OPEN_EXISTING, FILE_FLAG_OVERLAPPED, NULL); FillMemory(&dcb, sizeof(dcb), 0); dcb.BaudRate = BAUDRATE(TTYInfo); // set the baud rate dcb.ByteSize = BYTESIZE(TTYInfo); // set the data bits dcb.fParity = PARITY(TTYInfo); // set the parity dcb.StopBits = STOPBITS(TTYInfo); // set the stop bits SetCommState(COMDEV(TTYInfo), &dcb); // update the COM port configuration CONNECTED(TTYInfo) = TRUE; // we are now connected (hopefully) } // Start reading thread TTYInfo.hThread = CreateThread( NULL, // security attributes 0, // inital thread stack size, in bytes commReadThread, // address of thread function ghWndTerm, // argument for new thread 0, // creation flags &TTYInfo.hThread ); // address of returned thread ID TTYInfo.fConnected = TRUE; }
static void initialize_dbgu(void) { at91_dbgu_hw_init(); dbgu_init(BAUDRATE(MASTER_CLOCK, 115200)); }
static void initialize_dbgu(void) { at91_dbgu_hw_init(); usart_init(BAUDRATE(MASTER_CLOCK, BAUD_RATE)); }
/*------------------------------------------------------------------------------*/ void hw_init(void) { unsigned int cp15; /* * Configure PIOs */ const struct pio_desc hw_pio[] = { #ifdef CONFIG_DEBUG {"RXD", AT91C_PIN_PA(21), 0, PIO_DEFAULT, PIO_PERIPH_A}, {"TXD", AT91C_PIN_PA(22), 0, PIO_DEFAULT, PIO_PERIPH_A}, #endif {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, }; /* * Disable watchdog */ writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR); /* * At this stage the main oscillator is supposed to be enabled * * PCK = MCK = MOSC */ /* * Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ pmc_cfg_plla(PLL_SETTINGS, PLL_LOCK_TIMEOUT); /* * PCK = PLL = 2 * MCK */ pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT); /* * Switch MCK on PLLA output */ pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT); /* * Enable External Reset */ writel(AT91C_RSTC_KEY_UNLOCK || AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR); /* * Configure CP15 */ cp15 = get_cp15(); //cp15 |= I_CACHE; set_cp15(cp15); #ifdef CONFIG_SCLK sclk_enable(); #endif /* * Configure the PIO controller to output PCK0 */ pio_setup(hw_pio); #ifdef CONFIG_DEBUG /* * Enable Debug messages on the DBGU */ dbgu_init(BAUDRATE(MASTER_CLOCK, 115200)); dbgu_print("Start AT91Bootstrap...\n\r"); #endif /* CONFIG_VERBOSE */ /* * Configure the EBI Slave Slot Cycle to 64 */ writel((readl((AT91C_MATRIX_SCFG4)) & ~0xFF) | 0x40, AT91C_MATRIX_SCFG4); /* * Initialize the matrix Slave 0 & Slave 4 (SRAM & EBI) */ writel(readl(AT91C_MATRIX_SCFG0) | AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR | AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D, AT91C_MATRIX_SCFG0); writel(readl(AT91C_MATRIX_SCFG4) | AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR | AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D, AT91C_MATRIX_SCFG4); #ifdef CONFIG_SDRAM /* * Initialize the matrix */ writel(readl(AT91C_CCFG_EBICSA) | AT91C_EBI_CS1A_SDRAMC, AT91C_CCFG_EBICSA); #ifdef MCK_100 /* * Configure SDRAM Controller */ sdram_init(AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_2 | AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_7 | AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_5 | AT91C_SDRAMC_TXSR_8, /* Control Register */ (MASTER_CLOCK * 7) / 1000000, /* Refresh Timer Register */ AT91C_SDRAMC_MD_SDRAM); /* SDRAM (no low power) */ #else /* 133 MHz */ /* * Configure SDRAM Controller */ sdram_init(AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_3 | AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_9 | AT91C_SDRAMC_TRP_3 | AT91C_SDRAMC_TRCD_3 | AT91C_SDRAMC_TRAS_6 | AT91C_SDRAMC_TXSR_10, /* Control Register */ (MASTER_CLOCK * 7) / 1000000, /* Refresh Timer Register */ AT91C_SDRAMC_MD_SDRAM); /* SDRAM (no low power) */ #endif #endif }
/*----------------------------------------------------------------------------*/ void hw_init(void) { unsigned int cp15; /* * Configure PIOs */ const struct pio_desc hw_pio[] = { #ifdef CONFIG_DEBUG {"RXD", AT91C_PIN_PA(9), 0, PIO_DEFAULT, PIO_PERIPH_A}, {"TXD", AT91C_PIN_PA(10), 0, PIO_DEFAULT, PIO_PERIPH_A}, #endif {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, }; /* * Disable watchdog */ writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR); /* * At this stage the main oscillator is supposed to be enabled * * PCK = MCK = MOSC */ writel(0x00, AT91C_BASE_PMC + PMC_PLLICPR); /* * Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT); /* * PCK = PLLA/2 = 3 * MCK */ pmc_cfg_mck(BOARD_PRESCALER_MAIN_CLOCK, PLL_LOCK_TIMEOUT); /* * Switch MCK on PLLA output */ pmc_cfg_mck(BOARD_PRESCALER_PLLA, PLL_LOCK_TIMEOUT); /* * Enable External Reset */ writel(AT91C_RSTC_KEY_UNLOCK || AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR); /* * Configure CP15 */ cp15 = get_cp15(); cp15 |= I_CACHE; set_cp15(cp15); #ifdef CONFIG_SCLK sclk_enable(); #endif /* * Configure the PIO controller */ writel((1 << AT91C_ID_PIOA_B), (PMC_PCER + AT91C_BASE_PMC)); pio_setup(hw_pio); /* * Enable Debug messages on the DBGU */ #ifdef CONFIG_DEBUG dbgu_init(BAUDRATE(MASTER_CLOCK, 115200)); dbgu_print("Start AT91Bootstrap...\n\r"); #endif #ifdef CONFIG_DDR2 /* * Configure DDRAM Controller */ dbg_log(1, "Init DDR... "); ddramc_hw_init(); dbg_log(1, "Done!\n\r"); #endif /* CONFIG_DDR2 */ }
/*----------------------------------------------------------------------------*/ void hw_init(void) { unsigned int cp15; /* * Configure PIOs */ const struct pio_desc hw_pio[] = { #ifdef CONFIG_DEBUG {"RXD", AT91C_PIN_PB(14), 0, PIO_DEFAULT, PIO_PERIPH_A}, {"TXD", AT91C_PIN_PB(15), 0, PIO_DEFAULT, PIO_PERIPH_A}, #endif {(char *)0, 0, 0, PIO_DEFAULT, PIO_PERIPH_A}, }; /* * Disable watchdog */ writel(AT91C_WDTC_WDDIS, AT91C_BASE_WDTC + WDTC_WDMR); /* * At this stage the main oscillator is supposed to be enabled * * PCK = MCK = MOSC */ writel(0x00, AT91C_BASE_PMC + PMC_PLLICPR); /* * Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */ pmc_cfg_plla(PLLA_SETTINGS, PLL_LOCK_TIMEOUT); /* * PCK = PLLA/2 = 3 * MCK */ pmc_cfg_mck(MCKR_SETTINGS, PLL_LOCK_TIMEOUT); /* * Switch MCK on PLLA output */ pmc_cfg_mck(MCKR_CSS_SETTINGS, PLL_LOCK_TIMEOUT); /* * Configure PLLB */ pmc_cfg_pllb(PLLB_SETTINGS, PLL_LOCK_TIMEOUT); /* * Enable External Reset */ writel(AT91C_RSTC_KEY_UNLOCK || AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR); /* * Configure CP15 */ cp15 = get_cp15(); //cp15 |= I_CACHE; set_cp15(cp15); /* * Enable External Reset */ writel(AT91C_RSTC_KEY_UNLOCK || AT91C_RSTC_URSTEN, AT91C_BASE_RSTC + RSTC_RMR); /* * Configure the PIO controller */ pio_setup(hw_pio); /* * Configure the EBI Slave Slot Cycle to 64 */ writel((readl((AT91C_BASE_MATRIX + MATRIX_SCFG3)) & ~0xFF) | 0x40, (AT91C_BASE_MATRIX + MATRIX_SCFG3)); #ifdef CONFIG_DEBUG /* * Enable Debug messages on the DBGU */ dbgu_init(BAUDRATE(MASTER_CLOCK, 115200)); dbgu_print("Start AT91Bootstrap...\n\r"); #endif /* CONFIG_DEBUG */ #ifdef CONFIG_SDRAM /* * Initialize the matrix (memory voltage = 3.3) */ writel((readl(AT91C_BASE_CCFG + CCFG_EBICSA)) | AT91C_EBI_CS1A_SDRAMC | (1 << 16), AT91C_BASE_CCFG + CCFG_EBICSA); /* * Configure SDRAM Controller */ sdram_init(AT91C_SDRAMC_NC_9 | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_3 | AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_DBW_32_BITS | AT91C_SDRAMC_TWR_3 | AT91C_SDRAMC_TRC_9 | AT91C_SDRAMC_TRP_3 | AT91C_SDRAMC_TRCD_3 | AT91C_SDRAMC_TRAS_6 | AT91C_SDRAMC_TXSR_10, /* Control Register */ (MASTER_CLOCK * 7) / 1000000, /* Refresh Timer Register */ AT91C_SDRAMC_MD_SDRAM); /* SDRAM (no low power) */ #endif /* CONFIG_SDRAM */ }
/* set serial port baudrate by use of file descriptor fd */ void SetBaudrate (int baudrate) { termios_new.c_cflag = BAUDRATE (baudrate); /* set baudrate */ }