static int __brcm_pm_memc1_clock_running(void)
{
return BDEV_RD_F(CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE,
DDR1_SCB_CLOCK_ENABLE) &&
BDEV_RD_F(CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE,
DDR1_108_CLOCK_ENABLE);
}
static int __brcm_pm_memc1_clock_running(void)
{
return !(BDEV_RD_F(CLK_DDR23_APHY_1_PM_CTRL, DIS_216M_CLK) ||
BDEV_RD_F(CLK_DDR23_APHY_1_PM_CTRL, DIS_108M_CLK) ||
BDEV_RD_F(CLK_MEMC_1_PM_CTRL, DIS_216M_CLK) ||
BDEV_RD_F(CLK_MEMC_1_PM_CTRL, DIS_108M_CLK));
}
static void brcm_pm_memc1_sspd_control(int enable)
{
if (enable) {
BDEV_WR_F_RB(MEMC_DDR_1_SSPD_CMD, SSPD, 1);
while (!BDEV_RD_F(MEMC_DDR_1_POWER_DOWN_STATUS, SSPD))
udelay(1);
} else {
BDEV_WR_F_RB(MEMC_DDR_1_SSPD_CMD, SSPD, 0);
while (BDEV_RD_F(MEMC_DDR_1_POWER_DOWN_STATUS, SSPD))
udelay(1);
}
}
/***********************************************************************
* Poll for transfer completion
***********************************************************************/
static int brcm_mem_dma_wait_for_ready(int timeout)
{
while (BDEV_RD_F(MEM_DMA_0_STATUS, DMA_STATUS) == 1) {
if (timeout > 0)
if (!--timeout)
return -1;
mdelay(1);
}
return 0;
}
static int __brcm_pm_memc1_initialized(void)
{
return BDEV_RD_F(MEMC_DDR_1_DRAM_INIT_STATUS, INIT_DONE);
}
static void __brcm_pm_memc1_resume(int mode)
{
u32 val, cur_val;
s32 sval, scur_val, inc_val;
DBG(KERN_DEBUG "%s %d\n", __func__, mode);
/* power up LDOs */
BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_PLL_CTRL1_REG,
LDO_PWRDN, 0);
BDEV_WR_F_RB(MEMC_DDR23_APHY_WL0_1_WORDSLICE_CNTRL_1,
LDO_PWRDN, 0);
BDEV_WR_F_RB(MEMC_DDR23_APHY_WL1_1_WORDSLICE_CNTRL_1,
LDO_PWRDN, 0);
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH4_WL0_DQS0_PHASE_CNTRL, 0);
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH5_WL0_DQS1_PHASE_CNTRL, 0);
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH8_WL1_DQS0_PHASE_CNTRL, 0);
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH9_WL1_DQS1_PHASE_CNTRL, 0);
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH3_WL0_DQ_PHASE_CNTRL, 0);
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH7_WL1_DQ_PHASE_CNTRL, 0);
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH2_CLOCK_PHASE_CNTRL, 0);
BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_DESKEW_DLL_CNTRL, BYPASS_PHASE, 0);
BDEV_WR_F_RB(MEMC_DDR23_APHY_WL0_1_DDR_PAD_CNTRL,
IDDQ_MODE_ON_SELFREF, 0);
BDEV_WR_F_RB(MEMC_DDR23_APHY_WL1_1_DDR_PAD_CNTRL,
IDDQ_MODE_ON_SELFREF, 0);
BDEV_WR_F_RB(MEMC_DDR23_APHY_WL0_1_WORDSLICE_CNTRL_1,
PWRDN_DLL_ON_SELFREF, 0);
BDEV_WR_F_RB(MEMC_DDR23_APHY_WL1_1_WORDSLICE_CNTRL_1,
PWRDN_DLL_ON_SELFREF, 0);
BDEV_UNSET(BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL,
BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL_DEVCLK_OFF_ON_SELFREF_MASK |
BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK);
mdelay(1);
/* reset the freq divider */
BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_RESET, FREQ_DIV_RESET, 1);
mdelay(1);
/* reset DATAPATH_216, RD_DATAPATH_RESET, RESET_DATAPATH_DDR */
BDEV_SET_RB(BCHP_MEMC_DDR23_APHY_AC_1_RESET,
BCHP_MEMC_DDR23_APHY_AC_1_RESET_DATAPATH_216_RESET_MASK |
BCHP_MEMC_DDR23_APHY_AC_1_RESET_RD_DATAPATH_RESET_MASK |
BCHP_MEMC_DDR23_APHY_AC_1_RESET_DATAPATH_DDR_RESET_MASK);
mdelay(1);
/* reset the vcxo */
BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_RESET, VCXO_RESET, 1);
mdelay(1);
/* de-assert reset the vcxo */
BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_RESET, VCXO_RESET, 0);
/* de-assert reset the freq divider */
BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_RESET, FREQ_DIV_RESET, 0);
mdelay(1);
/* check for pll lock */
while (!BDEV_RD_F(MEMC_DDR23_APHY_AC_1_DDR_PLL_LOCK_STATUS,
LOCK_STATUS))
;
/* reload shmoo values */
/* set wl0_dq phase */
val = memc1_config.shmoo_value[4];
cur_val = 0;
while (cur_val <= val) {
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH3_WL0_DQ_PHASE_CNTRL,
cur_val);
cur_val++;
}
/* set wl1_dq phase */
val = memc1_config.shmoo_value[5];
cur_val = 0;
while (cur_val <= val) {
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH7_WL1_DQ_PHASE_CNTRL,
cur_val);
cur_val++;
}
/* set ch2 phase */
val = memc1_config.shmoo_value[6];
cur_val = 0;
while (cur_val < val) {
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH2_CLOCK_PHASE_CNTRL,
cur_val);
cur_val++;
}
/* set ch6 phase */
val = memc1_config.shmoo_value[7];
cur_val = 0;
while (cur_val < val) {
BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_DESKEW_DLL_CNTRL,
BYPASS_PHASE, cur_val);
cur_val++;
}
/* set wl0_dqs0 phases */
sval = memc1_config.shmoo_value[0];
scur_val = 0;
inc_val = sval > 0 ? 1 : -1;
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH4_WL0_DQS0_PHASE_CNTRL,
0);
while (sval != scur_val) {
scur_val += inc_val;
BDEV_WR_RB(
BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH4_WL0_DQS0_PHASE_CNTRL,
scur_val);
}
/* set wl0_dqs1 phases */
sval = memc1_config.shmoo_value[1];
scur_val = 0;
inc_val = sval > 0 ? 1 : -1;
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH5_WL0_DQS1_PHASE_CNTRL,
0);
while (sval != scur_val) {
scur_val += inc_val;
BDEV_WR_RB(
BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH5_WL0_DQS1_PHASE_CNTRL,
scur_val);
}
/* set wl1_dqs0 phases */
sval = memc1_config.shmoo_value[2];
scur_val = 0;
inc_val = sval > 0 ? 1 : -1;
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH8_WL1_DQS0_PHASE_CNTRL,
0);
while (sval != scur_val) {
scur_val += inc_val;
BDEV_WR_RB(
BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH8_WL1_DQS0_PHASE_CNTRL,
scur_val);
}
/* set wl1_dqs1 phases */
sval = memc1_config.shmoo_value[3];
scur_val = 0;
inc_val = sval > 0 ? 1 : -1;
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH9_WL1_DQS1_PHASE_CNTRL,
0);
while (sval != scur_val) {
scur_val += inc_val;
BDEV_WR_RB(
BCHP_MEMC_DDR23_APHY_AC_1_PLL_CH9_WL1_DQS1_PHASE_CNTRL,
scur_val);
}
/* reset the word slice dll */
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL0_1_WORD_SLICE_DLL_RESET, 1);
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL1_1_WORD_SLICE_DLL_RESET, 1);
mdelay(1);
/* reset VCDL values */
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL0_1_BYTE0_VCDL_PHASE_CNTL, 0);
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL0_1_BYTE1_VCDL_PHASE_CNTL, 0);
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL1_1_BYTE0_VCDL_PHASE_CNTL, 0);
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL1_1_BYTE1_VCDL_PHASE_CNTL, 0);
/* de-assert reset of the word slice dll */
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL0_1_WORD_SLICE_DLL_RESET, 0);
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL1_1_WORD_SLICE_DLL_RESET, 0);
mdelay(1);
/* de-assert reset from DATAPATH_216_RESET */
BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_RESET, DATAPATH_216_RESET, 0);
/* de-assert reset from RD_DATAPATH_RESET */
BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_RESET, RD_DATAPATH_RESET, 0);
/* de-assert reset from DATAPATH_DDR_RESET */
BDEV_WR_F_RB(MEMC_DDR23_APHY_AC_1_RESET, DATAPATH_DDR_RESET, 0);
mdelay(1);
/*
* Reload VCDL values:
*/
cur_val = 0x0101;
while (cur_val <= memc1_config.vcdl[0]) {
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL0_1_BYTE0_VCDL_PHASE_CNTL,
cur_val);
cur_val += 0x0101;
}
cur_val = 0x0101;
while (cur_val <= memc1_config.vcdl[1]) {
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL0_1_BYTE1_VCDL_PHASE_CNTL,
cur_val);
cur_val += 0x0101;
}
cur_val = 0x0101;
while (cur_val <= memc1_config.vcdl[2]) {
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL1_1_BYTE0_VCDL_PHASE_CNTL,
cur_val);
cur_val += 0x0101;
}
cur_val = 0x0101;
while (cur_val <= memc1_config.vcdl[3]) {
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_WL1_1_BYTE1_VCDL_PHASE_CNTL,
cur_val);
cur_val += 0x0101;
}
if (mode) {
/* Remove CKE_IDDQ */
BDEV_WR_RB(BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL,
BDEV_RD(BCHP_MEMC_DDR23_APHY_AC_1_DDR_PAD_CNTRL) & ~4);
BDEV_WR_F_RB(MEMC_MISC_1_SOFT_RESET,
MEMC_DRAM_INIT, 0);
BDEV_WR_F_RB(MEMC_MISC_1_SOFT_RESET,
MEMC_CORE, 0);
mdelay(1);
printk(KERN_DEBUG "memc1: powered up\n");
} else
printk(KERN_DEBUG "memc1: resumed\n");
}