.divsel_shift = 9, }; static const u8 default_parent_ids[] = { SYSPLL, AVPLL_B4, AVPLL_B5, AVPLL_B6, AVPLL_B7, SYSPLL }; static const struct berlin2_div_data bg2q_divs[] __initconst = { { .name = "sys", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 0), BERLIN2_PLL_SELECT(REG_CLKSELECT0, 0), BERLIN2_DIV_SELECT(REG_CLKSELECT0, 3), BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 3), BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 4), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 5), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = CLK_IGNORE_UNUSED, }, { .name = "drmfigo", .parent_ids = default_parent_ids, .num_parents = ARRAY_SIZE(default_parent_ids), .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 17), BERLIN2_PLL_SELECT(REG_CLKSELECT0, 6), BERLIN2_DIV_SELECT(REG_CLKSELECT0, 9),
static const u8 default_parent_ids[] = { SYSPLL, AVPLL_B4, AVPLL_A5, AVPLL_B6, AVPLL_B7, SYSPLL }; static const struct berlin2_div_data bg2_divs[] __initconst = { { .name = "sys", .parent_ids = (const u8 []){ SYSPLL, AVPLL_B4, AVPLL_B5, AVPLL_B6, AVPLL_B7, SYSPLL }, .num_parents = 6, .map = { BERLIN2_DIV_GATE(REG_CLKENABLE, 0), BERLIN2_PLL_SELECT(REG_CLKSELECT0, 0), BERLIN2_DIV_SELECT(REG_CLKSELECT0, 3), BERLIN2_PLL_SWITCH(REG_CLKSWITCH0, 3), BERLIN2_DIV_SWITCH(REG_CLKSWITCH0, 4), BERLIN2_DIV_D3SWITCH(REG_CLKSWITCH0, 5), }, .div_flags = BERLIN2_DIV_HAS_GATE | BERLIN2_DIV_HAS_MUX, .flags = CLK_IGNORE_UNUSED, }, { .name = "cpu", .parent_ids = (const u8 []){ CPUPLL, MEMPLL, MEMPLL, MEMPLL, MEMPLL }, .num_parents = 5, .map = { BERLIN2_PLL_SELECT(REG_CLKSELECT0, 6),