vc Qbus video subsystem 11-Jun-2013 MB First version */ #include "vax_defs.h" #include "sim_video.h" #include "vax_2681.h" /* CSR - control/status register */ BITFIELD vc_csr_bits[] = { BIT(MOD), /* Monitor size */ #define CSR_V_MDO 0 #define CSR_MOD (1<<CSR_V_MDO) BITNCF(1), /* unused */ BIT(VID), /* Video output en */ #define CSR_V_VID 2 #define CSR_VID (1<<CSR_V_VID) BIT(FNC), /* Cursor function */ #define CSR_V_FNC 3 #define CSR_FNC (1<<CSR_V_FNC) BIT(VRB), /* Video readback en */ #define CSR_V_VRB 4 #define CSR_VRB (1<<CSR_V_VRB) BIT(TST), /* Test bit */ #define CSR_V_TST 5 #define CSR_TST (1<<CSR_V_TST) BIT(IEN), /* Interrupt Enable */ #define CSR_V_IEN 6 #define CSR_IEN (1<<CSR_V_IEN)
#define RXDB_FRM 0x2000 /* framing error */ #define TXCS_RD (CSR_DONE + CSR_IE) /* terminal output */ #define TXCS_WR (CSR_IE) #define TXDB_V_SEL 8 /* unit select */ #define TXDB_M_SEL 0xF #define TXDB_MISC 0xF /* console misc */ #define MISC_MASK 0xFF /* console data mask */ #define MISC_SWDN 0x1 /* software done */ #define MISC_BOOT 0x2 /* reboot */ #define MISC_CLWS 0x3 /* clear warm start */ #define MISC_CLCS 0x4 /* clear cold start */ #define TXDB_SEL (TXDB_M_SEL << TXDB_V_SEL) /* non-terminal */ #define TXDB_GETSEL(x) (((x) >> TXDB_V_SEL) & TXDB_M_SEL) static BITFIELD rx_csr_bits[] = { BITNCF(6), /* unused */ BIT(IE), /* Interrupt Enable */ BIT(DONE), /* Xmit Ready */ BITNCF(8), /* unused */ ENDBITS }; static BITFIELD rx_buf_bits[] = { BITF(DAT,8), /* data buffer */ BITNCF(5), /* unused */ BIT(RBRK), BIT(OVR), BIT(ERR), ENDBITS };
#define TMR_CSR_ERR 0x80000000 /* error W1C */ #define TMR_CSR_DON 0x00000080 /* done W1C */ #define TMR_CSR_IE 0x00000040 /* int enb RW */ #define TMR_CSR_SGL 0x00000020 /* single WO */ #define TMR_CSR_XFR 0x00000010 /* xfer WO */ #define TMR_CSR_RUN 0x00000001 /* run RW */ #define TMR_CSR_RD (TMR_CSR_W1C | TMR_CSR_WR) #define TMR_CSR_W1C (TMR_CSR_ERR | TMR_CSR_DON) #define TMR_CSR_WR (TMR_CSR_IE | TMR_CSR_RUN) #define TMR_INC 10000 /* usec/interval */ #define CLK_DELAY 5000 /* 100 Hz */ #define TMXR_MULT 1 /* 100 Hz */ static BITFIELD tmr_iccs_bits [] = { BIT(RUN), /* Run */ BITNCF(3), /* unused */ BIT(XFR), /* Transfer */ BIT(SGL), /* Single */ BIT(IE), /* Interrupt Enable */ BIT(DON), /* Done */ BITNCF(23), /* unused */ BIT(ERR), /* Error */ ENDBITS }; /* Floppy definitions */ #define FL_NUMTR 77 /* tracks/disk */ #define FL_M_TRACK 0377 #define FL_NUMSC 26 /* sectors/track */ #define FL_M_SECTOR 0177
*/ #include "vax_defs.h" #include <time.h> /* control/status registers */ #define WTC_CSRA_RS 0x0F /* Rate Select Bits (Not Used by VMS) */ #define WTC_CSRA_V_DV 4 #define WTC_CSRA_M_DV 0x7 #define WTC_CSRA_DV (WTC_CSRA_M_DV << WTC_CSRA_V_DV) #define WTC_CSRA_UIP 0x80 /* update in progess (BUSY) */ #define WTC_CSRA_WR (WTC_CSRA_RS | WTC_CSRA_DV) const char *wtc_dv_modes[] = {"4.194304MHz", "1.048576MHz", "32.768KHz", "Any", "Any", "Test-Only", "Test-Only", "Test-Only"}; BITFIELD wtc_csra_bits[] = { BITNCF(4), /* Rate Select - unused MBZ for VMS */ BITFNAM(DV,3,wtc_dv_modes), /* Divider Select */ BIT(UIP), /* Update In Progress */ ENDBITS }; #define WTC_CSRB_DSE 0x01 /* daylight saving en */ #define WTC_CSRB_2412 0x02 /* 24/12hr select (1 -> 24 hr) */ #define WTC_CSRB_DM 0x04 /* data mode (1 -> binary, 0 -> BCD) */ #define WTC_CSRB_SET 0x80 /* set time */ #define WTC_CSRB_PIE 0x40 /* periodic interrupt enable (Not Used by VMS) */ #define WTC_CSRB_AIE 0x20 /* alarm interrupt enable (Not Used by VMS) */ #define WTC_CSRB_UIE 0x10 /* update ended interrupt enable (Not Used by VMS) */ #define WTC_CSRB_SQWE 0x08 /* square wave enable (Not Used by VMS) */ #define WTC_CSRB_WR (WTC_CSRB_DSE | WTC_CSRB_2412 | WTC_CSRB_DM | WTC_CSRB_SET) const char *wtc_dse_modes[] = {"Disabled", "Enabled"};
#define MBA_EXTOFS(x) (((x) >> MBA_V_DEVOFS) & MBA_M_DEVOFS) char *mba_regnames[] = {"CNF", "CR", "SR", "VA", "BC", "DR", "SMR", "CMD"}; /* Massbus configuration register */ #define MBACNF_OF 0x0 #define MBACNF_ADPDN 0x00800000 /* adap pdn - ni */ #define MBACNF_ADPUP 0x00400000 /* adap pup - ni */ #define MBACNF_CODE 0x00000020 #define MBACNF_RD (SBI_FAULTS|MBACNF_W1C) #define MBACNF_W1C 0x00C00000 BITFIELD mba_cnf_bits[] = { BITF(CODE,8), /* Adapter Code */ BITNCF(13), /* 08:20 Reserved */ BIT(OT), /* Over Temperature */ BIT(PU), /* Power Up */ BIT(PD), /* Power Down */ BITNCF(2), /* 24:25 Reserved */ BIT(XMTFLT), /* Transmit Fault */ BIT(MT), /* Multiple Transmitter */ BITNCF(1), /* 28 Reserved */ BIT(URD), /* Unexpected Read Data */ BIT(WS), /* Write Data Sequence (Fault B) */ BIT(PE), /* SBI Parity Error */ ENDBITS }; /* Control register */