static int sys_pwr_domain_suspend(void)
{
sys_slp_config();
plls_suspend();
pmu_sgrf_rst_hld();
mmio_write_32(SGRF_BASE + SGRF_SOC_CON0_1(1),
(PMUSRAM_BASE >> CPU_BOOT_ADDR_ALIGN) |
CPU_BOOT_ADDR_WMASK);
pmu_scu_b_pwrdn();
mmio_write_32(PMU_BASE + PMU_ADB400_CON,
BIT_WITH_WMSK(PMU_PWRDWN_REQ_CORE_B_2GIC_SW) |
BIT_WITH_WMSK(PMU_PWRDWN_REQ_CORE_B_SW) |
BIT_WITH_WMSK(PMU_PWRDWN_REQ_GIC2_CORE_B_SW));
dsb();
mmio_setbits_32(PMU_BASE + PMU_PWRDN_CON, BIT(PMU_SCU_B_PWRDWN_EN));
return 0;
}
static void sys_slp_config(void)
{
uint32_t slp_mode_cfg = 0;
mmio_write_32(PMU_BASE + PMU_CCI500_CON,
BIT_WITH_WMSK(PMU_CLR_PREQ_CCI500_HW) |
BIT_WITH_WMSK(PMU_CLR_QREQ_CCI500_HW) |
BIT_WITH_WMSK(PMU_QGATING_CCI500_CFG));
mmio_write_32(PMU_BASE + PMU_ADB400_CON,
BIT_WITH_WMSK(PMU_CLR_CORE_L_HW) |
BIT_WITH_WMSK(PMU_CLR_CORE_L_2GIC_HW) |
BIT_WITH_WMSK(PMU_CLR_GIC2_CORE_L_HW));
mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1A_IOMUX,
BIT_WITH_WMSK(AP_PWROFF));
slp_mode_cfg = BIT(PMU_PWR_MODE_EN) |
BIT(PMU_POWER_OFF_REQ_CFG) |
BIT(PMU_CPU0_PD_EN) |
BIT(PMU_L2_FLUSH_EN) |
BIT(PMU_L2_IDLE_EN) |
BIT(PMU_SCU_PD_EN);
mmio_setbits_32(PMU_BASE + PMU_WKUP_CFG4, PMU_CLUSTER_L_WKUP_EN);
mmio_setbits_32(PMU_BASE + PMU_WKUP_CFG4, PMU_CLUSTER_B_WKUP_EN);
mmio_clrbits_32(PMU_BASE + PMU_WKUP_CFG4, PMU_GPIO_WKUP_EN);
mmio_write_32(PMU_BASE + PMU_PWRMODE_CON, slp_mode_cfg);
mmio_write_32(PMU_BASE + PMU_STABLE_CNT, CYCL_24M_CNT_MS(5));
mmio_write_32(PMU_BASE + PMU_SCU_L_PWRDN_CNT, CYCL_24M_CNT_MS(2));
mmio_write_32(PMU_BASE + PMU_SCU_L_PWRUP_CNT, CYCL_24M_CNT_MS(2));
mmio_write_32(PMU_BASE + PMU_SCU_B_PWRDN_CNT, CYCL_24M_CNT_MS(2));
mmio_write_32(PMU_BASE + PMU_SCU_B_PWRUP_CNT, CYCL_24M_CNT_MS(2));
}
void set_pmu_rsthold(void)
{
uint32_t rstnhold_cofig0;
uint32_t rstnhold_cofig1;
slp_data.pmucru_rstnhold_con0 = mmio_read_32(PMUCRU_BASE +
PMUCRU_RSTNHOLD_CON0);
slp_data.pmucru_rstnhold_con1 = mmio_read_32(PMUCRU_BASE +
PMUCRU_RSTNHOLD_CON1);
rstnhold_cofig0 = BIT_WITH_WMSK(PRESETN_NOC_PMU_HOLD) |
BIT_WITH_WMSK(PRESETN_INTMEM_PMU_HOLD) |
BIT_WITH_WMSK(HRESETN_CM0S_PMU_HOLD) |
BIT_WITH_WMSK(HRESETN_CM0S_NOC_PMU_HOLD) |
BIT_WITH_WMSK(DRESETN_CM0S_PMU_HOLD) |
BIT_WITH_WMSK(POESETN_CM0S_PMU_HOLD) |
BIT_WITH_WMSK(PRESETN_TIMER_PMU_0_1_HOLD) |
BIT_WITH_WMSK(RESETN_TIMER_PMU_0_HOLD) |
BIT_WITH_WMSK(RESETN_TIMER_PMU_1_HOLD) |
BIT_WITH_WMSK(PRESETN_UART_M0_PMU_HOLD) |
BIT_WITH_WMSK(RESETN_UART_M0_PMU_HOLD) |
BIT_WITH_WMSK(PRESETN_WDT_PMU_HOLD);
rstnhold_cofig1 = BIT_WITH_WMSK(PRESETN_RKPWM_PMU_HOLD) |
BIT_WITH_WMSK(PRESETN_PMUGRF_HOLD) |
BIT_WITH_WMSK(PRESETN_SGRF_HOLD) |
BIT_WITH_WMSK(PRESETN_GPIO0_HOLD) |
BIT_WITH_WMSK(PRESETN_GPIO1_HOLD) |
BIT_WITH_WMSK(PRESETN_CRU_PMU_HOLD) |
BIT_WITH_WMSK(PRESETN_PVTM_PMU_HOLD);
mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON0, rstnhold_cofig0);
mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON1, rstnhold_cofig1);
}