/*
* MD functions for setting the baud rate and control modes.
*/
int
zs_set_speed(struct zs_chanstate *cs, int bps)
{
int tconst, real_bps;
if (bps == 0)
return 0;
#ifdef DIAGNOSTIC
if (cs->cs_brg_clk == 0)
panic("zs_set_speed");
#endif
tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
if (tconst < 0)
return EINVAL;
/* Convert back to make sure we can do it. */
real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
/* XXX - Allow some tolerance here? */
if (real_bps != bps)
return EINVAL;
cs->cs_preg[12] = tconst;
cs->cs_preg[13] = tconst >> 8;
/* Caller will stuff the pending registers. */
return 0;
}
void
zscninit(struct consdev *cn)
{
struct zs_chanstate *cs;
extern const struct cdevsw zstty_cdevsw;
cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), 0);
zs_cons = (uint8_t *)MIPS_PHYS_TO_KSEG1(ZS_BASE) + ZS_CHAN_A; /* XXX */
zs_conschan = cs = &zs_conschan_store;
/* Setup temporary chanstate. */
cs->cs_reg_csr = zs_cons + ZS_CSR;
cs->cs_reg_data = zs_cons + ZS_DATA;
/* Initialize the pending registers. */
memcpy(cs->cs_preg, zs_init_reg, 16);
cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;
cs->cs_preg[12] = BPS_TO_TCONST(PCLK / 16, ZS_DEFSPEED);
cs->cs_preg[13] = 0;
cs->cs_defspeed = ZS_DEFSPEED;
/* Clear the master interrupt enable. */
zs_write_reg(cs, 9, 0);
/* Reset the whole SCC chip. */
zs_write_reg(cs, 9, ZSWR9_HARD_RESET);
/* Copy "pending" to "current" and H/W */
zs_loadchannelregs(cs);
}
static int
zstty_speed(struct zstty_softc *sc, int rate)
{
int tconst;
if (rate == 0)
return (0);
tconst = BPS_TO_TCONST(sc->sc_brg_clk, rate);
if (tconst < 0 || TCONST_TO_BPS(sc->sc_brg_clk, tconst) != rate)
return (-1);
return (tconst);
}
/*
* MD functions for setting the baud rate and control modes.
*/
int
zs_set_speed(struct zs_chanstate *cs, int bps /* bits per second */)
{
int tconst, real_bps;
if (bps == 0)
return (0);
#ifdef DIAGNOSTIC
if (cs->cs_brg_clk == 0)
panic("zs_set_speed");
#endif
tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
if (tconst < 0)
return (EINVAL);
/* Convert back to make sure we can do it. */
real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
#if 0 /* XXX */
/* XXX - Allow some tolerance here? */
if (real_bps != bps)
return (EINVAL);
#else
/*
* Since our PCLK has somewhat strange value,
* we have to allow tolerance here.
*/
if (BPS_TO_TCONST(cs->cs_brg_clk, real_bps) != tconst)
return (EINVAL);
#endif
cs->cs_preg[12] = tconst;
cs->cs_preg[13] = tconst >> 8;
/* Caller will stuff the pending registers. */
return (0);
}
static void
zscninit(struct consdev *cn)
{
struct zs_chanstate *cs;
extern const struct cdevsw zstty_cdevsw;
extern int tty00_is_console;
extern uint32_t sccport0a;
cn->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), 0);
if (tty00_is_console)
cn->cn_pri = CN_REMOTE;
else
cn->cn_pri = CN_NORMAL;
zc_cons = (struct zschan *)sccport0a; /* XXX */
zs_conschan = cs = &zs_conschan_store;
/* Setup temporary chanstate. */
cs->cs_reg_csr = &zc_cons->zc_csr;
cs->cs_reg_data = &zc_cons->zc_data;
/* Initialize the pending registers. */
memcpy(cs->cs_preg, zs_init_reg, 16);
cs->cs_preg[5] |= ZSWR5_DTR | ZSWR5_RTS;
cs->cs_preg[12] = BPS_TO_TCONST(pclk[systype] / 16, 9600); /* XXX */
cs->cs_preg[13] = 0;
cs->cs_defspeed = 9600;
/* Clear the master interrupt enable. */
zs_write_reg(cs, 9, 0);
/* Reset the whole SCC chip. */
zs_write_reg(cs, 9, ZSWR9_HARD_RESET);
/* Copy "pending" to "current" and H/W */
zs_loadchannelregs(cs);
}
int
zs_set_speed(struct zs_chanstate *cs, int bps)
{
int tconst, real_bps;
tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
if (tconst < 0)
return (EINVAL);
/* Convert back to make sure we can do it. */
real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
#if 0
/* XXX - Allow some tolerance here? */
if (real_bps != bps)
return (EINVAL);
#endif
cs->cs_preg[12] = tconst;
cs->cs_preg[13] = tconst >> 8;
return (0);
}
/*
* MD functions for setting the baud rate and control modes.
*/
int
zs_set_speed(struct zs_chanstate *cs, int bps)
{
int tconst, real_bps;
#if 0
while (!(zs_read_csr(cs) & ZSRR0_TX_READY))
{/*nop*/}
#endif
/* Wait for transmit buffer to empty */
if (bps == 0) {
return (0);
}
#ifdef DIAGNOSTIC
if (cs->cs_brg_clk == 0)
panic("zs_set_speed");
#endif
tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
if (tconst < 0)
return (EINVAL);
/* Convert back to make sure we can do it. */
real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
/* XXX - Allow some tolerance here? */
#if 0
if (real_bps != bps)
return (EINVAL);
#endif
cs->cs_preg[12] = tconst;
cs->cs_preg[13] = tconst >> 8;
/* Caller will stuff the pending registers. */
return (0);
}
} __attribute__((__packed__));
static uint8_t zs_init_reg[16] = {
0, /* 0: CMD (reset, etc.) */
0, /* 1: No interrupts yet. */
0, /* 2: IVECT EWS-UX don't set this. */
ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP,
ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
0, /* 6: TXSYNC/SYNCLO */
0, /* 7: RXSYNC/SYNCHI */
0, /* 8: alias for data port */
ZSWR9_MASTER_IE,
0, /* 10: Misc. TX/RX control bits */
ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
BPS_TO_TCONST((PCLK/16), ZS_DEFSPEED), /* 12: BAUDLO (default=9600) */
0, /*13: BAUDHI (default=9600) */
ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
ZSWR15_BREAK_IE,
};
static int zs_sbdio_match(device_t, cfdata_t, void *);
static void zs_sbdio_attach(device_t, device_t, void *);
CFATTACH_DECL_NEW(zsc_sbdio, sizeof(struct zsc_softc),
zs_sbdio_match, zs_sbdio_attach, NULL, NULL);
int
zs_sbdio_match(device_t parent, cfdata_t cf, void *aux)
{
struct sbdio_attach_args *sa = aux;
static int zs_defspeed = ZS_DEFSPEED;
static uint8_t zs_init_reg[16] = {
0, /* 0: CMD (reset, etc.) */
0, /* 1: No interrupts yet. */
0, /* 2: no IVECT */
ZSWR3_RX_8 | ZSWR3_RX_ENABLE, /* 3: RX params and ctrl */
ZSWR4_CLK_X16 | ZSWR4_ONESB, /* 4: TX/RX misc params */
ZSWR5_TX_8 | ZSWR5_TX_ENABLE, /* 5: TX params and ctrl */
0, /* 6: TXSYNC/SYNCLO */
0, /* 7: RXSYNC/SYNCHI */
0, /* 8: alias for data port */
ZSWR9_MASTER_IE, /* 9: Master interrupt ctrl */
0, /*10: Misc TX/RX ctrl */
ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, /*11: Clock Mode ctrl */
BPS_TO_TCONST((PCLK/16), ZS_DEFSPEED), /*12: BAUDLO */
0, /*13: BAUDHI */
ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, /*14: Misc ctrl */
ZSWR15_BREAK_IE, /*15: Ext/Status intr ctrl */
};
/* register address offset for each channel */
static const int chanoff[] = { ZS_CHAN_A, ZS_CHAN_B };
static int
zs_match(device_t parent, cfdata_t cf, void *aux)
{
static int matched;
/* only one zs */
static struct zschan *zc_cons;
static uint8_t zs_init_reg[16] = {
0, /* 0: CMD (reset, etc.) */
0, /* 1: No interrupts yet. */
ZS_IVECT, /* IVECT */
ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
ZSWR4_CLK_X16 | ZSWR4_ONESB | ZSWR4_EVENP,
ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
0, /* 6: TXSYNC/SYNCLO */
0, /* 7: RXSYNC/SYNCHI */
0, /* 8: alias for data port */
ZSWR9_MASTER_IE,
0, /*10: Misc. TX/RX control bits */
ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
BPS_TO_TCONST((PCLK0/16), 9600), /*12: BAUDLO (default=9600) */
0, /*13: BAUDHI (default=9600) */
ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
ZSWR15_BREAK_IE,
};
/****************************************************************
* Autoconfig
****************************************************************/
/* Definition of the driver for autoconfig. */
static int zs_match(device_t, cfdata_t, void *);
static void zs_attach(device_t, device_t, void *);
static int zs_print(void *, const char *name);