void
vBSP430platformSpinForJumper_ni (void)
{
const unsigned char led_bits = BIT1 | BIT2 | BIT3 | BIT4 | BIT5;
/* P7.7 input configured with pullup */
P7DIR &= ~BIT7;
P7REN |= BIT7;
P7OUT |= BIT7;
/* Flash LEDs alternately while waiting */
#if BSP430_LED
vBSP430ledInitialize_ni();
#else /* BSP430_LED */
P1DIR |= led_bits;
P1SEL &= ~led_bits;
#endif /* BSP430_LED */
P1OUT &= ~(BIT2 | BIT4);
P1OUT |= BIT1 | BIT3 | BIT5;
while (! (P7IN & BIT7)) {
BSP430_CORE_WATCHDOG_CLEAR();
BSP430_CORE_DELAY_CYCLES(BSP430_CLOCK_NOMINAL_MCLK_HZ / 10);
P1OUT ^= led_bits;
}
/* Restore P1.0 and LEDs */
P1OUT &= ~led_bits;
P7OUT &= ~BIT7;
P7DIR |= BIT7;
P7REN &= ~BIT7;
}
int
readBQ27510 (hBSP430halSERIAL i2c,
uint8_t address,
int count,
uint16_t * dest)
{
int rc;
uint16_t u16;
uint8_t * bp = (uint8_t *)dest;
uint16_t * dp = dest;
const uint16_t * const dpe = dp + count;
if (0 >= count) {
return -1;
}
rc = iBSP430i2cTxData_rh(i2c, &address, sizeof(address));
if (sizeof(address) != rc) {
return -2;
}
BSP430_CORE_DELAY_CYCLES(BSP430_CORE_US_TO_TICKS(66, BSP430_CLOCK_NOMINAL_MCLK_HZ));
rc = iBSP430i2cRxData_rh(i2c, bp, count * sizeof(*dest));
if (count * sizeof(*dest) != rc) {
return -3;
}
while (dp != dpe) {
u16 = bp[0] | (bp[1] << 8);
*dp++ = u16;
bp += 2;
}
return count;
}
int
iBSP430clockConfigureLFXT1_ni (int enablep,
int loop_limit)
{
int loop_delta;
int rc = 0;
BSP430_CLOCK_CLEAR_FAULTS_NI();
if (enablep && (0 != loop_limit)) {
rc = iBSP430platformConfigurePeripheralPins_ni(BSP430_PERIPH_LFXT1, 0, 1);
if (0 == rc) {
loop_delta = (0 < loop_limit) ? 1 : 0;
FLL_CTL0 = (FLL_CTL0 & ~(OSCCAP0 | OSCCAP1 | XTS_FLL)) | BSP430_CLOCK_LFXT1_XCAP;
do {
BSP430_CLOCK_CLEAR_FAULTS_NI();
loop_limit -= loop_delta;
BSP430_CORE_WATCHDOG_CLEAR();
BSP430_CORE_DELAY_CYCLES(BSP430_CLOCK_LFXT1_STABILIZATION_DELAY_CYCLES);
} while (BSP430_FLLPLUS_LFXT1_IS_FAULTED_NI() && (0 != loop_limit));
rc = ! BSP430_FLLPLUS_LFXT1_IS_FAULTED_NI();
}
}
BSP430_CLOCK_OSC_CLEAR_FAULT_NI();
if (! rc) {
(void)iBSP430platformConfigurePeripheralPins_ni(BSP430_PERIPH_LFXT1, 0, 0);
FLL_CTL0 &= ~(OSCCAP0 | OSCCAP1);
}
return rc;
}
int
iBSP430clockConfigureLFXT1_ni (int enablep,
int loop_limit)
{
int loop_delta;
int rc = 0;
BSP430_CLOCK_CLEAR_FAULTS_NI();
if (enablep && (0 != loop_limit)) {
rc = iBSP430platformConfigurePeripheralPins_ni(BSP430_PERIPH_LFXT1, 0, 1);
if (0 == rc) {
loop_delta = (0 < loop_limit) ? 1 : 0;
/* See whether the crystal is populated and functional. Do
* this with the DCO reset to the power-up configuration,
* where clock should be nominal 1 MHz.
*
* @TODO: Preserve XT2 configuration */
BCSCTL3 = BSP430_CLOCK_LFXT1_XCAP;
do {
loop_limit -= loop_delta;
BSP430_CORE_WATCHDOG_CLEAR();
BSP430_CORE_DELAY_CYCLES(BSP430_CLOCK_LFXT1_STABILIZATION_DELAY_CYCLES);
} while ((BSP430_BC2_LFXT1_IS_FAULTED_NI()) && (0 != loop_limit));
rc = ! BSP430_BC2_LFXT1_IS_FAULTED_NI();
}
}
BSP430_CLOCK_OSC_CLEAR_FAULT_NI();
if (! rc) {
(void)iBSP430platformConfigurePeripheralPins_ni(BSP430_PERIPH_LFXT1, 0, 0);
/* Explicitly fall back to VLOCLK and disable capacitors */
BCSCTL3 = LFXT1S_2;
}
return rc;
}
void
vBSP430platformSpinForJumper_ni (void)
{
/* P1.2 input with pullup */
P1SEL &= ~BIT2;
P1DIR &= ~BIT2;
P1REN |= BIT2;
P1OUT |= BIT2;
#if BSP430_LED
vBSP430ledInitialize_ni();
#else /* BSP430_LED */
P1DIR |= (BIT0 | BIT1);
P1SEL &= ~(BIT0 | BIT1);
#endif /* BSP430_LED */
P1OUT |= BIT0;
while (! (P1IN & BIT2)) {
BSP430_CORE_WATCHDOG_CLEAR();
BSP430_CORE_DELAY_CYCLES(BSP430_CLOCK_NOMINAL_MCLK_HZ / 10);
P1OUT ^= BIT0 | BIT1;
}
/* Restore P1.2 */
P1OUT &= ~(BIT0 | BIT1 | BIT2);
P1DIR |= BIT2;
P1REN &= ~BIT2;
}
unsigned long
ulBSP430clockConfigureMCLK_ni (unsigned long mclk_Hz)
{
unsigned int flld = 0;
unsigned int fn_x = 0;
int dcoplus = 0;
unsigned int dcoclk_xt1 = (mclk_Hz + BSP430_CLOCK_NOMINAL_XT1CLK_HZ / 2) / BSP430_CLOCK_NOMINAL_XT1CLK_HZ;
/* Convert a value in MHz to the same value in ticks of LXFT1 */
#define MHZ_TO_XT1(_n) (((_n)*1000000UL) / BSP430_CLOCK_NOMINAL_XT1CLK_HZ)
/* Gross selection of DCO range. We select the range if the target
* frequency is above the midpoint of the previous range. */
if (MHZ_TO_XT1(26/2) < dcoclk_xt1) {
fn_x = FN_8;
} else if (MHZ_TO_XT1(17/2) < dcoclk_xt1) {
fn_x = FN_4;
} else if (MHZ_TO_XT1(12/2) < dcoclk_xt1) {
fn_x = FN_3;
} else if (MHZ_TO_XT1(6/2) < dcoclk_xt1) {
fn_x = FN_2;
}
#undef MHZ_TO_XT1
/* Need a divider if multiplier is too large. */
while (FLL_N_MASK < (dcoclk_xt1 - 1)) {
dcoplus = 1;
++flld;
dcoclk_xt1 /= 2;
}
(void)iBSP430clockConfigureLFXT1_ni(1, -1);
if (dcoplus) {
FLL_CTL0 |= DCOPLUS;
}
SCFQCTL = dcoclk_xt1 - 1;
SCFI0 = (flld * FLLD0) | fn_x;
/* Clear all the oscillator faults and spin until DCO stabilized. */
do {
BSP430_CLOCK_CLEAR_FAULTS_NI();
BSP430_CORE_WATCHDOG_CLEAR();
/* Conservatively assume a 32 MHz clock */
BSP430_CORE_DELAY_CYCLES(32 * BSP430_CLOCK_FAULT_RECHECK_DELAY_US);
} while (BSP430_FLLPLUS_DCO_IS_FAULTED_NI());
return ulBSP430clockMCLK_Hz_ni();
}
void main ()
{
sBSP430halPORT * hh10d_port = hBSP430portLookup(APP_HH10D_PORT_PERIPH_HANDLE);
hBSP430halSERIAL i2c = hBSP430serialLookup(APP_HH10D_I2C_PERIPH_HANDLE);
int uptime_Hz;
int hh10d_offs;
int hh10d_sens;
vBSP430platformInitialize_ni();
(void)iBSP430consoleInitialize();
cprintf("\nApplication starting\n");
BSP430_CORE_DELAY_CYCLES(10000);
if (NULL == hh10d_port) {
cprintf("\nERROR: No port HAL; did you enable configBSP430_HAL_%s?\n", xBSP430portName(APP_HH10D_PORT_PERIPH_HANDLE) ?: "whatever");
return;
}
void main ()
{
const sColor * cp = colors;
const sColor * const ecp = colors + sizeof(colors) / sizeof(*colors);
vBSP430platformInitialize_ni();
(void)iBSP430consoleInitialize();
while (1) {
if (0 > cp->idx) {
cprintf("%s is not available\n", cp->name);
} else {
vBSP430ledSet(cp->idx, 1);
cprintf("%s lit; mask 0x%x\n", cp->name, read_leds());
BSP430_CORE_DELAY_CYCLES(5 * BSP430_CLOCK_NOMINAL_MCLK_HZ);
vBSP430ledSet(cp->idx, 0);
}
if (++cp == ecp) {
cp = colors;
}
}
}
int
iBSP430clockConfigureLFXT1_ni (int enablep,
int loop_limit)
{
int loop_delta;
int rc = 0;
BSP430_CLOCK_CLEAR_FAULTS_NI();
if (enablep && (0 != loop_limit)) {
rc = iBSP430platformConfigurePeripheralPins_ni(BSP430_PERIPH_LFXT1, 0, 1);
if (0 == rc) {
loop_delta = (0 < loop_limit) ? 1 : 0;
/* Low frequency XT1 needed. Spin at high drive to stability, then
* drop back. */
CSCTL6 = XT1DRIVE_3 | (CSCTL6 & ~(XTS | XT1BYPASS | XT1AGCOFF | XT1AUTOOFF));
do {
BSP430_CLOCK_CLEAR_FAULTS_NI();
loop_limit -= loop_delta;
BSP430_CORE_WATCHDOG_CLEAR();
BSP430_CORE_DELAY_CYCLES(BSP430_CLOCK_LFXT1_STABILIZATION_DELAY_CYCLES);
} while ((BSP430_CS4_LFXT1_IS_FAULTED_NI()) && (0 != loop_limit));
rc = ! BSP430_CS4_LFXT1_IS_FAULTED_NI();
}
}
BSP430_CLOCK_OSC_CLEAR_FAULT_NI();
CSCTL6 &= ~XT1DRIVE_3;
if (! rc) {
(void)iBSP430platformConfigurePeripheralPins_ni(BSP430_PERIPH_LFXT1, 0, 0);
/* Disable as an indication that XIN is not enabled. Also remove
* capacitance setting. */
CSCTL6 = XT1BYPASS | (CSCTL6 & ~(XT1DRIVE0 | XT1DRIVE1));
}
return rc;
}
void main ()
{
int rc = 0;
/* GDO0 and GDO2 are always interrupt-capable. */
volatile sBSP430hplPORTIE * gdo0 = xBSP430hplLookupPORTIE(BSP430_RF_CC110X_GDO0_PORT_PERIPH_HANDLE);
volatile sBSP430hplPORTIE * gdo2 = xBSP430hplLookupPORTIE(BSP430_RF_CC110X_GDO2_PORT_PERIPH_HANDLE);
hBSP430halPORT hgdo1 = hBSP430portLookup(BSP430_RF_CC110X_GDO1_PORT_PERIPH_HANDLE);
hBSP430halPORT hcsn = hBSP430portLookup(BSP430_RF_CC110X_CSn_PORT_PERIPH_HANDLE);
spi = hBSP430serialLookup(BSP430_RF_CC110X_SPI_PERIPH_HANDLE);
vBSP430platformInitialize_ni();
(void)iBSP430consoleInitialize();
cprintf("\nccid " __DATE__ " " __TIME__ "\n");
cprintf("GDO0 %p at %s.%u\n", gdo0, xBSP430portName(BSP430_RF_CC110X_GDO0_PORT_PERIPH_HANDLE), iBSP430portBitPosition(BSP430_RF_CC110X_GDO0_PORT_BIT));
cprintf("GDO1 HAL %p HPL %p at %s.%u\n", hgdo1, hgdo1->hpl.any, xBSP430portName(BSP430_RF_CC110X_GDO1_PORT_PERIPH_HANDLE), iBSP430portBitPosition(BSP430_RF_CC110X_GDO1_PORT_BIT));
cprintf("GDO2 %p at %s.%u\n", gdo2, xBSP430portName(BSP430_RF_CC110X_GDO2_PORT_PERIPH_HANDLE), iBSP430portBitPosition(BSP430_RF_CC110X_GDO2_PORT_BIT));
cprintf("CSn HAL %p HPL %p at %s.%u\n", hcsn, hcsn->hpl.any, xBSP430portName(BSP430_RF_CC110X_CSn_PORT_PERIPH_HANDLE), iBSP430portBitPosition(BSP430_RF_CC110X_CSn_PORT_BIT));
cprintf("SPI %p is %s\n", spi, xBSP430serialName(BSP430_RF_CC110X_SPI_PERIPH_HANDLE));
#if BSP430_PLATFORM_PERIPHERAL_HELP
cprintf("SPI Pins: %s\n", xBSP430platformPeripheralHelp(BSP430_RF_CC110X_SPI_PERIPH_HANDLE, BSP430_PERIPHCFG_SERIAL_SPI3));
#endif /* BSP430_PLATFORM_PERIPHERAL_HELP */
cprintf(__DATE__ " " __TIME__ "\n");
/* Configure the SPI interface, but immediately put it into hold
* mode so we can check CHIP_RDYn on the MISO/GDO1 input. */
spi = hBSP430serialOpenSPI(spi, BSP430_RF_CC110X_SPI_CTL0_BYTE, 0, 0);
if (spi) {
rc = iBSP430serialSetHold_rh(spi, 1);
/* GDO1 to input, pull-up */
BSP430_PORT_HAL_HPL_DIR(hgdo1) &= ~BSP430_RF_CC110X_GDO1_PORT_BIT;
BSP430_PORT_HAL_SET_REN(hgdo1, BSP430_RF_CC110X_GDO1_PORT_BIT, BSP430_PORT_REN_PULL_UP);
}
cprintf("SPI device %p hold returned %d\n", spi, rc);
if (! spi) {
return;
}
/* Configure CSn initial high to ensure we have a falling edge when
* we first enable the radio. */
BSP430_PORT_HAL_HPL_SEL(hcsn) &= ~BSP430_RF_CC110X_CSn_PORT_BIT;
BSP430_PORT_HAL_HPL_OUT(hcsn) |= BSP430_RF_CC110X_CSn_PORT_BIT;
BSP430_PORT_HAL_HPL_DIR(hcsn) |= BSP430_RF_CC110X_CSn_PORT_BIT;
/* Now enable the radio */
BSP430_PORT_HAL_HPL_OUT(hcsn) &= ~BSP430_RF_CC110X_CSn_PORT_BIT;
/* Spin until GDO1 (CHP_RDYn) is clear indicating radio is responsive */
while (BSP430_PORT_HAL_HPL_IN(hgdo1) & BSP430_RF_CC110X_GDO1_PORT_BIT) {
cprintf("Waiting for radio ready\n");
BSP430_CORE_DELAY_CYCLES(BSP430_CLOCK_NOMINAL_MCLK_HZ);
}
/* Enable SPI */
rc = iBSP430serialSetHold_rh(spi, 0);
cprintf("Radio is up, hold release %d; sending SRES strobe\n", rc);
/* Send a reset */
do {
rc = sendStrobe(0x30);
cprintf("Strobe response %#02x\n", rc);
if (0x0F != rc) {
BSP430_CORE_DELAY_CYCLES(BSP430_CLOCK_NOMINAL_MCLK_HZ);
}
} while (0x0F != rc);
cprintf("PARTNUM response %#02x\n", readRegister(0x30));
cprintf("VERSION response %#02x\n", readRegister(0x31));
cprintf("IOCFG2 read %#02x\n", readRegister(0x00));
cprintf("IOCFG1 read %#02x\n", readRegister(0x01));
cprintf("IOCFG0 read %#02x\n", readRegister(0x02));
/* ChipCon radios consume 1.4mA when idle. That goes down to
* nominally 400 nA if the GDOs are configured to "HW to 0" and the
* chip is told to power-down on loss of CSn. On the EXP430F5438
* the RF PWR header indicates that a CC1101 is using 40 nA in this
* mode.*/
rc = writeRegister(0x00, 0x2f);
rc = writeRegister(0x01, 0x2f);
rc = writeRegister(0x02, 0x2f);
cprintf("Cleared IOCFG\n");
cprintf("IOCFG2 read %#02x\n", readRegister(0x00));
cprintf("IOCFG1 read %#02x\n", readRegister(0x01));
cprintf("IOCFG0 read %#02x\n", readRegister(0x02));
/* SPWD */
rc = sendStrobe(0x39);
cprintf("SPWD got %d\n", rc);
/* Disable SPI before removing CSn otherwise the sequence isn't
* right. */
rc = iBSP430serialSetHold_rh(spi, 1);
BSP430_PORT_HAL_HPL_OUT(hcsn) |= BSP430_RF_CC110X_CSn_PORT_BIT;
/* This gets the RF2500T power down to about 120 nA. Note:
* Purposefully enter LPM with #GIE off since we do not intend to
* wake up.*/
BSP430_CORE_LPM_ENTER(LPM3_bits);
}
void main ()
{
sBSP430halPORT * port_hal;
hBSP430halTIMER hal;
volatile sBSP430hplTIMER * hpl;
vBSP430platformInitialize_ni();
(void)iBSP430consoleInitialize();
cputchar('\n');
BSP430_CORE_DELAY_CYCLES(BSP430_CLOCK_NOMINAL_MCLK_HZ / 1000);
cprintf("\n\nsynccap " __DATE__ " " __TIME__ "\n");
cprintf("External input on %s.%u corresponds to %s.%u%c\n",
xBSP430portName(BSP430_TIMER_CCACLK_CC1_PORT_PERIPH_HANDLE),
bitToPin(BSP430_TIMER_CCACLK_CC1_PORT_BIT),
xBSP430timerName(BSP430_TIMER_CCACLK_PERIPH_HANDLE),
PORT_CCIDX,
'A' + (BSP430_TIMER_CCACLK_CC1_CCIS / CCIS0));
port_hal = hBSP430portLookup(BSP430_TIMER_CCACLK_CC1_PORT_PERIPH_HANDLE);
if (NULL == port_hal) {
cprintf("Port HAL not available\n");
return;
}
hal = hBSP430timerLookup(BSP430_TIMER_CCACLK_PERIPH_HANDLE);
if (NULL == hal) {
cprintf("Can't find timer\n");
return;
}
BSP430_PORT_HAL_HPL_DIR(port_hal) &= ~BSP430_TIMER_CCACLK_CC1_PORT_BIT;
BSP430_PORT_HAL_HPL_SEL(port_hal) |= BSP430_TIMER_CCACLK_CC1_PORT_BIT;
hpl = hal->hpl;
hpl->cctl[1] = CM_3 | BSP430_TIMER_CCACLK_CC1_CCIS | SCS | CAP | CCIE;
captured.last_cci = !!(hpl->cctl[1] & CCI);
BSP430_HAL_ISR_CALLBACK_LINK_NI(sBSP430halISRIndexedChainNode,
hal->cc_cbchain_ni[PORT_CCIDX],
captured.cb,
next_ni);
hpl->ctl = TASSEL_2 | MC_2 | TACLR | TAIE;
/* Need to enable interrupts so timer overflow events are properly
* acknowledged */
while (1) {
unsigned int ccr;
unsigned int cctl;
unsigned int count;
unsigned int errors;
int last_cci;
unsigned long event_tt;
BSP430_CORE_DISABLE_INTERRUPT();
do {
event_tt = captured.event_tt;
captured.event_tt = 0;
count = captured.count;
errors = captured.errors;
captured.count = 0;
captured.errors = 0;
last_cci = captured.last_cci;
cctl = hpl->cctl[PORT_CCIDX];
ccr = hpl->ccr[PORT_CCIDX];
hpl->cctl[PORT_CCIDX] &= ~COV;
} while (0);
BSP430_CORE_ENABLE_INTERRUPT();
cprintf("Up %lu ACLK ticks, timer %lu event %lx ccr %x cctl %04x\n"
"\tCCI %d SCCI %d COV %d ; recorded CCI %d ; count %u errors %d\n",
ulBSP430uptime(),
ulBSP430timerCounter(hal, NULL),
event_tt,
ccr,
cctl,
!!(cctl & CCI), !!(cctl & SCCI), !!(cctl & COV), last_cci, count, errors);
BSP430_CORE_DELAY_CYCLES(BSP430_CLOCK_NOMINAL_MCLK_HZ);
}
}
unsigned long
ulBSP430clockConfigureMCLK_ni (unsigned long mclk_Hz)
{
unsigned char dcoctl;
unsigned char bcsctl1;
unsigned long error_Hz;
int use_trim_to_mclk = 1;
long freq_Hz;
if (0 == mclk_Hz) {
mclk_Hz = BSP430_CLOCK_PUC_MCLK_HZ;
use_trim_to_mclk = 0;
}
/* Power-up defaults */
dcoctl = 0x60;
bcsctl1 = 0x87;
freq_Hz = BSP430_CLOCK_PUC_MCLK_HZ;
/* Calculate absolute error from _freq_Hz to target */
#define ERROR_HZ(_freq_Hz) ((mclk_Hz < _freq_Hz) ? (_freq_Hz - mclk_Hz) : (mclk_Hz - _freq_Hz))
error_Hz = ERROR_HZ(freq_Hz);
(void)error_Hz;
/* Test a candidate to see if it's better than what we've got now */
#define TRY_FREQ(_tag, _cand_Hz) do { \
unsigned long cand_error_Hz = ERROR_HZ(_cand_Hz); \
if (cand_error_Hz < error_Hz) { \
dcoctl = CALDCO_##_tag; \
bcsctl1 = CALBC1_##_tag; \
freq_Hz = _cand_Hz; \
error_Hz = cand_error_Hz; \
} \
} while (0)
/* Candidate availability is MCU-specific and can be determined by
* checking for a corresponding preprocessor definition */
#if defined(CALDCO_1MHZ_)
TRY_FREQ(1MHZ, 1000000UL);
#endif /* CALDCO_1MHZ */
#if defined(CALDCO_8MHZ_)
TRY_FREQ(8MHZ, 8000000UL);
#endif /* CALDCO_8MHZ */
#if defined(CALDCO_12MHZ_)
TRY_FREQ(12MHZ, 12000000UL);
#endif /* CALDCO_12MHZ */
#if defined(CALDCO_16MHZ_)
TRY_FREQ(16MHZ, 16000000UL);
#endif /* CALDCO_16MHZ */
#undef TRY_FREQ
#undef ERROR_HZ
/* Clearing DCO bits first supports workaround for erratum BCL12 */
DCOCTL = 0;
BCSCTL1 = bcsctl1;
DCOCTL = dcoctl;
/* SELM = DCOCLK; DIVM = /1 */
BCSCTL2 &= ~(SELM_MASK | DIVM_MASK);
configuredMCLK_Hz = freq_Hz;
if (use_trim_to_mclk) {
#if BSP430_BC2_TRIM_TO_MCLK - 0
(void)iBSP430bc2TrimToMCLK_ni(mclk_Hz);
#endif /* BSP430_BC2_TRIM_TO_MCLK */
}
/* Spin until DCO faults cleared */
do {
BSP430_CLOCK_CLEAR_FAULTS_NI();
BSP430_CORE_WATCHDOG_CLEAR();
/* Conservatively assume a 32 MHz clock */
BSP430_CORE_DELAY_CYCLES(32 * BSP430_CLOCK_FAULT_RECHECK_DELAY_US);
} while (BSP430_CLOCK_OSC_IS_FAULTED_NI());
return configuredMCLK_Hz;
}
void main ()
{
hBSP430halSERIAL i2c = hBSP430serialLookup(APP_TMP102_I2C_PERIPH_HANDLE);
uint8_t pr = 0;
vBSP430platformInitialize_ni();
(void)iBSP430consoleInitialize();
cprintf("I2C interface on %s is %p\n", xBSP430serialName(APP_TMP102_I2C_PERIPH_HANDLE), i2c);
#if BSP430_PLATFORM_PERIPHERAL_HELP
cprintf("TMP102 I2C Pins: %s\n", xBSP430platformPeripheralHelp(APP_TMP102_I2C_PERIPH_HANDLE, BSP430_PERIPHCFG_SERIAL_I2C));
#endif /* BSP430_PLATFORM_PERIPHERAL_HELP */
i2c = hBSP430serialOpenI2C(i2c,
BSP430_SERIAL_ADJUST_CTL0_INITIALIZER(UCMST),
0, 0);
if (! i2c) {
cprintf("I2C open failed.\n");
return;
}
(void)iBSP430i2cSetAddresses_ni(i2c, -1, APP_TMP102_I2C_ADDRESS);
/** Raw number is a 16 bit value. First 12 bits represent the
* temperature as a count of 0.0625C values. (If the LSB is 1, then
* an extended temperature is used and the 13th bit represents a
* half count.) 0.625 = 5/8; shifting by 3 gets us the 13-bit
* value; dividing by 2 accounts for the half-count in extended
* temperature mode. */
#define TMP102_RAW_TO_dC_(raw_) (5 * ((raw_) >> 3) / 16)
#define TMP102_RAW_TO_dC(raw_) ((0 <= (int)(raw_)) ? TMP102_RAW_TO_dC_(raw_) : -TMP102_RAW_TO_dC_(-(int)(raw_)))
#define dC_TO_dF(dC_) (320 + 9 * (dC_) / 5)
#if 0
{
unsigned int data[] = { 0x7FF0, 0x4B00, 0x1900, 0xFFC0, 0xE700, 0xC908 };
int i;
for (i = 0; i < sizeof(data)/sizeof(*data); ++i) {
int temp_dC = TMP102_RAW_TO_dC(data[i]);
cprintf("temp 0x%04x = %d dC = %d d[degF]\n", data[i], temp_dC, dC_TO_dF(temp_dC));
}
}
#endif
while (1) {
int rc;
uint8_t data[2];
uint16_t raw;
rc = iBSP430i2cTxData_ni(i2c, &pr, 1);
if (0 > rc) {
cprintf("I2C TX ERROR\n");
break;
}
memset(data, 0, sizeof(data));
rc = iBSP430i2cRxData_ni(i2c, data, sizeof(data));
if (0 > rc) {
cprintf("I2C RX ERROR\n");
break;
}
raw = data[1] | (data[0] << 8);
if (0 == pr) {
int temp_dC = TMP102_RAW_TO_dC(raw);
cprintf("temp 0x%04x = %d dC = %d d[degF]\n", raw, temp_dC, dC_TO_dF(temp_dC));
} else {
cprintf("reg %d is 0x%04x\n", pr, raw);
}
pr = (pr + 1) & 0x03;
BSP430_CORE_DELAY_CYCLES(BSP430_CLOCK_NOMINAL_MCLK_HZ);
}
}
int initializeADC (void)
{
cal_adc = NULL;
if (BSP430_TLV_TABLE_IS_VALID()) {
const sBSP430tlvEntry * ep = (const sBSP430tlvEntry *)TLV_START;
const sBSP430tlvEntry * const epe = (const sBSP430tlvEntry *)(TLV_END+1);
while (ep < epe) {
if (BSP430_TLV_ENTRY_IS_ADC(ep)) {
cal_adc = (cal_adc_ptr_type)ep;
}
#if HAVE_REF
if (TLV_REFCAL == ep->tag) {
cal_ref = (const sBSP430tlvREFCAL *)ep;
}
#endif /* HAVE_REF */
ep = BSP430_TLV_NEXT_ENTRY(ep);
}
}
#if HAVE_REF
while (REFCTL0 & REFGENBUSY) {
;
}
REFCTL0 = REFVSEL_1 | REFON
#ifdef REFMSTR
/* REFMSTR is implicit (and not defined) in FR57xx/FR58xx
* devices, required on ADC10_A devices, and optional for
* ADC12_A (but if not selected you have to control the
* reference voltage from the legacy ADC12 settings). Use
* it if you've got it. */
| REFMSTR
#endif /* REFMSTR */
;
#else /* HAVE_REF */
#if defined(__MSP430_HAS_REF_B4__)
PMMCTL0_H = PMMPW_H;
PMMCTL2 |= INTREFEN | TSENSOREN;
PMMCTL0_H = !PMMPW_H;
#endif /* REF_B4 */
#endif /* HAVE_REF */
#if defined(__MSP430_HAS_ADC10__)
ADC10CTL0 = 0;
ADC10CTL0 = SREF_1 | ADC10SHT_3 | REFON | ADC10ON;
ADC10CTL1 = ADC10DIV_3;
#elif defined(__MSP430_HAS_ADC10_A__)
#error Not implemented
#elif defined(__MSP430_HAS_ADC10_B__) || defined(__MSP430_HAS_ADC10_B4__)
ADC10CTL0 = 0;
ADC10CTL0 = ADC10SHT_3 | ADC10ON;
ADC10CTL1 = ADC10SHS_0 | ADC10SHP | ADC10DIV_3 | ADC10SSEL_0;
ADC10CTL2 = ADC10PDIV_0 | ADC10RES | ADC10SR;
#elif defined(__MSP430_HAS_ADC12__)
/* Original ADC12 does not use namespaced prefixes */
/* ~ADC12ENC: Place module into hold before modifying configuration */
ADC12CTL0 &= ~ADC12ENC;
/* ADC12SHT_10: 512 ADC12CLK cycles per sample
* REFON: Enable internal reference
* ADC12ON: Turn module on
* Do not enable yet.
*/
ADC12CTL0 = SHT0_10 | REFON | ADC12ON;
/* Start collection with conversion register zero
* ADC12SHS_0: Trigger on ADC12SC bit
* ADC12SHP: Pulsed sampling
* No sample-input signal inversion
* Divide clock by 1
* ADC12SSEL_0: Clock source is MODCLK (nominal 5MHz)
* ADC12CONSEQ_0: Single-channel, single-conversion
*/
ADC12CTL1 = SHS_0 | SHP | ADC12SSEL_0 | CONSEQ_0;
/* Delay 17ms to allow REF to stabilize */
BSP430_UPTIME_DELAY_MS(17, LPM0_bits, 0);
#elif defined(__MSP430_HAS_ADC12_PLUS__)
/* ~ADC12ENC: Place module into hold before modifying configuration */
ADC12CTL0 &= ~ADC12ENC;
/* ADC12SHT_10: 512 ADC12CLK cycles per sample
* ADC12ON: Turn module on
* Do not enable yet.
*/
ADC12CTL0 = ADC12SHT0_10 | ADC12ON;
/* Start collection with conversion register zero
* ADC12SHS_0: Trigger on ADC12SC bit
* ADC12SHP: Pulsed sampling
* No sample-input signal inversion
* Divide clock by 1
* ADC12SSEL_0: Clock source is MODCLK (nominal 5MHz)
* ADC12CONSEQ_0: Single-channel, single-conversion
*/
ADC12CTL1 = ADC12SHS_0 | ADC12SHP | ADC12SSEL_0 | ADC12CONSEQ_0;
/* No predivider
* ADC12RES: 12-bit resolution
* Binary unsigned read-back
* ADC12SR: Sampling rate limited to 50 ksps (reduce current) */
ADC12CTL2 = ADC12RES_2 | ADC12SR;
#elif defined(__MSP430_HAS_ADC12_B__)
/* ~ADC12ENC: Place module into hold before modifying configuration */
ADC12CTL0 &= ~ADC12ENC;
/* ADC12SHT_10: 512 ADC12CLK cycles per sample
* ADC12ON: Turn module on
* Do not enable yet.
*/
ADC12CTL0 = ADC12SHT0_10 | ADC12ON;
/* Start collection with conversion register zero
* ADC12SHS_0: Trigger on ADC12SC bit
* ADC12SHP: Pulsed sampling
* No sample-input signal inversion
* Divide clock by 1
* ADC12SSEL_0: Clock source is MODCLK (nominal 5MHz)
* ADC12CONSEQ_0: Single-channel, single-conversion
*/
ADC12CTL1 = ADC12SHS_0 | ADC12SHP | ADC12SSEL_0 | ADC12CONSEQ_0;
/* No predivider
* ADC12RES: 12-bit resolution
* Binary unsigned read-back */
ADC12CTL2 = ADC12RES_2;
/* Disable channel mapping.
* Use internal temperature and voltage channels */
ADC12CTL3 = ADC12TCMAP | ADC12BATMAP;
/* Delay 75us to allow REF to stabilize */
BSP430_CORE_DELAY_CYCLES(BSP430_CLOCK_US_TO_NOMINAL_MCLK(75));
#else
#error No ADC available
#endif /* ADC */
#ifdef INCH_AUX
/* Manually configure aux channel here */
#if (BSP430_PLATFORM_EXP430F5529LP - 0)
P6SEL |= BIT0 << AUX_CHANNEL;
#elif (BSP430_PLATFORM_EXP430G2 - 0)
ADC10AE0 |= BIT0 << AUX_CHANNEL;
#endif /* EXP430F5529LP */
#endif /* INCH_AUX */
return 0;
}
void main ()
{
volatile sBSP430hplPORTIE * b0hpl;
hBSP430halTIMER b0timer_hal;
int b0pin = iBSP430portBitPosition(BSP430_PLATFORM_BUTTON0_PORT_BIT);
struct sBSP430timerPulseCapture pulsecap_state;
hBSP430timerPulseCapture pulsecap;
unsigned long freq_Hz;
int rc;
vBSP430platformInitialize_ni();
(void)iBSP430consoleInitialize();
cprintf("\npulsecap " __DATE__ " " __TIME__ "\n");
cprintf("There's supposed to be a button at %s.%u\n",
xBSP430portName(BSP430_PLATFORM_BUTTON0_PORT_PERIPH_HANDLE),
b0pin);
b0hpl = xBSP430hplLookupPORTIE(BSP430_PLATFORM_BUTTON0_PORT_PERIPH_HANDLE);
if (NULL == b0hpl) {
cprintf("Guess it's not there. Never mind.\n");
return;
}
cprintf("Found it at %p. Now looking for timer HAL.\n", b0hpl);
b0timer_hal = hBSP430timerLookup(BUTTON0_TIMER_PERIPH_HANDLE);
if (NULL == b0timer_hal) {
cprintf("That's not there, though. Going away now.\n");
return;
}
vBSP430timerResetCounter_ni(b0timer_hal);
b0timer_hal->hpl->ctl = TASSEL__SMCLK | MC__CONTINOUS | TBCLR | TBIE;
vBSP430timerInferHints_ni(b0timer_hal);
freq_Hz = ulBSP430timerFrequency_Hz_ni(BUTTON0_TIMER_PERIPH_HANDLE);
cprintf("Cool, we're good to go with a %lu Hz timer at %p, now %lu.\n",
freq_Hz, b0timer_hal, ulBSP430timerCounter_ni(b0timer_hal, NULL));
/* Configure the port for its primary peripheral function */
b0hpl->dir &= ~BSP430_PLATFORM_BUTTON0_PORT_BIT;
BSP430_PORT_HPL_SET_REN(b0hpl, BSP430_PLATFORM_BUTTON0_PORT_BIT, BSP430_PORT_REN_PULL_UP);
BSP430_PORT_HPL_SET_SEL(b0hpl, BSP430_PLATFORM_BUTTON0_PORT_BIT, 1);
pulsecap = hBSP430timerPulseCaptureInitialize(&pulsecap_state,
BUTTON0_TIMER_PERIPH_HANDLE,
BUTTON0_TIMER_CCIDX,
BUTTON0_TIMER_CCIS,
BSP430_TIMER_PULSECAP_START_CALLBACK | BSP430_TIMER_PULSECAP_END_CALLBACK,
pulsecap_callback_ni);
if (NULL == pulsecap) {
cprintf("Sorry, pulsecap initialization failed\n");
return;
}
cprintf("%s.%u%c cctl %04x; pulsecap %p flags %04x\n",
xBSP430timerName(BUTTON0_TIMER_PERIPH_HANDLE),
BUTTON0_TIMER_CCIDX,
'A' + (BUTTON0_TIMER_CCIS / CCIS0),
b0timer_hal->hpl->cctl[BUTTON0_TIMER_CCIDX],
pulsecap, pulsecap->flags_ni);
/* Need to enable interrupts so timer overflow events are properly
* acknowledged */
BSP430_CORE_ENABLE_INTERRUPT();
rc = iBSP430timerPulseCaptureEnable(pulsecap);
cprintf("Enable got %d\n", rc);
rc = iBSP430timerPulseCaptureActivate(pulsecap);
cprintf("Activate got %d\n", rc);
while (1) {
unsigned int flags;
unsigned long pulseWidth_tt;
unsigned int overflows;
unsigned int activehighs;
BSP430_CORE_DISABLE_INTERRUPT();
do {
flags = pulsecap_state.flags_ni;
pulseWidth_tt = pulseWidth_tt_v;
overflows = overflows_v;
activehighs = activehighs_v;
} while (0);
BSP430_CORE_ENABLE_INTERRUPT();
cprintf("Timer %lu flags %04x ; %u over %u activehigh\n",
ulBSP430timerCounter(b0timer_hal, NULL),
flags, overflows, activehighs);
if (0 != pulseWidth_tt) {
cprintf("\tNew width: %lu ticks = %lu us\n", pulseWidth_tt,
(unsigned long)((1000ULL * pulseWidth_tt) / (freq_Hz / 1000UL)));
pulseWidth_tt = 0;
}
BSP430_CORE_DELAY_CYCLES(BSP430_CLOCK_NOMINAL_MCLK_HZ);
}
}
void main ()
{
int rc;
sBSP430m25p m25p_data;
hBSP430m25p m25p;
unsigned long addr;
unsigned long t0;
unsigned long t1;
vBSP430platformInitialize_ni();
(void)iBSP430consoleInitialize();
cprintf("\nBuild " __DATE__ " " __TIME__ "\n");
cprintf("SPI is %s: %s\n",
xBSP430serialName(BSP430_PLATFORM_M25P_SPI_PERIPH_HANDLE),
xBSP430platformPeripheralHelp(BSP430_PLATFORM_M25P_SPI_PERIPH_HANDLE, 0));
#ifdef BSP430_PLATFORM_M25P_PWR_PORT_PERIPH_HANDLE
cprintf("PWR at %s.%u\n",
xBSP430portName(BSP430_PLATFORM_M25P_PWR_PORT_PERIPH_HANDLE),
iBSP430portBitPosition(BSP430_PLATFORM_M25P_PWR_PORT_BIT));
#else /* BSP430_PLATFORM_M25P_PWR_PORT_PERIPH_HANDLE */
cprintf("PWR is hard-wired\n");
#endif /* BSP430_PLATFORM_M25P_PWR_PORT_PERIPH_HANDLE */
#ifdef BSP430_PLATFORM_M25P_RSTn_PORT_PERIPH_HANDLE
cprintf("RSTn at %s.%u\n",
xBSP430portName(BSP430_PLATFORM_M25P_RSTn_PORT_PERIPH_HANDLE),
iBSP430portBitPosition(BSP430_PLATFORM_M25P_RSTn_PORT_BIT));
#else /* BSP430_PLATFORM_M25P_RSTn_PORT_PERIPH_HANDLE */
cprintf("RSTn is hard-wired\n");
#endif /* BSP430_PLATFORM_M25P_RSTn_PORT_PERIPH_HANDLE */
cprintf("CSn at %s.%u\n",
xBSP430portName(BSP430_PLATFORM_M25P_CSn_PORT_PERIPH_HANDLE),
iBSP430portBitPosition(BSP430_PLATFORM_M25P_CSn_PORT_BIT));
memset(&m25p_data, 0, sizeof(m25p_data));
m25p_data.spi = hBSP430serialLookup(BSP430_PLATFORM_M25P_SPI_PERIPH_HANDLE);
m25p_data.csn_port = xBSP430hplLookupPORT(BSP430_PLATFORM_M25P_CSn_PORT_PERIPH_HANDLE);
m25p_data.csn_bit = BSP430_PLATFORM_M25P_CSn_PORT_BIT;
#ifdef BSP430_PLATFORM_M25P_RSTn_PORT_PERIPH_HANDLE
m25p_data.rstn_port = xBSP430hplLookupPORT(BSP430_PLATFORM_M25P_RSTn_PORT_PERIPH_HANDLE);
m25p_data.rstn_bit = BSP430_PLATFORM_M25P_RSTn_PORT_BIT;
#endif /* BSP430_PLATFORM_M25P_RSTn_PORT_PERIPH_HANDLE */
m25p = hBSP430m25pInitialize(&m25p_data,
BSP430_SERIAL_ADJUST_CTL0_INITIALIZER(UCCKPL | UCMSB | UCMST),
UCSSEL_2, 1);
if (NULL == m25p) {
cprintf("M25P device initialization failed.\n");
return;
}
#ifdef BSP430_PLATFORM_M25P_PWR_PORT_PERIPH_HANDLE
{
volatile sBSP430hplPORT * pwr_hpl;
/* Turn on power, then wait 10 ms for chip to stabilize before releasing RSTn. */
pwr_hpl = xBSP430hplLookupPORT(BSP430_PLATFORM_M25P_PWR_PORT_PERIPH_HANDLE);
pwr_hpl->out &= ~BSP430_PLATFORM_M25P_PWR_PORT_BIT;
pwr_hpl->dir |= BSP430_PLATFORM_M25P_PWR_PORT_BIT;
pwr_hpl->out |= BSP430_PLATFORM_M25P_PWR_PORT_BIT;
BSP430_CORE_DELAY_CYCLES(10 * (BSP430_CLOCK_NOMINAL_MCLK_HZ / 1000));
}
#endif /* BSP430_PLATFORM_M25P_PWR_PORT_PERIPH_HANDLE */
BSP430_M25P_RESET_CLEAR(m25p);
cprintf("Status register %d\n", iBSP430m25pStatus_ni(m25p));
rc = iBSP430m25pStrobeCommand_ni(m25p, BSP430_M25P_CMD_WREN);
cprintf("WREN got %d, status register %d\n", rc, iBSP430m25pStatus_ni(m25p));
rc = iBSP430m25pStrobeCommand_ni(m25p, BSP430_M25P_CMD_WRDI);
cprintf("WRDI got %d, status register %d\n", rc, iBSP430m25pStatus_ni(m25p));
rc = iBSP430m25pInitiateCommand_ni(m25p, BSP430_M25P_CMD_RDID);
if (0 == rc) {
rc = iBSP430m25pCompleteTxRx_ni(m25p, NULL, 0, 20, buffer);
}
BSP430_CORE_ENABLE_INTERRUPT();
cprintf("READ_IDENTIFICATION got %d\n", rc);
if (0 <= rc) {
dumpMemory(buffer, rc, 0);
}
cprintf("Config identified %u sectors of %lu bytes each: %lu bytes total\n",
BSP430_PLATFORM_M25P_SECTOR_COUNT,
(unsigned long)BSP430_PLATFORM_M25P_SECTOR_SIZE,
BSP430_PLATFORM_M25P_SECTOR_COUNT * (unsigned long)BSP430_PLATFORM_M25P_SECTOR_SIZE);
#if (BSP430_PLATFORM_M25P_SUBSECTOR_SIZE - 0)
cprintf("Config supports access as %u sub-sectors of %u bytes each\n",
(unsigned int)(BSP430_PLATFORM_M25P_SECTOR_COUNT * (BSP430_PLATFORM_M25P_SECTOR_SIZE / BSP430_PLATFORM_M25P_SUBSECTOR_SIZE)),
(unsigned int)BSP430_PLATFORM_M25P_SUBSECTOR_SIZE);
#else /* BSP430_PLATFORM_M25P_SUBSECTOR_SIZE */
cprintf("Config indicates device is not sub-sector addressable\n");
#endif /* BSP430_PLATFORM_M25P_SUBSECTOR_SIZE */
cprintf("RDID identified %lu bytes total capacity\n", 0x1UL << buffer[2]);
addr = 0;
rc = readFromAddress(m25p, addr, sizeof(flashContents));
if (sizeof(flashContents) != rc) {
cprintf("ERROR %d reading initial block\n", rc);
} else {
dumpMemory(buffer, rc, addr);
if (0 == memcmp(flashContents, buffer, rc)) {
cprintf("Found expected contents.\n");
}
}
#if (BSP430_PLATFORM_M25P_SUPPORTS_PE - 0)
rc = writeToAddress(m25p, BSP430_M25P_CMD_PE, addr, NULL, 0);
cprintf("PAGE_ERASE got %d\n", rc);
#else /* BSP430_PLATFORM_M25P_SUPPORTS_PE */
rc = writeToAddress(m25p, BSP430_M25P_CMD_SE, addr, NULL, 0);
cprintf("SECTOR_ERASE got %d\n", rc);
#endif /* BSP430_PLATFORM_M25P_SUPPORTS_PE */
rc = readFromAddress(m25p, addr, sizeof(buffer));
if (0 < rc) {
dumpMemory(buffer, rc, addr);
}
rc = writeToAddress(m25p, BSP430_M25P_CMD_PP, addr, flashContents, sizeof(flashContents));
cprintf("PAGE_PROGRAM got %d\n", rc);
rc = readFromAddress(m25p, addr, sizeof(buffer));
if (0 < rc) {
dumpMemory(buffer, rc, addr);
}
/* PAGE PROGRAM is the one that only clears 1s to 0s so needs a
* prior page or sector erase */
rc = writeToAddress(m25p, BSP430_M25P_CMD_PP, addr, flashContents + 4, 4);
cprintf("PAGE_PROGRAM to %lx returned %d\n", addr, rc);
rc = readFromAddress(m25p, 0, sizeof(flashContents));
dumpMemory(buffer, rc, 0);
/*
Write 4 took 8
PAGE_PROGRAM to 0 returned 4
00000000 88 11 03 30 cc 33 c3 3c 01 23 45 67 89 ab cd ef ...0.3.<.#Eg....
*/
/* PAGE_WRITE is the one that does not need a prior erase cycle */
addr = 8;
#if (BSP430_PLATFORM_M25P_SUPPORTS_PW - 0)
rc = writeToAddress(m25p, BSP430_M25P_CMD_PW, addr, flashContents + 4, 4);
cprintf("PAGE_WRITE to %lx returned %d\n", addr, rc);
#else
rc = writeToAddress(m25p, BSP430_M25P_CMD_PP, addr, flashContents + 4, 4);
cprintf("overwrite PAGE_PROGRAM to unerased %lx returned %d\n", addr, rc);
#endif
rc = readFromAddress(m25p, 0, sizeof(flashContents));
dumpMemory(buffer, rc, 0);
/*
Write 4 took 204
PAGE_WRITE to 8 returned 4
00000000 88 11 03 30 cc 33 c3 3c cc 33 c3 3c 89 ab cd ef ...0.3.<.3.<....
*/
cprintf("Initiating bulk erase...");
BSP430_CORE_DISABLE_INTERRUPT();
do {
t0 = t1 = 0;
rc = iBSP430m25pStrobeCommand_ni(m25p, BSP430_M25P_CMD_WREN);
if (0 == rc) {
rc = iBSP430m25pStrobeCommand_ni(m25p, BSP430_M25P_CMD_BE);
}
if (0 == rc) {
int sr;
t0 = ulBSP430uptime_ni();
do {
sr = iBSP430m25pStatus_ni(m25p);
} while ((0 <= sr) && (BSP430_M25P_SR_WIP & sr));
t1 = ulBSP430uptime();
}
} while (0);
BSP430_CORE_ENABLE_INTERRUPT();
cprintf("\nBULK_ERASE got %d\n", rc);
if (0 == rc) {
char tstr[BSP430_UPTIME_AS_TEXT_LENGTH];
cprintf("Bulk erase took %lu utt = %s\n", t1-t0, xBSP430uptimeAsText(t1 - t0, tstr));
}
rc = readFromAddress(m25p, 0, sizeof(flashContents));
dumpMemory(buffer, rc, 0);
rc = writeToAddress(m25p, BSP430_M25P_CMD_PP, 0, flashContents, sizeof(flashContents));
cprintf("Restore got %d\n", rc);
addr = 0;
while (addr < (256 * 1025L)) {
rc = readFromAddress(m25p, addr, sizeof(buffer));
if (0 > rc) {
break;
}
dumpMemory(buffer, rc, addr);
addr += rc;
break;
}
}
void main ()
{
#if (BSP430_CONSOLE - 0)
const char * help;
unsigned long smclk_Hz;
unsigned long aclk_Hz;
#endif /* BSP430_CONSOLE */
/* First thing you do in main is configure the platform. */
vBSP430platformInitialize_ni();
/* If we support a console, dump out a bunch of configuration
* information. */
#if (BSP430_CONSOLE - 0)
(void)iBSP430consoleInitialize();
cputtext("\nclocks " __DATE__ " " __TIME__ "\n");
cputtext("\nBSP430_PLATFORM_BOOT_CONFIGURE_LFXT1: ");
cputu(BSP430_PLATFORM_BOOT_CONFIGURE_LFXT1, 10);
cputtext("\nBSP430_CLOCK_LFXT1_STABILIZATION_DELAY_CYCLES: ");
cputul(BSP430_CLOCK_LFXT1_STABILIZATION_DELAY_CYCLES, 10);
cputtext("\nBSP430_PLATFORM_BOOT_LFXT1_DELAY_SEC: ");
cputu(BSP430_PLATFORM_BOOT_LFXT1_DELAY_SEC, 10);
cputtext("\nBSP430_PLATFORM_BOOT_CONFIGURE_CLOCKS: ");
cputu(BSP430_PLATFORM_BOOT_CONFIGURE_CLOCKS, 10);
#if defined(__MSP430_HAS_BC2__)
#if (configBSP430_BC2_TRIM_TO_MCLK - 0)
cputtext("\nconfigBSP430_BC2_TRIM_TO_MCLK: 1");
#else /* configBSP430_BC2_TRIM_TO_MCLK */
cputtext("\nconfigBSP430_BC2_TRIM_TO_MCLK: 0");
#endif /* configBSP430_BC2_TRIM_TO_MCLK */
#if (BSP430_BC2_TRIM_TO_MCLK - 0)
cputtext("\nBSP430_BC2_TRIM_TO_MCLK: 1");
#else /* BSP430_BC2_TRIM_TO_MCLK */
cputtext("\nBSP430_BC2_TRIM_TO_MCLK: 0");
#endif /* BSP430_BC2_TRIM_TO_MCLK */
#endif /* BC2 */
#if defined(__MSP430_HAS_UCS__) || defined(__MSP430_HAS_UCS_RF__)
#if (configBSP430_UCS_TRIM_DCOCLKDIV - 0)
cputtext("\nconfigBSP430_UCS_TRIM_DCOCLKDIV: 1");
#else /* configBSP430_UCS_TRIM_DCOCLKDIV */
cputtext("\nconfigBSP430_UCS_TRIM_DCOCLKDIV: 0");
#endif /* configBSP430_UCS_TRIM_DCOCLKDIV */
#if (BSP430_UCS_TRIM_DCOCLKDIV - 0)
cputtext("\nBSP430_UCS_TRIM_DCOCLKDIV: 1");
#else /* BSP430_UCS_TRIM_DCOCLKDIV */
cputtext("\nBSP430_UCS_TRIM_DCOCLKDIV: 0");
#endif /* BSP430_UCS_TRIM_DCOCLKDIV */
#endif /* UCS */
cputtext("\nBSP430_CLOCK_PUC_MCLK_HZ: ");
cputul(BSP430_CLOCK_PUC_MCLK_HZ, 10);
cputtext("\nBSP430_CLOCK_NOMINAL_MCLK_HZ: ");
cputul(BSP430_CLOCK_NOMINAL_MCLK_HZ, 10);
cputtext("\nBSP430_CLOCK_LFXT1_IS_FAULTED_NI(): ");
cputu(BSP430_CLOCK_LFXT1_IS_FAULTED_NI(), 10);
cputtext("\nBSP430_CLOCK_NOMINAL_VLOCLK_HZ: ");
cputu(BSP430_CLOCK_NOMINAL_VLOCLK_HZ, 10);
cputtext("\nBSP430_CLOCK_NOMINAL_XT1CLK_HZ: ");
cputul(BSP430_CLOCK_NOMINAL_XT1CLK_HZ, 10);
#if defined(BSP430_CLOCK_NOMINAL_XT2CLK_HZ)
cputtext("\nBSP430_PLATFORM_BOOT_CONFIGURE_XT2: ");
cputu(BSP430_PLATFORM_BOOT_CONFIGURE_XT2, 10);
cputtext("\nBSP430_CLOCK_XT2_IS_FAULTED_NI(): ");
cputu(BSP430_CLOCK_XT2_IS_FAULTED_NI(), 10);
cputtext("\nBSP430_CLOCK_NOMINAL_XT2CLK_HZ: ");
cputul(BSP430_CLOCK_NOMINAL_XT2CLK_HZ, 10);
#endif /* BSP430_CLOCK_NOMINAL_XT2CLK_HZ */
cputtext("\nulBSP430clockMCLK_Hz_ni(): ");
cputul(ulBSP430clockMCLK_Hz_ni(), 10);
cputtext("\nBSP430_PLATFORM_BOOT_SMCLK_DIVIDING_SHIFT: ");
cputi(BSP430_PLATFORM_BOOT_SMCLK_DIVIDING_SHIFT, 10);
cputtext("\nulBSP430clockSMCLK_Hz_ni(): ");
smclk_Hz = ulBSP430clockSMCLK_Hz_ni();
cputul(smclk_Hz, 10);
cputtext("\nBSP430_PLATFORM_BOOT_ACLK_DIVIDING_SHIFT: ");
cputi(BSP430_PLATFORM_BOOT_ACLK_DIVIDING_SHIFT, 10);
cputtext("\nulBSP430clockACLK_Hz_ni(): ");
aclk_Hz = ulBSP430clockACLK_Hz_ni();
cputul(aclk_Hz, 10);
#if (BSP430_TIMER_CCACLK - 0)
if (1000000UL <= aclk_Hz) {
cputtext("\nUnable to use high-speed ACLK for differential timing of SMCLK");
} else {
do {
const unsigned int SAMPLE_PERIOD_ACLK = 10;
volatile sBSP430hplTIMER * tp = xBSP430hplLookupTIMER(BSP430_TIMER_CCACLK_PERIPH_HANDLE);
unsigned int cc_delta;
unsigned long aclk_rel_smclk_Hz;
unsigned long smclk_rel_aclk_Hz;
if (! tp) {
cputtext("\nUnable to access configured CCACLK timer");
break;
}
/* Capture the SMCLK ticks between adjacent ACLK ticks */
tp->ctl = TASSEL_2 | MC_2 | TACLR;
cc_delta = uiBSP430timerCaptureDelta_ni(BSP430_TIMER_CCACLK_PERIPH_HANDLE,
BSP430_TIMER_CCACLK_ACLK_CCIDX,
CM_2,
BSP430_TIMER_CCACLK_ACLK_CCIS,
SAMPLE_PERIOD_ACLK);
tp->ctl = 0;
if (-1 == cc_delta) {
cputtext("\nCCACLK measurement failed");
break;
}
cputchar('\n');
cputu(SAMPLE_PERIOD_ACLK, 10);
cputtext(" ticks of ACLK produced ");
cputu(cc_delta, 10);
cputtext(" ticks of SMCLK");
cputtext("\nComparison with measured values:");
cputtext("\n SMCLK (Hz) (if measured ACLK correct): ");
smclk_rel_aclk_Hz = (cc_delta * aclk_Hz) / SAMPLE_PERIOD_ACLK;
cputul(smclk_rel_aclk_Hz, 10);
cputtext(" (error ");
cputl(smclk_rel_aclk_Hz - smclk_Hz, 10);
cputtext(" = ");
cputl(1000 * labs(smclk_rel_aclk_Hz - smclk_Hz) / smclk_Hz, 10);
cputtext(" kHz/MHz)");
cputtext("\n ACLK (Hz) (if measured SMCLK correct): ");
aclk_rel_smclk_Hz = SAMPLE_PERIOD_ACLK * smclk_Hz / cc_delta;
cputul(aclk_rel_smclk_Hz, 10);
cputtext(" (error ");
cputl(aclk_rel_smclk_Hz - aclk_Hz, 10);
cputtext(" = ");
cputl(1000 * labs(aclk_rel_smclk_Hz - aclk_Hz) / aclk_Hz, 10);
cputtext(" Hz/kHz)");
} while (0);
}
#else /* BSP430_TIMER_CCACLK */
cputtext("\nNo CCACLK timer available for ACLK/SMCLK comparison");
#endif /* BSP430_TIMER_CCACLK */
cputchar('\n');
#if defined(__MSP430_HAS_BC2__)
cputtext("\nBC2: DCO ");
cputu(DCOCTL, 16);
cputtext(" CTL1 ");
cputu(BCSCTL1, 16);
cputtext(" CTL2 ");
cputu(BCSCTL2, 16);
cputtext(" CTL3 ");
cputu(BCSCTL3, 16);
#endif
#if defined(__MSP430_HAS_FLL__) || defined(__MSP430_HAS_FLLPLUS__)
cprintf("\nFLL: SCF QCTL %02x I0 %02x I1 %02x ; CTL0 %02x CTL1 %02x CTL2 %02x\n",
SCFQCTL, SCFI0, SCFI1, FLL_CTL0, FLL_CTL1,
#if defined(FLL_CTL2_)
FLL_CTL2
#else /* FLL_CTL2 */
~0
#endif /* FLL_CTL2 */
);
#endif /* FLL/PLUS */
#if defined(__MSP430_HAS_UCS__) || defined(__MSP430_HAS_UCS_RF__)
cputtext("\nBSP430_UCS_FLL_SELREF: "
#if SELREF__XT2CLK <= BSP430_UCS_FLL_SELREF
"XT2CLK"
#elif SELREF__REFOCLK <= BSP430_UCS_FLL_SELREF
"REFOCLK"
#else /* BSP430_UCS_FLL_SELREF */
"XT1CLK"
#endif /* BSP430_UCS_FLL_SELREF */
);
cprintf("\nUCS RSEL %d DCO %d MOD %d:"
"\n CTL0 %04x CTL1 %04x CTL2 %04x CTL3 %04x"
"\n CTL4 %04x CTL5 %04x CTL6 %04x CTL7 %04x",
0x1F & (UCSCTL1 / DCORSEL0), 0x1F & (UCSCTL0 / DCO0), 0x1F & (UCSCTL0 / MOD0),
UCSCTL0, UCSCTL1, UCSCTL2, UCSCTL3,
UCSCTL4, UCSCTL5, UCSCTL6, UCSCTL7);
#endif /* UCS */
#if defined(__MSP430_HAS_CS__) || defined(__MSP430_HAS_CS_A__)
cprintf("\nCS %s : RSEL %d DCOFSEL %d:"
"\n CTL0 %04x CTL1 %04x CTL2 %04x CTL3 %04x"
"\n CTL4 %04x CTL5 %04x CTL6 %04x"
"\n FRCTL0 %04x",
#if (BSP430_CS_IS_FR57XX - 0)
"FR57xx"
#endif
#if (BSP430_CS_IS_FR58XX - 0)
"FR58xx"
#endif
"", !!(DCORSEL & CSCTL1), 0x07 & (CSCTL1 / DCOFSEL0),
CSCTL0, CSCTL1, CSCTL2, CSCTL3,
CSCTL4, CSCTL5, CSCTL6, FRCTL0);
#endif /* CS */
#endif /* BSP430_CONSOLE */
if (0 == iBSP430platformConfigurePeripheralPins_ni(BSP430_PERIPH_EXPOSED_CLOCKS, 0, 1)) {
#if (BSP430_CONSOLE - 0)
cputtext("\n\nClock signals exposed:\n ");
help = NULL;
#ifdef BSP430_PLATFORM_PERIPHERAL_HELP
help = xBSP430platformPeripheralHelp(BSP430_PERIPH_EXPOSED_CLOCKS, 0);
#endif /* BSP430_PLATFORM_PERIPHERAL_HELP */
if (NULL == help) {
help = "Go look at the data sheet and source, because nobody told me where they are";
}
cputtext(help);
cputtext("\nStatus register LPM bits: ");
cputu(__read_status_register() & BSP430_CORE_LPM_SR_MASK, 16);
cputtext("\nIFG1 bits: ");
#if defined(__MSP430_HAS_MSP430XV2_CPU__)
cputu(SFRIFG1, 16);
#else /* CPUX */
cputu(IFG1, 16);
#endif /* CPUX */
cputtext(" with OFIFG ");
cputu(OFIFG, 16);
cputchar('\n');
#endif /* BSP430_CONSOLE */
/* Spin here with CPU active. In LPM0, MCLK is disabled. Other
* clocks get disabled at deeper sleep modes; if you fall off the
* bottom, you might end up in LPM4 with all clocks disabled. */
while (1) {
vBSP430ledSet(0, -1);
BSP430_CORE_WATCHDOG_CLEAR();
BSP430_CORE_DELAY_CYCLES(BSP430_CLOCK_NOMINAL_MCLK_HZ / 2);
}
} else {
#if (BSP430_CONSOLE - 0)
cputtext("\nFailed to expose clock signals\n");
#endif /* BSP430_CONSOLE */
}
}
void main ()
{
int rc;
unsigned long uptime_ticks_per_sec;
const struct sBSP430onewireBus * bus = &ds18b20;
vBSP430platformInitialize_ni();
(void)iBSP430consoleInitialize();
cprintf("\nHere we go...\n");
uptime_ticks_per_sec = ulBSP430uptimeConversionFrequency_Hz_ni();
cprintf("Uptime now %lu with frequency %lu Hz\n",
ulBSP430uptime_ni(), uptime_ticks_per_sec);
cprintf("Monitoring DS18xx on %s.%u bit %x\n",
xBSP430portName(BSP430_PORT_HAL_GET_PERIPH_HANDLE(APP_DS18B20_PORT_HAL)) ?: "P?",
iBSP430portBitPosition(APP_DS18B20_BIT),
APP_DS18B20_BIT);
do {
rc = iBSP430onewireReadSerialNumber(bus, &serial);
if (0 != rc) {
cprintf("ERROR: Failed to read serial number from DS18B20: %d\n", rc);
BSP430_CORE_DELAY_CYCLES(BSP430_CLOCK_NOMINAL_MCLK_HZ);
}
} while (0 != rc);
cprintf("DS18B20 serial number: %02x%02x%02x%02x%02x%02x\n",
serial.id[0], serial.id[1], serial.id[2],
serial.id[3], serial.id[4], serial.id[5]);
while (1) {
int rc;
unsigned long start_tck;
unsigned long end_tck;
unsigned int duration_ms;
unsigned int delay_count = 0;
int t_c;
start_tck = ulBSP430uptime_ni();
rc = -1;
if (0 == iBSP430onewireRequestTemperature_ni(bus)) {
/* Wait for read to complete. Each read is nominally 61
* microseconds. Conversion time can be as long as 750 ms if
* 12-bit resolution is used. (12-bit resolution is the
* default.) */
while (! iBSP430onewireReadBit_ni(bus)) {
++delay_count;
}
rc = iBSP430onewireReadTemperature_ni(bus, &t_c);
}
end_tck = ulBSP430uptime_ni();
duration_ms = 1000 * (end_tck - start_tck) / uptime_ticks_per_sec;
if (0 == rc) {
cprintf("Temperature %d dCel or %d d[degF] in %u ms\n",
(10 * t_c) / 16, BSP430_ONEWIRE_xCel_TO_ddegF(t_c), duration_ms);
} else {
cprintf("Measurement failed in %u ms\n", duration_ms);
}
/* You'd want to do this if you were going to sleep here */
vBSP430onewireShutdown_ni(bus);
}
}
