void bsp_start(void) { rtems_status_code sc = RTEMS_SUCCESSFUL; ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; #if defined(MPC55XX_BOARD_MPC5674FEVB) unsigned system_clock_divider = 2; #else unsigned system_clock_divider = 1; #endif null_pointer_protection(); /* * make sure BSS/SBSS is cleared */ memset(&bsp_section_bss_begin [0], 0, (size_t) bsp_section_bss_size); /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() * function store the result in global variables so that it can be used * latter... */ myCpu = get_ppc_cpu_type(); myCpuRevision = get_ppc_cpu_revision(); /* * determine clock speed */ bsp_clock_speed = mpc55xx_get_system_clock() / system_clock_divider; /* Time reference value */ bsp_clicks_per_usec = bsp_clock_speed / 1000000; /* Initialize exceptions */ ppc_exc_vector_base = (uint32_t) mpc55xx_exc_vector_base; sc = ppc_exc_initialize( PPC_INTERRUPT_DISABLE_MASK_DEFAULT, (uintptr_t) bsp_section_work_begin, Configuration.interrupt_stack_size ); if (sc != RTEMS_SUCCESSFUL) { BSP_panic( "Cannot initialize exceptions"); } ppc_exc_set_handler(ASM_ALIGN_VECTOR, ppc_exc_alignment_handler); /* Initialize interrupts */ sc = bsp_interrupt_initialize(); if (sc != RTEMS_SUCCESSFUL) { BSP_panic( "Cannot initialize interrupts"); } mpc55xx_edma_init(); #ifdef MPC55XX_EMIOS_PRESCALER mpc55xx_emios_initialize(MPC55XX_EMIOS_PRESCALER); #endif }
DiscoveryVersion BSP_getDiscoveryVersion(int assertion) { static DiscoveryVersion rval = unknown; if ( unknown ==rval ) { unsigned char dc; unsigned short ds; /* this must work before and after the call to BSP_pciInitialize() -- * since the host bridge is at 0,0,0 it doesn't matter if the hosed * access methods are installed or not (as a matter of fact this shouldn't * matter for any device on hose 0) */ printk("config addr is 0x%08x\n", BSP_pci_configuration.pci_config_addr); printk("config data is 0x%08x\n", BSP_pci_configuration.pci_config_data); pci_read_config_word(0,0,0,PCI_VENDOR_ID, &ds); if ( PCI_VENDOR_ID_MARVELL != ds ) { if ( assertion ) { printk("Host bridge vendor id: 0x%04x\n",ds); BSP_panic("Host bridge vendor @ pci(0,0,0) is not MARVELL"); } else return unknown; } pci_read_config_word(0,0,0,PCI_DEVICE_ID, &ds); pci_read_config_byte(0,0,0,PCI_REVISION_ID, &dc); switch (ds) { case PCI_DEVICE_ID_MARVELL_MV64360: rval = MV_64360; break; case PCI_DEVICE_ID_MARVELL_GT64260: switch (dc) { default: break; case 0x10: return (rval = GT_64260_A); case 0x20: return (rval = GT_64260_B); } default: if ( assertion ) { printk("Marvell device id 0x%04x, revision 0x%02x; check %s:%u\n", ds, dc, __FILE__,__LINE__); BSP_panic("Unknown Marvell bridge or revision@ pci(0,0,0) is not MARVELL"); } break; } } return rval; }
void BSP_rtems_irq_mngt_init(unsigned cpuId) { int i; /* * connect all exception vectors needed */ ppc_exc_set_handler(ASM_EXT_VECTOR, C_dispatch_irq_handler); ppc_exc_set_handler(ASM_BOOKE_DEC_VECTOR, C_dispatch_irq_handler); /* * setup interrupt handlers table */ for (i = 0; i < BSP_IRQ_NUMBER; i++) { rtemsIrqTbl[i] = emptyIrq; rtemsIrqTbl[i].name = i; } /* * initialize interrupt management */ if (!BSP_rtems_irq_mngt_set(&initialConfig)) { BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n"); } }
void bsp_start( void ) { rtems_status_code sc = RTEMS_SUCCESSFUL; uintptr_t intrStackStart; uintptr_t intrStackSize; /* * Note we can not get CPU identification dynamically, so * force current_ppc_cpu. */ current_ppc_cpu = PPC_PSIM; /* * initialize the device driver parameters * assume we are running with 20MHz bus * this should speed up some tests :-) */ BSP_bus_frequency = 20; bsp_time_base_frequency = 20000000; bsp_clicks_per_usec = BSP_bus_frequency; rtems_counter_initialize_converter(bsp_time_base_frequency); /* * Initialize the interrupt related settings. */ intrStackStart = (uintptr_t) bsp_interrupt_stack_start; intrStackSize = (uintptr_t) bsp_interrupt_stack_size; BSP_mem_size = (uint32_t )RamSize; /* * Initialize default raw exception handlers. */ ppc_exc_initialize(intrStackStart, intrStackSize); /* Install default handler for the decrementer exception */ sc = ppc_exc_set_handler( ASM_DEC_VECTOR, default_decrementer_exception_handler); if (sc != RTEMS_SUCCESSFUL) { BSP_panic("cannot install decrementer exception handler"); } /* Initalize interrupt support */ bsp_interrupt_initialize(); #if 0 /* * Setup BATs and enable MMU */ /* Memory */ setdbat(0, 0x0<<24, 0x0<<24, 2<<24, _PAGE_RW); setibat(0, 0x0<<24, 0x0<<24, 2<<24, 0); /* PCI */ setdbat(1, 0x8<<24, 0x8<<24, 1<<24, IO_PAGE); setdbat(2, 0xc<<24, 0xc<<24, 1<<24, IO_PAGE); _write_MSR(_read_MSR() | MSR_DR | MSR_IR); __asm__ volatile("sync; isync"); #endif }
void _CPU_ISR_install_vector( uint32_t vector, proc_ptr new_handler, proc_ptr *old_handler ) { BSP_panic("_CPU_ISR_install_vector called\n"); }
/* * This code assumes the exceptions management setup has already * been done. We just need to replace the exceptions that will * be handled like interrupt. On MPC7455 and many PPC processors * this means the decrementer exception and the external exception. */ void BSP_rtems_irq_mng_init(unsigned cpuId) { rtems_raw_except_connect_data vectorDesc; int i; /* * First initialize the Interrupt management hardware */ #ifdef TRACE_IRQ_INIT printk("Initializing the interrupt controller of the GT64260\n"); #endif #ifdef TRACE_IRQ_INIT printk("Going to re-initialize the rtemsIrq table %d\n",BSP_IRQ_NUMBER); #endif /* * Initialize Rtems management interrupt table */ /* * re-init the rtemsIrq table */ for (i = 0; i < BSP_IRQ_NUMBER; i++) { rtemsIrq[i] = defaultIrq; rtemsIrq[i].name = i; } /* * Init initial Interrupt management config */ initial_config.irqNb = BSP_IRQ_NUMBER; initial_config.defaultEntry = defaultIrq; initial_config.irqHdlTbl = rtemsIrq; initial_config.irqBase = BSP_ASM_IRQ_VECTOR_BASE; initial_config.irqPrioTbl = BSPirqPrioTable; #ifdef TRACE_IRQ_INIT printk("Going to setup irq mngt configuration\n"); #endif if (!BSP_rtems_irq_mngt_set(&initial_config)) { /* * put something here that will show the failure... */ BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n"); } #ifdef TRACE_IRQ_INIT printk("Done setup irq mngt configuration\n"); #endif #ifdef TRACE_IRQ_INIT printk("RTEMS IRQ management is now operationnal\n"); #endif }
void bsp_predriver_hook() { rtems_status_code sc = RTEMS_SUCCESSFUL; RTEMS_DEBUG_PRINT( "Initialize eDMA ...\n"); sc = mpc55xx_edma_init(); if (sc != RTEMS_SUCCESSFUL) { BSP_panic( "Cannot initialize eDMA"); } else { DEBUG_DONE(); } }
/* * This code assumes the exceptions management setup has already * been done. We just need to replace the exceptions that will * be handled like interrupt. On mcp750/mpc750 and many PPC processors * this means the decrementer exception and the external exception. */ void BSP_rtems_irq_mng_init(unsigned cpuId) { int i; /* * First initialize the Interrupt management hardware */ #ifdef TRACE_IRQ_INIT printk("Going to initialize openpic compliant device\n"); #endif /* FIXME (t.s.): we should probably setup the EOI delay by * passing a non-zero 'epic_freq' argument (frequency of the * EPIC serial interface) but I don't know the value on this * board (8245 SDRAM freq, IIRC)... */ openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses, 0, 16, 0 /* epic_freq */); #ifdef TRACE_IRQ_INIT printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n"); #endif /* * Initialize Rtems management interrupt table */ /* * re-init the rtemsIrq table */ for (i = 0; i < BSP_IRQ_NUMBER; i++) { rtemsIrq[i] = defaultIrq; rtemsIrq[i].name = i; } /* * Init initial Interrupt management config */ initial_config.irqNb = BSP_IRQ_NUMBER; initial_config.defaultEntry = defaultIrq; initial_config.irqHdlTbl = rtemsIrq; initial_config.irqBase = BSP_LOWEST_OFFSET; initial_config.irqPrioTbl = irqPrioTable; printk("Call BSP_rtems_irq_mngt_set\n"); if (!BSP_rtems_irq_mngt_set(&initial_config)) { /* * put something here that will show the failure... */ BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n"); } #ifdef TRACE_IRQ_INIT printk("RTEMS IRQ management is now operationnal\n"); #endif }
/* * bsp_start * * This routine does the bulk of the system initialization. */ void bsp_start( void ) { rtems_status_code sc = RTEMS_SUCCESSFUL; ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; /* Get the UART clock initialized first in case we call printk */ InitUARTClock(); Init_FPGA(); EarlyUARTInit(115200); /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() * function store the result in global variables * so that it can be used later... */ myCpu = get_ppc_cpu_type(); myCpuRevision = get_ppc_cpu_revision(); /* * initialize the device driver parameters */ /* Set globals visible to clock.c */ /* timebase register ticks/microsecond = CPU Clk in MHz */ bsp_clicks_per_usec = 400; bsp_timer_internal_clock = TRUE; bsp_timer_average_overhead = 2; bsp_timer_least_valid = 3; /* * Initialize default raw exception handlers. */ sc = ppc_exc_initialize( PPC_INTERRUPT_DISABLE_MASK_DEFAULT, (uintptr_t) intrStack_start, (uintptr_t) intrStack_size ); if (sc != RTEMS_SUCCESSFUL) { BSP_panic("cannot initialize exceptions"); } /* * Install our own set of exception vectors */ BSP_rtems_irq_mng_init(0); }
/* * This code assumes the exceptions management setup has already * been done. We just need to replace the exceptions that will * be handled like interrupt. On mcp750/mpc750 and many PPC processors * this means the decrementer exception and the external exception. */ void BSP_rtems_irq_mng_init(unsigned cpuId) { int i; /* * First initialize the Interrupt management hardware */ OpenPIC = (void*)PSIM.OpenPIC; openpic_init(1,0,0,16,0,0); /* * Initialize Rtems management interrupt table */ /* * re-init the rtemsIrq table */ for (i = 0; i < BSP_IRQ_NUMBER; i++) { rtemsIrq[i] = defaultIrq; rtemsIrq[i].name = i; } /* * Init initial Interrupt management config */ initial_config.irqNb = BSP_IRQ_NUMBER; initial_config.defaultEntry = defaultIrq; initial_config.irqHdlTbl = rtemsIrq; initial_config.irqBase = BSP_LOWEST_OFFSET; initial_config.irqPrioTbl = irqPrioTable; for (i = BSP_PCI_IRQ_LOWEST_OFFSET; i< BSP_PCI_IRQ_NUMBER; i++ ) { irqPrioTable[i] = 8; } if (!BSP_rtems_irq_mngt_set(&initial_config)) { /* * put something here that will show the failure... */ BSP_panic( "Unable to initialize RTEMS interrupt Management!!! System locked\n" ); } #ifdef TRACE_IRQ_INIT printk("RTEMS IRQ management is now operationnal\n"); #endif }
/* * bsp_start * * This routine does the bulk of the system initialization. */ void bsp_start( void ) { rtems_status_code sc = RTEMS_SUCCESSFUL; ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() * function store the result in global variables * so that it can be used latter... */ myCpu = get_ppc_cpu_type(); myCpuRevision = get_ppc_cpu_revision(); /* * initialize the device driver parameters */ /* timebase register ticks/microsecond */ bsp_clicks_per_usec = (250000000 / 1000000); bsp_serial_per_sec = 14625000; bsp_serial_external_clock = false; bsp_timer_internal_clock = true; bsp_serial_xon_xoff = false; bsp_serial_cts_rts = false; bsp_serial_rate = 115200; bsp_timer_average_overhead = 2; bsp_timer_least_valid = 3; /* * Initialize default raw exception handlers. */ sc = ppc_exc_initialize( PPC_INTERRUPT_DISABLE_MASK_DEFAULT, (uint32_t)IntrStack_start, IntrStack_end - IntrStack_start ); if (sc != RTEMS_SUCCESSFUL) { BSP_panic("cannot initialize exceptions"); } /* * Install our own set of exception vectors */ BSP_rtems_irq_mng_init(0); }
/* * This code assumes the exceptions management setup has already * been done. We just need to replace the exceptions that will * be handled like interrupt. On mcp750/mpc750 and many PPC processors * this means the decrementer exception and the external exception. */ void BSP_rtems_irq_mng_init(unsigned cpuId) { int i; /* * First initialize the Interrupt management hardware */ /* * Initialize RTEMS management interrupt table */ /* * re-init the rtemsIrq table */ for (i = 0; i < BSP_IRQ_NUMBER; i++) { irqPrioTable[i] = 8; rtemsIrq[i] = defaultIrq; rtemsIrq[i].name = i; #ifdef BSP_SHARED_HANDLER_SUPPORT rtemsIrq[i].next_handler = NULL; #endif } /* * Init initial Interrupt management config */ initial_config.irqNb = BSP_IRQ_NUMBER; initial_config.defaultEntry = defaultIrq; initial_config.irqHdlTbl = rtemsIrq; initial_config.irqBase = BSP_LOWEST_OFFSET; initial_config.irqPrioTbl = irqPrioTable; if (!BSP_rtems_irq_mngt_set(&initial_config)) { /* * put something here that will show the failure... */ BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n"); } #ifdef TRACE_IRQ_INIT printk("RTEMS IRQ management is now operational\n"); #endif }
static void _bsp_start(void) { rtems_status_code sc = RTEMS_SUCCESSFUL; uintptr_t intrStackStart = CPU_UP_ALIGN((uint32_t)__bsp_ram_start); uintptr_t intrStackSize = rtems_configuration_get_interrupt_stack_size(); /* * Initialize default raw exception handlers. * * This BSP does not assume anything about firmware possibly loaded in the * FPGA, so the external interrupt should not be enabled in order to avoid * spurious interrupts. */ sc = ppc_exc_initialize(PPC_INTERRUPT_DISABLE_MASK_DEFAULT & ~MSR_EE, intrStackStart, intrStackSize); if (sc != RTEMS_SUCCESSFUL) BSP_panic("Cannot initialize exceptions"); /* Install our own set of exception vectors */ BSP_rtems_irq_mngt_init(0); }
/* This is a very ugly hack. I don't want to change the shared * code to support multiple hoses so we hide everything under * the hood with horrible kludges for now. Sorry. */ void BSP_pci_initialize(void) { #if 0 /* These values are already set up for the shared/pci.c code */ { extern pci_config_access_functions pci_indirect_functions; /* by means of the PCI_CONFIG_ADDR/PCI_CONFIG_DATA macros (bsp.h) */ BSP_pci_configuration.pci_config_addr = hoses[0].pci_config_addr; BSP_pci_configuration.pci_config_data = hoses[0].pci_config_data; BSP_pci_configuration.pci_functions = &pci_indirect_functions; } #endif /* initialize the first hose */ /* scan hose 0 and sets the maximum bus number */ pci_initialize(); /* remember the boundary */ BSP_pci_hose1_bus_base = pci_bus_count(); /* so far, so good -- now comes the cludgy part: */ /* hack/reset the bus count */ ucMaxPCIBus = 0; /* scan hose 1 */ BSP_pci_configuration.pci_config_addr = hoses[1].pci_config_addr; BSP_pci_configuration.pci_config_data = hoses[1].pci_config_data; pci_initialize(); /* check for overflow of an unsigned char */ if ( BSP_pci_hose1_bus_base + pci_bus_count() > 255 ) { BSP_panic("Too many PCI busses in the system"); } /* readjust total number */ ucMaxPCIBus+=BSP_pci_hose1_bus_base; /* install new access functions that can hide the hoses */ BSP_pci_configuration.pci_config_addr = (volatile unsigned char *)0xdeadbeef; BSP_pci_configuration.pci_config_data = (volatile unsigned char *)0xdeadbeef; BSP_pci_configuration.pci_functions = &pci_hosed_indirect_functions; }
static void sccInitialize (int chan) { int i; /* * allocate buffers * FIXME: use a cache-line size boundary alloc here */ rxBuf[chan] = malloc(sizeof(*rxBuf[chan]) + 2*PPC_CACHE_ALIGNMENT); if (rxBuf[chan] == NULL) { BSP_panic("Cannot allocate console rx buffer\n"); } else { /* * round up rxBuf[chan] to start at a cache line size */ rxBuf[chan] = (sccRxBuf_t *) (((uint32_t)rxBuf[chan]) + (PPC_CACHE_ALIGNMENT - ((uint32_t)rxBuf[chan]) % PPC_CACHE_ALIGNMENT)); } /* * Allocate buffer descriptors */ sccCurrRxBd[chan] = sccFrstRxBd[chan] = m8xx_bd_allocate(SCC_RXBD_CNT); sccPrepTxBd[chan] = sccDequTxBd[chan] = sccFrstTxBd[chan] = m8xx_bd_allocate(SCC_TXBD_CNT); switch(chan) { case CONS_CHN_SCC1: /* * Configure port A pins to enable TXD1 and RXD1 pins * FIXME: add setup for modem control lines.... */ m8xx.papar |= 0x03; m8xx.padir &= ~0x03; /* * Configure port C pins to enable RTS1 pins (static active low) */ m8xx.pcpar &= ~0x01; m8xx.pcso &= ~0x01; m8xx.pcdir |= 0x01; m8xx.pcdat &= ~0x01; break; case CONS_CHN_SCC2: /* * Configure port A pins to enable TXD2 and RXD2 pins * FIXME: add setup for modem control lines.... */ m8xx.papar |= 0x0C; m8xx.padir &= ~0x0C; /* * Configure port C pins to enable RTS2 pins (static active low) */ m8xx.pcpar &= ~0x02; m8xx.pcso &= ~0x02; m8xx.pcdir |= 0x02; m8xx.pcdat &= ~0x02; break; case CONS_CHN_SCC3: /* * Configure port A pins to enable TXD3 and RXD3 pins * FIXME: add setup for modem control lines.... */ m8xx.papar |= 0x30; m8xx.padir &= ~0x30; /* * Configure port C pins to enable RTS3 (static active low) */ m8xx.pcpar &= ~0x04; m8xx.pcso &= ~0x04; m8xx.pcdir |= 0x04; m8xx.pcdat &= ~0x04; break; case CONS_CHN_SCC4: /* * Configure port A pins to enable TXD4 and RXD4 pins * FIXME: add setup for modem control lines.... */ m8xx.papar |= 0xC0; m8xx.padir &= ~0xC0; /* * Configure port C pins to enable RTS4 pins (static active low) */ m8xx.pcpar &= ~0x08; m8xx.pcso &= ~0x08; m8xx.pcdir |= 0x08; m8xx.pcdat &= ~0x08; break; case CONS_CHN_SMC1: /* * Configure port B pins to enable SMTXD1 and SMRXD1 pins */ m8xx.pbpar |= 0xC0; m8xx.pbdir &= ~0xC0; break; case CONS_CHN_SMC2: /* * Configure port B pins to enable SMTXD2 and SMRXD2 pins */ m8xx.pbpar |= 0xC00; m8xx.pbdir &= ~0xC00; break; } /* * allocate and connect BRG */ sccBRGalloc(chan,9600); /* * Set up SCCx parameter RAM common to all protocols */ CHN_PARAM_SET(chan,rbase,(char *)sccFrstRxBd[chan] - (char *)&m8xx); CHN_PARAM_SET(chan,tbase,(char *)sccFrstTxBd[chan] - (char *)&m8xx); CHN_PARAM_SET(chan,rfcr ,M8xx_RFCR_MOT | M8xx_RFCR_DMA_SPACE(0)); CHN_PARAM_SET(chan,tfcr ,M8xx_TFCR_MOT | M8xx_TFCR_DMA_SPACE(0)); if (m8xx_scc_mode[chan] != TERMIOS_POLLED) CHN_PARAM_SET(chan,mrblr,RXBUFSIZE); else CHN_PARAM_SET(chan,mrblr,1); /* * Set up SCCx parameter RAM UART-specific parameters */ CHN_PARAM_SET(chan,un.uart.max_idl ,MAX_IDL_DEFAULT); CHN_PARAM_SET(chan,un.uart.brkln ,0); CHN_PARAM_SET(chan,un.uart.brkec ,0); CHN_PARAM_SET(chan,un.uart.brkcr ,0); if (m8xx_console_chan_desc[chan].is_scc) { m8xx_console_chan_desc[chan].parms.sccp->un.uart.character[0]=0x8000; /* no char filter */ m8xx_console_chan_desc[chan].parms.sccp->un.uart.rccm=0x80FF; /* control character mask */ } /* * Set up the Receive Buffer Descriptors */ for (i = 0;i < SCC_RXBD_CNT;i++) { sccFrstRxBd[chan][i].status = M8xx_BD_EMPTY | M8xx_BD_INTERRUPT; if (i == SCC_RXBD_CNT-1) { sccFrstRxBd[chan][i].status |= M8xx_BD_WRAP; } sccFrstRxBd[chan][i].length = 0; sccFrstRxBd[chan][i].buffer = (*rxBuf[chan])[i]; } /* * Setup the Transmit Buffer Descriptor */ for (i = 0;i < SCC_TXBD_CNT;i++) { sccFrstTxBd[chan][i].status = M8xx_BD_INTERRUPT; if (i == SCC_TXBD_CNT-1) { sccFrstTxBd[chan][i].status |= M8xx_BD_WRAP; } sccFrstTxBd[chan][i].length = 0; sccFrstTxBd[chan][i].buffer = NULL; } /* * Set up SCC general and protocol-specific mode registers */ CHN_EVENT_CLR(chan,~0); /* Clear any pending events */ CHN_MASK_SET(chan,0); /* Mask all interrupt/event sources */ if (m8xx_console_chan_desc[chan].is_scc) { m8xx_console_chan_desc[chan].regs.sccr->psmr = 0xb000; /* 8N1, CTS flow control */ m8xx_console_chan_desc[chan].regs.sccr->gsmr_h = 0x00000000; m8xx_console_chan_desc[chan].regs.sccr->gsmr_l = 0x00028004; /* UART mode */ } else { m8xx_console_chan_desc[chan].regs.smcr->smcmr = 0x4820; } /* * Send "Init parameters" command */ m8xx_cp_execute_cmd(M8xx_CR_OP_INIT_RX_TX | m8xx_console_chan_desc[chan].cr_chan_code); /* * Enable receiver and transmitter */ if (m8xx_console_chan_desc[chan].is_scc) { m8xx_console_chan_desc[chan].regs.sccr->gsmr_l |= 0x00000030; } else { m8xx_console_chan_desc[chan].regs.smcr->smcmr |= 0x0003; } if (m8xx_scc_mode[chan] != TERMIOS_POLLED) { rtems_irq_connect_data irq_conn_data = { m8xx_console_chan_desc[chan].ivec_src, sccInterruptHandler, /* rtems_irq_hdl */ (rtems_irq_hdl_param)chan, /* (rtems_irq_hdl_param) */ mpc8xx_console_irq_on, /* (rtems_irq_enable) */ mpc8xx_console_irq_off, /* (rtems_irq_disable) */ mpc8xx_console_irq_isOn /* (rtems_irq_is_enabled) */ }; if (!BSP_install_rtems_irq_handler (&irq_conn_data)) { rtems_panic("console: cannot install IRQ handler"); } } }
/* * bsp_start * * This routine does the bulk of the system initialization. */ void bsp_start( void ) { rtems_status_code sc = RTEMS_SUCCESSFUL; uintptr_t intrStackStart; uintptr_t intrStackSize; /* * Note we can not get CPU identification dynamically. * PVR has to be set to PPC_PSIM (0xfffe) from the device * file. */ get_ppc_cpu_type(); /* * initialize the device driver parameters */ BSP_bus_frequency = (unsigned int)&PSIM_INSTRUCTIONS_PER_MICROSECOND; bsp_clicks_per_usec = BSP_bus_frequency; BSP_time_base_divisor = 1; /* * The simulator likes the exception table to be at 0xfff00000. */ bsp_exceptions_in_RAM = FALSE; /* * Initialize the interrupt related settings. */ intrStackStart = (uintptr_t) __rtems_end; intrStackSize = rtems_configuration_get_interrupt_stack_size(); /* * Initialize default raw exception handlers. */ sc = ppc_exc_initialize( PPC_INTERRUPT_DISABLE_MASK_DEFAULT, intrStackStart, intrStackSize ); if (sc != RTEMS_SUCCESSFUL) { BSP_panic("cannot initialize exceptions"); } /* * Initalize RTEMS IRQ system */ BSP_rtems_irq_mng_init(0); /* * Setup BATs and enable MMU */ /* Memory */ setdbat(0, 0x0<<24, 0x0<<24, 2<<24, _PAGE_RW); setibat(0, 0x0<<24, 0x0<<24, 2<<24, 0); /* PCI */ setdbat(1, 0x8<<24, 0x8<<24, 1<<24, IO_PAGE); setdbat(2, 0xc<<24, 0xc<<24, 1<<24, IO_PAGE); _write_MSR(_read_MSR() | MSR_DR | MSR_IR); asm volatile("sync; isync"); }
void bsp_start( void) { rtems_status_code sc = RTEMS_SUCCESSFUL; unsigned long i = 0; ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; uintptr_t interrupt_stack_start = (uintptr_t) bsp_interrupt_stack_start; uintptr_t interrupt_stack_size = (uintptr_t) bsp_interrupt_stack_size; /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function * store the result in global variables so that it can be used latter... */ myCpu = get_ppc_cpu_type(); myCpuRevision = get_ppc_cpu_revision(); /* Basic CPU initialization */ cpu_init(); /* * Enable instruction and data caches. Do not force writethrough mode. */ #ifdef BSP_INSTRUCTION_CACHE_ENABLED rtems_cache_enable_instruction(); #endif #ifdef BSP_DATA_CACHE_ENABLED rtems_cache_enable_data(); #endif /* * This is evaluated during runtime, so it should be ok to set it * before we initialize the drivers. */ /* Initialize some device driver parameters */ #ifdef HAS_UBOOT BSP_bus_frequency = bsp_uboot_board_info.bi_busfreq; #else /* HAS_UBOOT */ BSP_bus_frequency = BSP_CLKIN_FRQ * BSP_SYSPLL_MF / BSP_SYSPLL_CKID; #endif /* HAS_UBOOT */ bsp_time_base_frequency = BSP_bus_frequency / 4; bsp_clicks_per_usec = bsp_time_base_frequency / 1000000; /* Initialize some console parameters */ for (i = 0; i < Console_Configuration_Count; ++i) { Console_Configuration_Ports [i].ulClock = BSP_bus_frequency; #ifdef HAS_UBOOT Console_Configuration_Ports [i].pDeviceParams = (void *) bsp_uboot_board_info.bi_baudrate; #endif } /* Initialize exception handler */ #ifndef BSP_DATA_CACHE_ENABLED ppc_exc_cache_wb_check = 0; #endif sc = ppc_exc_initialize( PPC_INTERRUPT_DISABLE_MASK_DEFAULT, interrupt_stack_start, interrupt_stack_size ); if (sc != RTEMS_SUCCESSFUL) { BSP_panic("cannot initialize exceptions"); } /* Install default handler for the decrementer exception */ sc = ppc_exc_set_handler( ASM_DEC_VECTOR, mpc83xx_decrementer_exception_handler); if (sc != RTEMS_SUCCESSFUL) { BSP_panic("cannot install decrementer exception handler"); } /* Initalize interrupt support */ sc = bsp_interrupt_initialize(); if (sc != RTEMS_SUCCESSFUL) { BSP_panic("cannot intitialize interrupts\n"); } #ifdef SHOW_MORE_INIT_SETTINGS printk("Exit from bspstart\n"); #endif }
void BSP_motload_pci_fixup(void) { uint32_t b0,b1,r0,r1,lim,dis; /* MotLoad on the mvme5500 and mvme6100 configures the PCI * busses nicely, i.e., the values read from the memory address * space BARs by means of PCI config cycles directly reflect the * CPU memory map. Thus, the presence of two hoses is already hidden. * * Unfortunately, all PCI I/O addresses are 'zero-based' i.e., * a hose-specific base address would have to be added to * the values read from config space. * * We fix this here so I/O BARs also reflect the CPU memory map. * * Furthermore, the mvme5500 uses * f000.0000 * ..f07f.ffff for PCI-0 / hose0 * * and * * f080.0000 * ..f0ff.0000 for PCI-1 / hose 0 * * whereas the mvme6100 does it the other way round... */ b0 = in_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_Low_Decode) ); b1 = in_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_Low_Decode) ); r0 = in_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_Remap) ); r1 = in_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_Remap) ); switch ( BSP_getDiscoveryVersion(0) ) { case MV_64360: /* In case of the MV64360 the 'limit' is actually a 'size'! * Disable by setting special bits in the 'BAR disable reg'. */ dis = in_le32( (volatile unsigned*)(BSP_MV64x60_BASE + MV_64360_BASE_ADDR_DISBL) ); /* disable PCI0 I/O and PCI1 I/O */ out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + MV_64360_BASE_ADDR_DISBL), dis | (1<<9) | (1<<14) ); /* remap busses on hose 0; if the remap register was already set, assume * that someone else [such as the bootloader] already performed the fixup */ if ( (b0 & 0xffff) && 0 == (r0 & 0xffff) ) { rtems_pci_io_remap( 0, BSP_pci_hose1_bus_base, (b0 & 0xffff)<<16 ); out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_Remap), (b0 & 0xffff) ); } /* remap busses on hose 1 */ if ( (b1 & 0xffff) && 0 == (r1 & 0xffff) ) { rtems_pci_io_remap( BSP_pci_hose1_bus_base, pci_bus_count(), (b1 & 0xffff)<<16 ); out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_Remap), (b1 & 0xffff) ); } /* re-enable */ out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + MV_64360_BASE_ADDR_DISBL), dis ); break; case GT_64260_A: case GT_64260_B: if ( (b0 & 0xfff) && 0 == (r0 & 0xfff) ) { /* base are only 12 bits */ /* switch window off by setting the limit < base */ lim = in_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_High_Decode) ); out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_High_Decode), 0 ); /* remap busses on hose 0 */ rtems_pci_io_remap( 0, BSP_pci_hose1_bus_base, (b0 & 0xfff)<<20 ); /* BTW: it seems that writing the base register also copies the * value into the 'remap' register automatically (??) */ out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_Remap), (b0 & 0xfff) ); /* re-enable */ out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI0_IO_High_Decode), lim ); } if ( (b1 & 0xfff) && 0 == (r1 & 0xfff) ) { /* base are only 12 bits */ /* switch window off by setting the limit < base */ lim = in_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_High_Decode) ); out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_High_Decode), 0 ); /* remap busses on hose 1 */ rtems_pci_io_remap( BSP_pci_hose1_bus_base, pci_bus_count(), (b1 & 0xfff)<<20 ); out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_Remap), (b1 & 0xfff) ); /* re-enable */ out_le32( (volatile unsigned*)(BSP_MV64x60_BASE + GT_PCI1_IO_High_Decode), lim ); } break; default: BSP_panic("Unknown discovery version; switch in file: "__FILE__" not implemented (yet)"); break; /* never get here */ } /* Fixup the IRQ lines; the mvme6100 maps them nicely into our scheme, i.e., GPP * interrupts start at 64 upwards * * The mvme5500 is apparently initialized differently :-(. GPP interrupts start at 0 * Since all PCI interrupts are wired to GPP we simply check for a value < 64 and * reprogram the interrupt line register. */ BSP_pciScan(0, fixup_irq_line, 0); }
void VIA_isa_bridge_interrupts_setup(void) { pci_isa_bridge_device pci_dev; uint32_t temp; unsigned char tmp; unsigned char maxBus; unsigned found = 0; maxBus = pci_bus_count(); pci_dev.function = 0; /* Assumes the bidge is the first function */ for (pci_dev.bus = 0; pci_dev.bus < maxBus; pci_dev.bus++) { #ifdef SCAN_PCI_PRINT printk("isa_bridge_interrupts_setup: Scanning bus %d\n", pci_dev.bus); #endif for (pci_dev.device = 0; pci_dev.device < PCI_MAX_DEVICES; pci_dev.device++) { #ifdef SCAN_PCI_PRINT printk("isa_bridge_interrupts_setup: Scanning device %d\n", pci_dev.device); #endif pci_read_config_dword(pci_dev.bus, pci_dev.device, pci_dev.function, PCI_VENDOR_ID, &temp); #ifdef SCAN_PCI_PRINT printk("Vendor/device = %x\n", temp); #endif if ((temp == (((unsigned short) PCI_VENDOR_ID_VIA) | (PCI_DEVICE_ID_VIA_82C586_0 << 16))) ) { bridge = pci_dev; via_82c586 = &bridge; #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS /* * Should print : bus = 0, device = 11, function = 0 on a MCP750. */ printk("Via PCI/ISA bridge found at bus = %d, device = %d, function = %d\n", via_82c586->bus, via_82c586->device, via_82c586->function); #endif found = 1; goto loop_exit; } } } loop_exit: if (!found) BSP_panic("VIA_82C586 PCI/ISA bridge not found!n"); tmp = inb(0x810); if ( !(tmp & 0x2)) { #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS printk("This is a second generation MCP750 board\n"); printk("We must reprogram the PCI/ISA bridge...\n"); #endif pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function, 0x47, &tmp); #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS printk(" PCI ISA bridge control2 = %x\n", (unsigned) tmp); #endif /* * Enable 4D0/4D1 ISA interrupt level/edge config registers */ tmp |= 0x20; pci_write_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function, 0x47, tmp); /* * Now program the ISA interrupt edge/level */ tmp = ELCRS_INT9_LVL | ELCRS_INT10_LVL | ELCRS_INT11_LVL; outb(tmp, ISA8259_S_ELCR); tmp = ELCRM_INT5_LVL; outb(tmp, ISA8259_M_ELCR);; /* * Set the Interrupt inputs to non-inverting level interrupt */ pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function, 0x54, &tmp); #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS printk(" PCI ISA bridge PCI/IRQ Edge/Level Select = %x\n", (unsigned) tmp); #endif tmp = 0; pci_write_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function, 0x54, tmp); } else { #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS printk("This is a first generation MCP750 board\n"); printk("We just show the actual value used by PCI/ISA bridge\n"); #endif pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function, 0x47, &tmp); #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS printk(" PCI ISA bridge control2 = %x\n", (unsigned) tmp); #endif /* * Show the Interrupt inputs inverting/non-inverting level status */ pci_read_config_byte(via_82c586->bus, via_82c586->device, via_82c586->function, 0x54, &tmp); #ifdef SHOW_ISA_PCI_BRIDGE_SETTINGS printk(" PCI ISA bridge PCI/IRQ Edge/Level Select = %x\n", (unsigned) tmp); #endif } }
void bsp_start( void ) { rtems_status_code sc = RTEMS_SUCCESSFUL; #if !defined(mvme2100) unsigned l2cr; #endif uintptr_t intrStackStart; uintptr_t intrStackSize; ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; prep_t boardManufacturer; motorolaBoard myBoard; Triv121PgTbl pt=0; /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() * function store the result in global variables so that it can be used * later... */ myCpu = get_ppc_cpu_type(); myCpuRevision = get_ppc_cpu_revision(); /* * Init MMU block address translation to enable hardware access */ #if !defined(mvme2100) /* * PC legacy IO space used for inb/outb and all PC compatible hardware */ setdbat(1, _IO_BASE, _IO_BASE, 0x10000000, IO_PAGE); #endif /* * PCI devices memory area. Needed to access OpenPIC features * provided by the Raven * * T. Straumann: give more PCI address space */ setdbat(2, PCI_MEM_BASE+PCI_MEM_WIN0, PCI_MEM_BASE+PCI_MEM_WIN0, 0x10000000, IO_PAGE); /* * Must have acces to open pic PCI ACK registers provided by the RAVEN */ setdbat(3, 0xf0000000, 0xf0000000, 0x10000000, IO_PAGE); #if defined(mvme2100) /* Need 0xfec00000 mapped for this */ EUMBBAR = get_eumbbar(); #endif /* * enables L1 Cache. Note that the L1_caches_enables() codes checks for * relevant CPU type so that the reason why there is no use of myCpu... */ L1_caches_enables(); #if !defined(mvme2100) /* * Enable L2 Cache. Note that the set_L2CR(L2CR) codes checks for * relevant CPU type (mpc750)... */ l2cr = get_L2CR(); #ifdef SHOW_LCR2_REGISTER printk("Initial L2CR value = %x\n", l2cr); #endif if ( (! (l2cr & 0x80000000)) && ((int) l2cr == -1)) set_L2CR(0xb9A14000); #endif /* * Initialize the interrupt related settings. */ intrStackStart = (uintptr_t) __rtems_end; intrStackSize = rtems_configuration_get_interrupt_stack_size(); /* * Initialize default raw exception handlers. */ sc = ppc_exc_initialize( PPC_INTERRUPT_DISABLE_MASK_DEFAULT, intrStackStart, intrStackSize ); if (sc != RTEMS_SUCCESSFUL) { BSP_panic("cannot initialize exceptions"); } select_console(CONSOLE_LOG); /* * We check that the keyboard is present and immediately * select the serial console if not. */ #if defined(BSP_KBD_IOBASE) { int err; err = kbdreset(); if (err) select_console(CONSOLE_SERIAL); } #else select_console(CONSOLE_SERIAL); #endif boardManufacturer = checkPrepBoardType(&residualCopy); if (boardManufacturer != PREP_Motorola) { printk("Unsupported hardware vendor\n"); while (1); } myBoard = getMotorolaBoard(); printk("-----------------------------------------\n"); printk("Welcome to %s on %s\n", _RTEMS_version, motorolaBoardToString(myBoard)); printk("-----------------------------------------\n"); #ifdef SHOW_MORE_INIT_SETTINGS printk("Residuals are located at %x\n", (unsigned) &residualCopy); printk("Additionnal boot options are %s\n", loaderParam); printk("Initial system stack at %x\n",stack); printk("Software IRQ stack starts at %x with size %u\n", intrStackStart, intrStackSize); printk("-----------------------------------------\n"); #endif #ifdef TEST_RETURN_TO_PPCBUG printk("Hit <Enter> to return to PPCBUG monitor\n"); printk("When Finished hit GO. It should print <Back from monitor>\n"); debug_getc(); _return_to_ppcbug(); printk("Back from monitor\n"); _return_to_ppcbug(); #endif /* TEST_RETURN_TO_PPCBUG */ #ifdef SHOW_MORE_INIT_SETTINGS printk("Going to start PCI buses scanning and initialization\n"); #endif pci_initialize(); { const struct _int_map *bspmap = motorolaIntMap(currentBoard); if( bspmap ) { printk("pci : Configuring interrupt routing for '%s'\n", motorolaBoardToString(currentBoard)); FixupPCI(bspmap, motorolaIntSwizzle(currentBoard)); } else printk("pci : Interrupt routing not available for this bsp\n"); } #ifdef SHOW_MORE_INIT_SETTINGS printk("Number of PCI buses found is : %d\n", pci_bus_count()); #endif #ifdef TEST_RAW_EXCEPTION_CODE printk("Testing exception handling Part 1\n"); /* * Cause a software exception */ __asm__ __volatile ("sc"); /* * Check we can still catch exceptions and return coorectly. */ printk("Testing exception handling Part 2\n"); __asm__ __volatile ("sc"); /* * Somehow doing the above seems to clobber SPRG0 on the mvme2100. The * interrupt disable mask is stored in SPRG0. Is this a problem? */ ppc_interrupt_set_disable_mask( PPC_INTERRUPT_DISABLE_MASK_DEFAULT); #endif /* See above */ BSP_mem_size = residualCopy.TotalMemory; BSP_bus_frequency = residualCopy.VitalProductData.ProcessorBusHz; BSP_processor_frequency = residualCopy.VitalProductData.ProcessorHz; BSP_time_base_divisor = (residualCopy.VitalProductData.TimeBaseDivisor? residualCopy.VitalProductData.TimeBaseDivisor : 4000); /* clear hostbridge errors but leave MCP disabled - * PCI config space scanning code will trip otherwise :-( */ _BSP_clear_hostbridge_errors(0 /* enableMCP */, 0/*quiet*/); /* Allocate and set up the page table mappings * This is only available on >604 CPUs. * * NOTE: This setup routine may modify the available memory * size. It is essential to call it before * calculating the workspace etc. */ pt = BSP_pgtbl_setup(&BSP_mem_size); if (!pt || TRIV121_MAP_SUCCESS != triv121PgTblMap( pt, TRIV121_121_VSID, 0xfeff0000, 1, TRIV121_ATTR_IO_PAGE, TRIV121_PP_RW_PAGE)) { printk("WARNING: unable to setup page tables VME " "bridge must share PCI space\n"); } /* * initialize the device driver parameters */ bsp_clicks_per_usec = BSP_bus_frequency/(BSP_time_base_divisor * 1000); /* * Initalize RTEMS IRQ system */ BSP_rtems_irq_mng_init(0); /* Activate the page table mappings only after * initializing interrupts because the irq_mng_init() * routine needs to modify the text */ if (pt) { #ifdef SHOW_MORE_INIT_SETTINGS printk("Page table setup finished; will activate it NOW...\n"); #endif BSP_pgtbl_activate(pt); /* finally, switch off DBAT3 */ setdbat(3, 0, 0, 0, 0); } #if defined(DEBUG_BATS) ShowBATS(); #endif #ifdef SHOW_MORE_INIT_SETTINGS printk("Exit from bspstart\n"); #endif }
/* * bsp_start() * * Board-specific initialization code. Called from the generic boot_card() * function defined in rtems/c/src/lib/libbsp/shared/main.c. That function * does some of the board independent initialization. It is called from the * MBX8xx entry point _start() defined in * rtems/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S * * _start() has set up a stack, has zeroed the .bss section, has turned off * interrupts, and placed the processor in the supervisor mode. boot_card() * has left the processor in that state when bsp_start() was called. * * RUNS WITH ADDRESS TRANSLATION AND CACHING TURNED OFF! * ASSUMES THAT THE VIRTUAL ADDRESSES WILL BE IDENTICAL TO THE PHYSICAL * ADDRESSES. Software-controlled address translation would be required * otherwise. * * Input parameters: NONE * * Output parameters: NONE * * Return values: NONE */ void bsp_start(void) { rtems_status_code sc = RTEMS_SUCCESSFUL; ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function * store the result in global variables so that it can be used latter... */ myCpu = get_ppc_cpu_type(); myCpuRevision = get_ppc_cpu_revision(); mmu_init(); /* * Enable instruction and data caches. Do not force writethrough mode. */ #if NVRAM_CONFIGURE == 1 if ( nvram->cache_mode & 0x02 ) rtems_cache_enable_instruction(); if ( nvram->cache_mode & 0x01 ) rtems_cache_enable_data(); #else #ifdef INSTRUCTION_CACHE_ENABLE rtems_cache_enable_instruction(); #endif #ifdef DATA_CACHE_ENABLE rtems_cache_enable_data(); #endif #endif /* Initialize exception handler */ sc = ppc_exc_initialize( PPC_INTERRUPT_DISABLE_MASK_DEFAULT, (uintptr_t) IntrStack_start, (uintptr_t) intrStack - (uintptr_t) IntrStack_start ); if ( sc != RTEMS_SUCCESSFUL ) { BSP_panic( "cannot initialize exceptions" ); } /* Initalize interrupt support */ sc = bsp_interrupt_initialize(); if ( sc != RTEMS_SUCCESSFUL ) { BSP_panic( "cannot initialize interrupts" ); } /* * initialize the device driver parameters */ #if ( defined(mbx860_001b) || \ defined(mbx860_002b) || \ defined(mbx860_003b) || \ defined(mbx860_003b) || \ defined(mbx860_004b) || \ defined(mbx860_005b) || \ defined(mbx860_006b) || \ defined(mbx821_001b) || \ defined(mbx821_002b) || \ defined(mbx821_003b) || \ defined(mbx821_004b) || \ defined(mbx821_005b) || \ defined(mbx821_006b)) bsp_clicks_per_usec = 0; /* for 32768Hz extclk */ #else bsp_clicks_per_usec = 1; /* for 4MHz extclk */ #endif bsp_serial_per_sec = 10000000; bsp_serial_external_clock = true; bsp_serial_xon_xoff = false; bsp_serial_cts_rts = true; bsp_serial_rate = 9600; #if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) ) bsp_clock_speed = 50000000; bsp_timer_average_overhead = 3; bsp_timer_least_valid = 3; #else bsp_clock_speed = 40000000; bsp_timer_average_overhead = 3; bsp_timer_least_valid = 3; #endif m8xx.scc2.sccm=0; m8xx.scc2p.rbase=0; m8xx.scc2p.tbase=0; m8xx_cp_execute_cmd( M8xx_CR_OP_STOP_TX | M8xx_CR_CHAN_SCC2 ); #ifdef SHOW_MORE_INIT_SETTINGS printk("Exit from bspstart\n"); #endif }
/* * High level IRQ handler called from shared_raw_irq_code_entry */ int C_dispatch_irq_handler (BSP_Exception_frame *frame, unsigned int excNum) { register unsigned int irq; #if BSP_ISA_IRQ_NUMBER > 0 register unsigned isaIntr; /* boolean */ register unsigned oldMask = 0; /* old isa pic masks */ register unsigned newMask; /* new isa pic masks */ #endif if (excNum == ASM_DEC_VECTOR) { bsp_irq_dispatch_list(rtems_hdl_tbl, BSP_DECREMENTER, default_rtems_entry.hdl); return 0; } #if BSP_PCI_IRQ_NUMBER > 0 if ( OpenPIC ) { irq = openpic_irq(0); if (irq == OPENPIC_VEC_SPURIOUS) { ++BSP_spuriousIntr; return 0; } /* some BSPs might want to use a different numbering... */ irq = irq - OPENPIC_VEC_SOURCE + BSP_PCI_IRQ_LOWEST_OFFSET; } else { #if BSP_ISA_IRQ_NUMBER > 0 #ifdef BSP_PCI_ISA_BRIDGE_IRQ irq = BSP_PCI_ISA_BRIDGE_IRQ; #else #error "Configuration Error -- BSP with ISA + PCI IRQs MUST define BSP_PCI_ISA_BRIDGE_IRQ" #endif #else BSP_panic("MUST have an OpenPIC if BSP has PCI IRQs but no ISA IRQs"); /* BSP_panic() never returns but the 'return' statement silences * a compiler warning about 'irq' possibly being used w/o initialization. */ return -1; #endif } #endif #if BSP_ISA_IRQ_NUMBER > 0 #ifdef BSP_PCI_ISA_BRIDGE_IRQ #if 0 == BSP_PCI_IRQ_NUMBER #error "Configuration Error -- BSP w/o PCI IRQs MUST NOT define BSP_PCI_ISA_BRIDGE_IRQ" #endif isaIntr = (irq == BSP_PCI_ISA_BRIDGE_IRQ); #else isaIntr = 1; #endif if (isaIntr) { /* * Acknowledge and read 8259 vector */ irq = (unsigned int) (*(unsigned char *) RAVEN_INTR_ACK_REG); /* * store current PIC mask */ oldMask = i8259s_cache; newMask = oldMask | irq_mask_or_tbl [irq]; i8259s_cache = newMask; outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); BSP_irq_ack_at_i8259s (irq); #if BSP_PCI_IRQ_NUMBER > 0 if ( OpenPIC ) openpic_eoi(0); #endif } #endif /* dispatch handlers */ bsp_irq_dispatch_list(rtems_hdl_tbl, irq, default_rtems_entry.hdl); #if BSP_ISA_IRQ_NUMBER > 0 if (isaIntr) { i8259s_cache = oldMask; outport_byte(PIC_MASTER_IMR_IO_PORT, i8259s_cache & 0xff); outport_byte(PIC_SLAVE_IMR_IO_PORT, ((i8259s_cache & 0xff00) >> 8)); } else #endif { #if BSP_PCI_IRQ_NUMBER > 0 #ifdef BSP_PCI_VME_DRIVER_DOES_EOI /* leave it to the VME bridge driver to do EOI, so * it can re-enable the openpic while handling * VME interrupts (-> VME priorities in software) */ if (_BSP_vme_bridge_irq != irq && OpenPIC)
int psim_exception_handler( BSP_Exception_frame *frame, unsigned exception_number) { BSP_panic("Unexpected interrupt occured"); return 0; }
void bsp_start(void) { rtems_status_code sc = RTEMS_SUCCESSFUL; ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; /* Set MPC8260ADS board LEDS and Uart enable lines */ _BSP_GPLED0_off(); _BSP_GPLED1_off(); _BSP_Uart1_enable(); _BSP_Uart2_enable(); /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function * store the result in global variables so that it can be used latter... */ myCpu = get_ppc_cpu_type(); myCpuRevision = get_ppc_cpu_revision(); cpu_init(); /* mmu_init(); */ /* Initialize exception handler */ /* FIXME: Interrupt stack begin and size */ sc = ppc_exc_initialize( PPC_INTERRUPT_DISABLE_MASK_DEFAULT, (uintptr_t) IntrStack_start, (uintptr_t) intrStack - (uintptr_t) IntrStack_start ); if (sc != RTEMS_SUCCESSFUL) { BSP_panic("cannot intitialize exceptions"); } /* Initalize interrupt support */ sc = bsp_interrupt_initialize(); if (sc != RTEMS_SUCCESSFUL) { BSP_panic("cannot intitialize interrupts"); } /* mmu_init(); */ /* * Enable instruction and data caches. Do not force writethrough mode. */ #if INSTRUCTION_CACHE_ENABLE rtems_cache_enable_instruction(); #endif #if DATA_CACHE_ENABLE rtems_cache_enable_data(); #endif /* * initialize the device driver parameters */ bsp_clicks_per_usec = 10; /* for 40MHz extclk */ bsp_serial_per_sec = 40000000; bsp_serial_external_clock = 0; bsp_serial_xon_xoff = 0; bsp_serial_cts_rts = 0; bsp_serial_rate = 9600; bsp_timer_average_overhead = 3; bsp_timer_least_valid = 3; bsp_clock_speed = 40000000; #ifdef REV_0_2 /* set up some board specific registers */ m8260.siumcr &= 0xF3FFFFFF; /* set TBEN ** BUG FIX ** */ m8260.siumcr |= 0x08000000; #endif /* use BRG1 to generate 32kHz timebase */ /* m8260.brgc1 = M8260_BRG_EN + (uint32_t)(((uint16_t)((40016384)/(32768)) - 1) << 1) + 0; */ #ifdef SHOW_MORE_INIT_SETTINGS printk("Exit from bspstart\n"); #endif }
/* * This code assumes the exceptions management setup has already * been done. We just need to replace the exceptions that will * be handled like interrupt. On mcp750/mpc750 and many PPC processors * this means the decrementer exception and the external exception. */ void BSP_rtems_irq_mng_init(unsigned cpuId) { #if BSP_ISA_IRQ_NUMBER > 0 && !defined(mvme2100) int known_cpi_isa_bridge = 0; #endif int i; /* * First initialize the Interrupt management hardware */ #if defined(mvme2100) #ifdef TRACE_IRQ_INIT printk("Going to initialize EPIC interrupt controller (openpic compliant)\n"); #endif /* EPIC sources don't start at the regular place; define appropriate offset * prior to initializing the PIC. */ openpic_init(1, mvme2100_openpic_initpolarities, mvme2100_openpic_initsenses, 16, 16, BSP_bus_frequency); #else #if BSP_PCI_IRQ_NUMBER > 0 #ifdef TRACE_IRQ_INIT printk("Going to initialize raven interrupt controller (openpic compliant)\n"); #endif openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses, 0, 0, 0); #ifdef TRACE_IRQ_INIT printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n"); #endif #endif #if BSP_ISA_IRQ_NUMBER > 0 if ( currentBoard == MESQUITE ) { #ifndef qemu VIA_isa_bridge_interrupts_setup(); #endif known_cpi_isa_bridge = 1; } if ( currentBoard == MVME_2300 ) { /* nothing to do for W83C553 bridge */ known_cpi_isa_bridge = 1; } if ( currentBoard == MTX_WO_PP || currentBoard == MTX_W_PP ) { /* W83C554, don't to anything at the moment. gregm 11/6/2002 */ known_cpi_isa_bridge = 1; } if (!known_cpi_isa_bridge) { printk("Please add code for PCI/ISA bridge init to libbsp/powerpc/shared/irq/irq_init.c\n"); printk("If your card works correctly please add a test and set known_cpi_isa_bridge to true\n"); printk("currentBoard = %i\n", currentBoard); } #ifdef TRACE_IRQ_INIT printk("Going to initialize the ISA PC legacy IRQ management hardware\n"); #endif BSP_i8259s_init(); #endif #endif /* * Initialize RTEMS management interrupt table */ /* * re-init the rtemsIrq table */ for (i = 0; i < BSP_IRQ_NUMBER; i++) { rtemsIrq[i] = defaultIrq; rtemsIrq[i].name = i; } /* * Init initial Interrupt management config */ initial_config.irqNb = BSP_IRQ_NUMBER; initial_config.defaultEntry = defaultIrq; initial_config.irqHdlTbl = rtemsIrq; initial_config.irqBase = BSP_LOWEST_OFFSET; initial_config.irqPrioTbl = irqPrioTable; if (!BSP_rtems_irq_mngt_set(&initial_config)) { /* * put something here that will show the failure... */ BSP_panic("Unable to initialize RTEMS interrupt Management!!! System locked\n"); } #ifdef TRACE_IRQ_INIT printk("RTEMS IRQ management is now operational\n"); #endif }
void bsp_start(void) { rtems_status_code sc = RTEMS_SUCCESSFUL; unsigned long i = 0; ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function * store the result in global variables so that it can be used latter... */ myCpu = get_ppc_cpu_type(); myCpuRevision = get_ppc_cpu_revision(); /* Initialize some device driver parameters */ #ifdef HAS_UBOOT BSP_bus_frequency = bsp_uboot_board_info.bi_busfreq; bsp_clicks_per_usec = bsp_uboot_board_info.bi_busfreq / 8000000; #endif /* HAS_UBOOT */ /* Initialize some console parameters */ for (i = 0; i < Console_Port_Count; ++i) { console_tbl *ct = &Console_Port_Tbl [i]; ct->ulClock = BSP_bus_frequency; #ifdef HAS_UBOOT if (ct->deviceType == SERIAL_NS16550) { ct->pDeviceParams = (void *) bsp_uboot_board_info.bi_baudrate; } #endif } /* Disable decrementer */ PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS(BOOKE_TCR, BOOKE_TCR_DIE); /* Initialize exception handler */ ppc_exc_vector_base = (uint32_t) bsp_exc_vector_base; sc = ppc_exc_initialize( PPC_INTERRUPT_DISABLE_MASK_DEFAULT, (uintptr_t) bsp_section_work_begin, Configuration.interrupt_stack_size ); if (sc != RTEMS_SUCCESSFUL) { BSP_panic("cannot initialize exceptions"); } /* Now it is possible to make the code execute only */ qoriq_mmu_change_perm( FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SX, FSL_EIS_MAS3_SX, FSL_EIS_MAS3_SR ); /* Initalize interrupt support */ sc = bsp_interrupt_initialize(); if (sc != RTEMS_SUCCESSFUL) { BSP_panic("cannot intitialize interrupts\n"); } /* Disable boot page translation */ qoriq.lcc.bptr &= ~BPTR_EN; }
void detect_host_bridge(void) { PPC_DEVICE *hostbridge; uint32_t id0; uint32_t tmp; /* * This code assumes that the host bridge is located at * bus 0, dev 0, func 0 AND that the old pre PCI 2.1 * standard devices detection mechanism that was used on PC * (still used in BSD source code) works. */ hostbridge=residual_find_device(&residualCopy, PROCESSORDEVICE, NULL, BridgeController, PCIBridge, -1, 0); if (hostbridge) { if (hostbridge->DeviceId.Interface==PCIBridgeIndirect) { pci.pci_functions=&pci_indirect_functions; /* Should be extracted from residual data, * indeed MPC106 in CHRP mode is different, * but we should not use residual data in * this case anyway. */ pci.pci_config_addr = ((volatile unsigned char *) (ptr_mem_map->io_base+0xcf8)); pci.pci_config_data = ptr_mem_map->io_base+0xcfc; } else if(hostbridge->DeviceId.Interface==PCIBridgeDirect) { pci.pci_functions=&pci_direct_functions; pci.pci_config_data=(unsigned char *) 0x80800000; } else { } } else { /* Let us try by experimentation at our own risk! */ pci.pci_functions = &pci_direct_functions; /* On all direct bridges I know the host bridge itself * appears as device 0 function 0. */ pci_read_config_dword(0, 0, 0, PCI_VENDOR_ID, &id0); if (id0==~0U) { pci.pci_functions = &pci_indirect_functions; pci.pci_config_addr = ((volatile unsigned char*) (ptr_mem_map->io_base+0xcf8)); pci.pci_config_data = ((volatile unsigned char*)ptr_mem_map->io_base+0xcfc); } /* Here we should check that the host bridge is actually * present, but if it not, we are in such a desperate * situation, that we probably can't even tell it. */ } pci_read_config_dword(0, 0, 0, 0, &id0); #ifdef SHOW_RAVEN_SETTINGS printk("idreg 0 = 0x%x\n",id0); #endif if((id0 == PCI_VENDOR_ID_MOTOROLA + (PCI_DEVICE_ID_MOTOROLA_RAVEN<<16)) || (id0 == PCI_VENDOR_ID_MOTOROLA + (PCI_DEVICE_ID_MOTOROLA_HAWK<<16))) { /* * We have a Raven bridge. We will get information about its settings */ pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0); #ifdef SHOW_RAVEN_SETTING printk("RAVEN PCI command register = %x\n",id0); #endif id0 |= RAVEN_CLEAR_EVENTS_MASK; pci_write_config_dword(0, 0, 0, PCI_COMMAND, id0); pci_read_config_dword(0, 0, 0, PCI_COMMAND, &id0); #ifdef SHOW_RAVEN_SETTING printk("After error clearing RAVEN PCI command register = %x\n",id0); #endif if (id0 & RAVEN_MPIC_IOSPACE_ENABLE) { pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_0, &tmp); #ifdef SHOW_RAVEN_SETTING printk("Raven MPIC is accessed via IO Space Access at address : %x\n",(tmp & ~0x1)); #endif } if (id0 & RAVEN_MPIC_MEMSPACE_ENABLE) { pci_read_config_dword(0, 0, 0,PCI_BASE_ADDRESS_1, &tmp); #ifdef SHOW_RAVEN_SETTING printk("Raven MPIC is accessed via memory Space Access at address : %x\n", tmp); #endif OpenPIC=(volatile struct OpenPIC *) (tmp + PREP_ISA_MEM_BASE); printk("OpenPIC found at %x.\n", OpenPIC); } } #if BSP_PCI_IRQ_NUMBER > 0 if (OpenPIC == (volatile struct OpenPIC *)0) { BSP_panic("OpenPic Not found\n"); } #endif }
void bsp_start( void) { rtems_status_code sc = RTEMS_SUCCESSFUL; ppc_cpu_id_t myCpu; ppc_cpu_revision_t myCpuRevision; uintptr_t interrupt_stack_start = (uintptr_t) bsp_interrupt_stack_start; uintptr_t interrupt_stack_size = (uintptr_t) bsp_interrupt_stack_size; /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function * store the result in global variables so that it can be used latter... */ myCpu = get_ppc_cpu_type(); myCpuRevision = get_ppc_cpu_revision(); /* Basic CPU initialization */ cpu_init(); /* * Enable instruction and data caches. Do not force writethrough mode. */ #if INSTRUCTION_CACHE_ENABLE rtems_cache_enable_instruction(); #endif #if DATA_CACHE_ENABLE rtems_cache_enable_data(); #endif /* * This is evaluated during runtime, so it should be ok to set it * before we initialize the drivers. */ /* Initialize some device driver parameters */ /* * get the (internal) bus frequency * NOTE: the external bus may be clocked at a lower speed * but this does not concern the internal units like PIT, * DEC, baudrate generator etc) */ if (RTEMS_SUCCESSFUL != bsp_tqm_get_cib_uint32("cu", &BSP_bus_frequency)) { BSP_panic("Cannot determine BUS frequency\n"); } bsp_clicks_per_usec = BSP_bus_frequency/1000000/16; bsp_timer_least_valid = 3; bsp_timer_average_overhead = 3; /* Initialize exception handler */ sc = ppc_exc_initialize( PPC_INTERRUPT_DISABLE_MASK_DEFAULT, interrupt_stack_start, interrupt_stack_size ); if (sc != RTEMS_SUCCESSFUL) { BSP_panic("cannot initialize exceptions"); } /* Initalize interrupt support */ sc = bsp_interrupt_initialize(); if (sc != RTEMS_SUCCESSFUL) { BSP_panic("cannot intitialize interrupts"); } #ifdef SHOW_MORE_INIT_SETTINGS printk("Exit from bspstart\n"); #endif }
void bsp_start( void) { rtems_status_code sc = RTEMS_SUCCESSFUL; unsigned long i = 0; /* * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function * store the result in global variables so that it can be used latter... */ get_ppc_cpu_type(); get_ppc_cpu_revision(); /* Basic CPU initialization */ cpu_init(); /* * Enable instruction and data caches. Do not force writethrough mode. */ #ifdef BSP_INSTRUCTION_CACHE_ENABLED rtems_cache_enable_instruction(); #endif #ifdef BSP_DATA_CACHE_ENABLED rtems_cache_enable_data(); #endif /* * This is evaluated during runtime, so it should be ok to set it * before we initialize the drivers. */ /* Initialize some device driver parameters */ #ifdef HAS_UBOOT BSP_bus_frequency = bsp_uboot_board_info.bi_busfreq; #else /* HAS_UBOOT */ BSP_bus_frequency = BSP_CLKIN_FRQ * BSP_SYSPLL_MF / BSP_SYSPLL_CKID; #endif /* HAS_UBOOT */ bsp_time_base_frequency = BSP_bus_frequency / 4; bsp_clicks_per_usec = bsp_time_base_frequency / 1000000; rtems_counter_initialize_converter(bsp_time_base_frequency); /* Initialize some console parameters */ for (i = 0; i < console_device_count; ++i) { ns16550_context *ctx = (ns16550_context *) console_device_table[i].context; ctx->clock = BSP_bus_frequency; #ifdef HAS_UBOOT ctx->initial_baud = bsp_uboot_board_info.bi_baudrate; #endif } /* Initialize exception handler */ #ifndef BSP_DATA_CACHE_ENABLED ppc_exc_cache_wb_check = 0; #endif ppc_exc_initialize( (uintptr_t) bsp_section_work_begin, rtems_configuration_get_interrupt_stack_size() ); /* Install default handler for the decrementer exception */ sc = ppc_exc_set_handler( ASM_DEC_VECTOR, mpc83xx_decrementer_exception_handler); if (sc != RTEMS_SUCCESSFUL) { BSP_panic("cannot install decrementer exception handler"); } /* Initalize interrupt support */ bsp_interrupt_initialize(); #ifdef SHOW_MORE_INIT_SETTINGS printk("Exit from bspstart\n"); #endif }