/* This function is called for configurating pinmux for spi module
* This function only support switching default or gpio or fixed-ALTx mode on fixed pins
* (Although there are many ALTx-pinmux configuration choices on various pins for the same
* peripheral module) */
void spi_pinmux_config(unsigned int instance, pinmux_type_t pinmux)
{
switch(instance)
{
case 0:
switch(pinmux)
{
case kPinmuxType_Default:
BW_PORT_PCRn_MUX(HW_PORTD, 0, 0);
BW_PORT_PCRn_MUX(HW_PORTD, 1, 0);
BW_PORT_PCRn_MUX(HW_PORTD, 2, 0);
BW_PORT_PCRn_MUX(HW_PORTD, 3, 0);
break;
case kPinmuxType_Peripheral:
// Enable pins for SPI0 on PTD0~3
BW_PORT_PCRn_MUX(HW_PORTD, 0, 2); // SPI0_PCS0 is ALT2 for pin PTD0
BW_PORT_PCRn_MUX(HW_PORTD, 1, 2); // SPI0_SCK is ALT2 for pin PTD1
BW_PORT_PCRn_MUX(HW_PORTD, 2, 2); // SPI0_SOUT is ALT2 for pin PTD2
BW_PORT_PCRn_MUX(HW_PORTD, 3, 2); // SPI0_SIN is ALT2 for pin PTD3
break;
default:
break;
}
break;
case 1:
break;
case 2:
break;
default:
break;
}
}
void init_hardware(void)
{
// Disable the MPU otherwise USB cannot access the bus
MPU->CESR = 0;
// Enable all the ports
SIM->SCGC5 |= ( SIM_SCGC5_PORTA_MASK
| SIM_SCGC5_PORTB_MASK
| SIM_SCGC5_PORTC_MASK
| SIM_SCGC5_PORTD_MASK
| SIM_SCGC5_PORTE_MASK );
#if DEBUG && defined(TOWER)
// Enable the pins for the debug UART0
BW_PORT_PCRn_MUX(HW_PORTA, 15, 3); // UART0_RX is PTA15 in ALT3
BW_PORT_PCRn_MUX(HW_PORTA, 14, 3); // UART0_TX is PTA14 in ALT3
#endif // DEBUG && defined(TOWER)
// Update SystemCoreClock. FOPT bits set the OUTDIV1 value.
SystemCoreClock /= (HW_SIM_CLKDIV1.B.OUTDIV1 + 1);
}
/* This function is called for configurating pinmux for uart module
* This function only support switching default or gpio or fixed-ALTx mode on fixed pins
* (Although there are many ALTx-pinmux configuration choices on various pins for the same
* peripheral module) */
void uart_pinmux_config(unsigned int instance, pinmux_type_t pinmux)
{
switch(instance)
{
case 0:
#ifdef FREEDOM
switch(pinmux)
{
case kPinmuxType_Default:
BW_PORT_PCRn_MUX(HW_PORTB, UART0_RX_GPIO_PIN_NUM, 0);
BW_PORT_PCRn_MUX(HW_PORTB, UART0_TX_GPIO_PIN_NUM, 0);
break;
case kPinmuxType_GPIO:
BW_PORT_PCRn_MUX(HW_PORTB, UART0_RX_GPIO_PIN_NUM, UART0_RX_GPIO_ALT_MODE); // Set UART0_RX pin in GPIO mode
HW_GPIO_PDDR_CLR(HW_GPIOB, 1 << UART0_RX_GPIO_PIN_NUM); // Set UART0_RX pin as an input
break;
case kPinmuxType_Peripheral:
BW_PORT_PCRn_MUX(HW_PORTB, UART0_RX_GPIO_PIN_NUM, UART0_RX_ALT_MODE); // Set UART0_RX pin to UART0_RX functionality
BW_PORT_PCRn_MUX(HW_PORTB, UART0_TX_GPIO_PIN_NUM, UART0_TX_ALT_MODE); // Set UART0_TX pin to UART0_TX functionality
break;
default:
break;
}
#endif // FREEDOM
break;
case 1:
#ifdef TOWER
switch(pinmux)
{
case kPinmuxType_Default:
BW_PORT_PCRn_MUX(HW_PORTC, UART1_RX_GPIO_PIN_NUM, 0);
BW_PORT_PCRn_MUX(HW_PORTC, UART1_TX_GPIO_PIN_NUM, 0);
break;
case kPinmuxType_GPIO:
BW_PORT_PCRn_MUX(HW_PORTC, UART1_RX_GPIO_PIN_NUM, UART1_RX_GPIO_ALT_MODE); // Set UART1_RX pin in GPIO mode
HW_GPIO_PDDR_CLR(HW_GPIOC, 1 << UART1_RX_GPIO_PIN_NUM); // Set UART1_RX pin as an input
break;
case kPinmuxType_Peripheral:
BW_PORT_PCRn_MUX(HW_PORTC, UART1_RX_GPIO_PIN_NUM, UART1_RX_ALT_MODE); // Set UART1_RX pin to UART1_RX functionality
BW_PORT_PCRn_MUX(HW_PORTC, UART1_TX_GPIO_PIN_NUM, UART1_TX_ALT_MODE); // Set UART1_TX pin to UART1_TX functionality
break;
default:
break;
}
#endif // TOWER
break;
case 2:
case 3:
case 4:
break;
case 5:
#ifdef TOWER
switch(pinmux)
{
case kPinmuxType_Default:
BW_PORT_PCRn_MUX(HW_PORTE, UART5_RX_GPIO_PIN_NUM, 0);
BW_PORT_PCRn_MUX(HW_PORTE, UART5_TX_GPIO_PIN_NUM, 0);
break;
case kPinmuxType_GPIO:
BW_PORT_PCRn_MUX(HW_PORTE, UART5_RX_GPIO_PIN_NUM, UART5_RX_GPIO_ALT_MODE); // Set UART5_RX pin in GPIO mode
HW_GPIO_PDDR_CLR(HW_GPIOE, 1 << UART5_RX_GPIO_PIN_NUM); // Set UART5_RX pin as an input
break;
case kPinmuxType_Peripheral:
BW_PORT_PCRn_MUX(HW_PORTE, UART5_RX_GPIO_PIN_NUM, UART5_RX_ALT_MODE); // Set UART5_RX pin to UART5_RX functionality
BW_PORT_PCRn_MUX(HW_PORTE, UART5_TX_GPIO_PIN_NUM, UART5_TX_ALT_MODE); // Set UART5_TX pin to UART5_TX functionality
break;
default:
break;
}
#endif // TOWER
break;
default:
break;
}
}
/* This function is called for configurating pinmux for i2c module
* This function only support switching default or gpio or fixed-ALTx mode on fixed pins
* (Although there are many ALTx-pinmux configuration choices on various pins for the same
* peripheral module) */
void i2c_pinmux_config(unsigned int instance, pinmux_type_t pinmux)
{
switch(instance)
{
case 0:
#ifdef TOWER
switch(pinmux)
{
case kPinmuxType_Default:
BW_PORT_PCRn_MUX(HW_PORTD, 8, 0);
BW_PORT_PCRn_MUX(HW_PORTD, 9, 0);
break;
case kPinmuxType_Peripheral:
// Enable pins for I2C0.
BW_PORT_PCRn_MUX(HW_PORTD, 8, 2); // I2C0_SCL is ALT2 for pin PTD8
BW_PORT_PCRn_MUX(HW_PORTD, 9, 2); // I2C0_SDA is ALT2 for pin PTD9
break;
default:
break;
}
#endif // TOWER
switch(pinmux)
{
case kPinmuxType_Default:
BW_PORT_PCRn_MUX(HW_PORTE, 24, 0);
BW_PORT_PCRn_MUX(HW_PORTE, 25, 0);
break;
case kPinmuxType_Peripheral:
// Enable pins for I2C0.
BW_PORT_PCRn_MUX(HW_PORTE, 24, 5); // I2C0_SCL is ALT5 for pin PTE24
BW_PORT_PCRn_ODE(HW_PORTE, 24, true);
BW_PORT_PCRn_MUX(HW_PORTE, 25, 5); // I2C0_SDA is ALT5 for pin PTE25
BW_PORT_PCRn_ODE(HW_PORTE, 25, true);
break;
default:
break;
}
break;
case 1:
#ifdef FREEDOM
switch(pinmux)
{
case kPinmuxType_Default:
BW_PORT_PCRn_MUX(HW_PORTC, 10, 0);
BW_PORT_PCRn_MUX(HW_PORTC, 11, 0);
break;
case kPinmuxType_Peripheral:
// Enable pins for I2C1.
BW_PORT_PCRn_MUX(HW_PORTC, 10, 2); // I2C1_SCL is ALT2 for pin PTC10
BW_PORT_PCRn_MUX(HW_PORTC, 11, 2); // I2C1_SDA is ALT2 for pin PTC11
break;
default:
break;
}
#endif // FREEDOM
break;
case 2:
break;
default:
break;
}
}
static int32_t bsp_usb_otg_io_init
(
int32_t i
)
{
if (i == 0)
{
#if (OS_ADAPTER_ACTIVE_OS == OS_ADAPTER_MQX)
#if BSPCFG_USB_USE_IRC48M
/*
* Configure SIM_CLKDIV2: USBDIV = 0, USBFRAC = 0
*/
//HW_SIM_CLKDIV2_CLR(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK);
SIM_CLKDIV2 &= ~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK);
/* Configure USB to be clocked from IRC 48MHz */
//HW_SIM_SOPT2_SET(SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_IRC48MSEL_MASK);
SIM_SOPT2 |= (SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_IRC48MSEL_MASK);
/* Enable USB-OTG IP clocking */
//HW_SIM_SCGC4_SET(SIM_SCGC4_USBOTG_MASK);
SIM_SCGC4 |= (SIM_SCGC4_USBOTG_MASK);
/* Enable IRC 48MHz for USB module */
USB_CLK_RECOVER_IRC_EN = 0x03;
#else
/* Configure USBFRAC = 0, USBDIV = 0 => frq(USBout) = 1 / 1 * frq(PLLin) */
//HW_SIM_CLKDIV2_CLR(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK);
SIM_CLKDIV2 &= ~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK);
/* Configure USB to be clocked from PLL */
//HW_SIM_SOPT2_SET(SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK);
SIM_SOPT2 |= (SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL(0x01));
/* Enable USB-OTG IP clocking */
//HW_SIM_SCGC4_SET(SIM_SCGC4_USBOTG_MASK);
SIM_SCGC4 |= (SIM_SCGC4_USBOTG_MASK);
#endif
#else
#if BSPCFG_USB_USE_IRC48M
/*
* Configure SIM_CLKDIV2: USBDIV = 0, USBFRAC = 0
*/
HW_SIM_CLKDIV2_CLR(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK);
/* Configure USB to be clocked from IRC 48MHz */
HW_SIM_SOPT2_SET(SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_IRC48MSEL_MASK);
/* Enable USB-OTG IP clocking */
HW_SIM_SCGC4_SET(SIM_SCGC4_USBOTG_MASK);
/* Enable IRC 48MHz for USB module */
USB_CLK_RECOVER_IRC_EN = 0x03;
#else
/* Configure USBFRAC = 0, USBDIV = 0 => frq(USBout) = 1 / 1 * frq(PLLin) */
HW_SIM_CLKDIV2_CLR(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK);
/* Configure USB to be clocked from PLL */
HW_SIM_SOPT2_SET(SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL(0x01));
/* Enable USB-OTG IP clocking */
HW_SIM_SCGC4_SET(SIM_SCGC4_USBOTG_MASK);
#endif
/* Weak pull downs */
HW_USB_USBCTRL_WR(0x40);
#if KHCICFG_HOST_PORT_NATIVE
/* Souce the P5V0_K22_USB. Set PTC9 to high */
BW_PORT_PCRn_MUX(HW_PORTC, 9, 1); /* GPIO mux */
HW_GPIO_PDDR_SET(2, 1<<9); /* Set output */
HW_GPIO_PSOR_SET(2, 1<<9); /* Output high */
#endif
#endif
}
else
{
return -1; /* unknow controller */
}
return 0;
}
