uint32_t twins_state::screen_update_spider(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
{
int y,x,count;
static const int xxx=320,yyy=204;
bitmap.fill(m_palette->black_pen());
count=0;
uint8_t *videoram = (uint8_t*)m_videoram;
for (y=0;y<yyy;y++)
{
for(x=0;x<xxx;x++)
{
bitmap.pix16(y, x) = videoram[BYTE_XOR_LE(count)];
count++;
}
}
count = 0;
videoram = (uint8_t*)m_videoram2;
for (y=0;y<yyy;y++)
{
for(x=0;x<xxx;x++)
{
uint8_t pixel = videoram[BYTE_XOR_LE(count)];
if (pixel) bitmap.pix16(y, x) = pixel;
count++;
}
}
return 0;
}
static WRITE16_HANDLER( arm7_ram_w )
{
pgm_arm_type2_state *state = space.machine().driver_data<pgm_arm_type2_state>();
UINT16 *share16 = reinterpret_cast<UINT16 *>(state->m_arm7_shareram.target());
if (PGMARM7LOGERROR)
logerror("M68K: ARM7 Shared RAM Write: %04x = %04x (%04x) (%06x)\n", BYTE_XOR_LE(offset), data, mem_mask, space.device().safe_pc());
COMBINE_DATA(&share16[BYTE_XOR_LE(offset)]);
}
static READ16_HANDLER( arm7_ram_r )
{
pgm_arm_type2_state *state = space.machine().driver_data<pgm_arm_type2_state>();
UINT16 *share16 = reinterpret_cast<UINT16 *>(state->m_arm7_shareram.target());
if (PGMARM7LOGERROR)
logerror("M68K: ARM7 Shared RAM Read: %04x = %04x (%08x) (%06x)\n", BYTE_XOR_LE(offset), share16[BYTE_XOR_LE(offset)], mem_mask, space.device().safe_pc());
return share16[BYTE_XOR_LE(offset)];
}
/* TTL text plane stuff */
static TILE_GET_INFO( ttl_get_tile_info )
{
rungun_state *state = machine.driver_data<rungun_state>();
UINT8 *lvram = (UINT8 *)state->m_ttl_vram;
int attr, code;
attr = (lvram[BYTE_XOR_LE(tile_index<<2)] & 0xf0) >> 4;
code = ((lvram[BYTE_XOR_LE(tile_index<<2)] & 0x0f) << 8) | (lvram[BYTE_XOR_LE((tile_index<<2)+2)]);
SET_TILE_INFO(state->m_ttl_gfx_index, code, attr, 0);
}
static WRITE8_HANDLER( dallas_share_w )
{
wrally_state *state = space->machine().driver_data<wrally_state>();
UINT8 *shareram = (UINT8 *)state->m_shareram;
shareram[BYTE_XOR_LE(offset) ^ 1] = data;
}
/***************************************************************************
World Rally (c) 1993 Gaelco (Designed & Developed by Zigurat. Produced by Gaelco)
Driver by Manuel Abadia, Mike Coates, Nicola Salmoria and Miguel Andel Horna
Thanks to GAELCO SA for the DS5002FP code and information about the encryption
Main PCB components:
====================
CPUs related:
=============
* 1xDS5002FP @ D12 (Dallas security processor @ 12 MHz)
* 1xHM62256ALFP-8T (32KB NVSRAM) @ C11 (encrypted DS5002FP program code)
* 1xLithium cell
* 2xMS6264A-20NC (16KB SRAM) @ D14 & D15 (shared memory between M68000 & DS5002FP)
* 4x74LS157 (Quad 2 input multiplexer) @ F14, F15, F16 & F17 (used to select M68000 or DS5002FP address bus)
* 4x74LS245 (Octal bus transceiver) @ C14, C15, C16 & C17 (used to store shared RAM data)
* 2x74LS373 (Octal tristate latch) @ D16 & D17 (used by DS5002FP to access data from shared RAM)
* 1xMC68000P12 @ C20 (Motorola 68000 @ 12 MHz)
* 1xOSC24MHz @ B20
* 2xM27C4001 @ C22 & C23 (M68000 program ROMs)
* 1xPAL20L8 @ B23 (handles 1st level M68000 memory map)
0 -> DTACK M68000 data ack
1 -> SELACT
2 -> Input/sound (see below)
3 -> ACTEXT
4 -> SELMOV
5 -> CSW
6 -> CSR
7 -> EXT
* 1x74LS138 (3 to 8 line decoder) @ B13 (handles 2nd level M68000 memory map)
0 -> IN0 DIPSW #1 & #2
1 -> IN1 Joystick 1P & 2P, COINSW, STARTSW
2 -> IN2 Wheel input
3 -> -
4 -> IN4 TESTSW & SERVICESW
5 -> OUT (see below)
6 -> CSBAN OKIM6295 bankswitch
7 -> CSSON OKIM6295 R/W
* 1x74LS259 (8 bit addressable latches) @A7 (handles 3rd level M68000 memory map)
0 -> Coin lockout 1
1 -> Coin lockout 2
2 -> Coin counter 1
3 -> Coin counter 2
4 -> Sound muting
5 -> flip screen
6 -> ENA/D?
7 -> CKA/D?
* 1x16AS @ B15
0 -> OE
1 -> XSRL Shared RAM @ D14
2 -> XSRH Shared RAM @ D15
3 -> SAD Shared Access with DS5002FP
4 -> SRE Shared Access with M68000
5 -> TRANS
6 -> XLD
7 -> XHI
Sound related:
==============
* 1xOKIM6295 @ C6
* 2xM27C4001 @ C1 & C3 (OKI ADPCM samples)
* 1xPAL16R4 @ E2 (handles OKI ROM banking)
Graphics related:
=================
* 1xOSC30MHz @ D5
* 2xTPC1020AFN-84C (FPGA) @ G8 & G13 (GFX processing)
* 2xMS6264A-20NC (8KB SRAM) @ I16 & I17 (Video RAM)
* 4xUM6116BK-25 (2KB SRAM) @ H1, H2, H4 & H5
* 2xUM6116BK-25 (2KB SRAM) @ H22 & H23
Palette related:
================
* 2xMS6264A-20NC (8KB SRAM) @ C8 & C9 (palette RAM (xxxxBBBBRRRRGGGG))
* 2x74HCT273 (octal D-Type flip-flop with clear) @ B8 & B9 (connected to RGB output)
Controls related: (added by Mirko Mattioli)
=================
When optical wheel is selected (via dipswitch), then gear shift (low/high) is enabled.
On the real PCB the optical wheel encoder is connected to 74LS169 ICs (@A16 and @A17)
via a flip-flop IC mounted in the steering wheel assembly. As a result, the output
of the flip-flop generates a signal that contains the information about the steering
direction; this signal is routed to pin #1 (U/D) at ICs A16 and A17 (high when turn
left and low when turn right). The second signal of the optical encoder goes directly
to pin #2 (CLK) at ICs A16 and A17 and it is a clock for the 74LS169 ICs; this clock
frequency is proportional to the movements of the steering wheel: fast movements
produces a high clock frequency, slow movements a low freq.
***************************************************************************/
#include "emu.h"
#include "cpu/m68000/m68000.h"
#include "cpu/mcs51/mcs51.h"
#include "sound/okim6295.h"
#include "includes/wrally.h"
static ADDRESS_MAP_START( wrally_map, AS_PROGRAM, 16, wrally_state )
AM_RANGE(0x000000, 0x0fffff) AM_ROM /* ROM */
AM_RANGE(0x100000, 0x103fff) AM_RAM_WRITE(wrally_vram_w) AM_SHARE("videoram") /* encrypted Video RAM */
AM_RANGE(0x108000, 0x108007) AM_RAM AM_SHARE("vregs") /* Video Registers */
AM_RANGE(0x10800c, 0x10800d) AM_WRITENOP /* CLR INT Video */
AM_RANGE(0x200000, 0x203fff) AM_RAM_WRITE(paletteram_xxxxBBBBRRRRGGGG_word_w) AM_SHARE("paletteram") /* Palette */
AM_RANGE(0x440000, 0x440fff) AM_RAM AM_SHARE("spriteram") /* Sprite RAM */
AM_RANGE(0x700000, 0x700001) AM_READ_PORT("DSW")
AM_RANGE(0x700002, 0x700003) AM_READ_PORT("P1_P2")
AM_RANGE(0x700004, 0x700005) AM_READ_PORT("WHEEL")
AM_RANGE(0x700008, 0x700009) AM_READ_PORT("SYSTEM")
AM_RANGE(0x70000c, 0x70000d) AM_WRITE(OKIM6295_bankswitch_w) /* OKI6295 bankswitch */
AM_RANGE(0x70000e, 0x70000f) AM_DEVREADWRITE8("oki", okim6295_device, read, write, 0x00ff) /* OKI6295 status/data register */
AM_RANGE(0x70000a, 0x70001b) AM_WRITE(wrally_coin_lockout_w) /* Coin lockouts */
AM_RANGE(0x70002a, 0x70003b) AM_WRITE(wrally_coin_counter_w) /* Coin counters */
AM_RANGE(0x70004a, 0x70004b) AM_WRITENOP /* Sound muting */
AM_RANGE(0x70005a, 0x70005b) AM_WRITE(wrally_flipscreen_w) /* Flip screen */
AM_RANGE(0x70006a, 0x70007b) AM_WRITENOP /* ??? */
AM_RANGE(0xfec000, 0xfeffff) AM_RAM AM_SHARE("shareram") /* Work RAM (shared with DS5002FP) */
ADDRESS_MAP_END
READ8_MEMBER(wrally_state::dallas_share_r)
{
UINT8 *shareram = (UINT8 *)m_shareram.target();
return shareram[BYTE_XOR_LE(offset) ^ 1];
}
static READ16_HANDLER( svg_m68k_ram_r )
{
pgm_arm_type3_state *state = space.machine().driver_data<pgm_arm_type3_state>();
int ram_sel = (state->m_svg_ram_sel & 1) ^ 1;
UINT16 *share16 = (UINT16 *)(state->m_svg_shareram[ram_sel & 1]);
return share16[BYTE_XOR_LE(offset)];
}
/***************************************************************************
World Rally (c) 1993 Gaelco (Designed & Developed by Zigurat. Produced by Gaelco)
Driver by Manuel Abadia, Mike Coates, Nicola Salmoria and Miguel Andel Horna
Thanks to GAELCO SA for the DS5002FP code and information about the encryption
Main PCB components:
====================
CPUs related:
=============
* 1xDS5002FP @ D12 (Dallas security processor @ 12 MHz)
* 1xHM62256ALFP-8T (32KB NVSRAM) @ C11 (encrypted DS5002FP program code)
* 1xLithium cell
* 2xMS6264A-20NC (16KB SRAM) @ D14 & D15 (shared memory between M68000 & DS5002FP)
* 4x74LS157 (Quad 2 input multiplexer) @ F14, F15, F16 & F17 (used to select M68000 or DS5002FP address bus)
* 4x74LS245 (Octal bus transceiver) @ C14, C15, C16 & C17 (used to store shared RAM data)
* 2x74LS373 (Octal tristate latch) @ D16 & D17 (used by DS5002FP to access data from shared RAM)
* 1xMC68000P12 @ C20 (Motorola 68000 @ 12 MHz)
* 1xOSC24MHz @ B20
* 2xM27C4001 @ C22 & C23 (M68000 program ROMs)
* 1xPAL20L8 @ B23 (handles 1st level M68000 memory map)
0 -> DTACK M68000 data ack
1 -> SELACT
2 -> Input/sound (see below)
3 -> ACTEXT
4 -> SELMOV
5 -> CSW
6 -> CSR
7 -> EXT
* 1x74LS138 (3 to 8 line decoder) @ B13 (handles 2nd level M68000 memory map)
0 -> IN0 DIPSW #1 & #2
1 -> IN1 Joystick 1P & 2P, COINSW, STARTSW
2 -> IN2 Wheel input
3 -> -
4 -> IN4 TESTSW & SERVICESW
5 -> OUT (see below)
6 -> CSBAN OKIM6295 bankswitch
7 -> CSSON OKIM6295 R/W
* 1x74LS259 (8 bit addressable latches) @A7 (handles 3rd level M68000 memory map)
0 -> Coin lockout 1
1 -> Coin lockout 2
2 -> Coin counter 1
3 -> Coin counter 2
4 -> Sound muting
5 -> flip screen
6 -> ENA/D?
7 -> CKA/D?
* 1x16AS @ B15
0 -> OE
1 -> XSRL Shared RAM @ D14
2 -> XSRH Shared RAM @ D15
3 -> SAD Shared Access with DS5002FP
4 -> SRE Shared Access with M68000
5 -> TRANS
6 -> XLD
7 -> XHI
Sound related:
==============
* 1xOKIM6295 @ C6
* 2xM27C4001 @ C1 & C3 (OKI ADPCM samples)
* 1xPAL16R4 @ E2 (handles OKI ROM banking)
Graphics related:
=================
* 1xOSC30MHz @ D5
* 2xTPC1020AFN-84C (FPGA) @ G8 & G13 (GFX processing)
* 2xMS6264A-20NC (8KB SRAM) @ I16 & I17 (Video RAM)
* 4xUM6116BK-25 (2KB SRAM) @ H1, H2, H4 & H5
* 2xUM6116BK-25 (2KB SRAM) @ H22 & H23
Palette related:
================
* 2xMS6264A-20NC (8KB SRAM) @ C8 & C9 (palette RAM (xxxxBBBBRRRRGGGG))
* 2x74HCT273 (octal D-Type flip-flop with clear) @ B8 & B9 (connected to RGB output)
Controls related: (added by Mirko Mattioli)
=================
When optical wheel is selected (via dipswitch), then gear shift (low/high) is enabled.
On the real PCB the optical wheel encoder is connected to 74LS169 ICs (@A16 and @A17)
via a flip-flop IC mounted in the steering wheel assembly. As a result, the output
of the flip-flop generates a signal that contains the information about the steering
direction; this signal is routed to pin #1 (U/D) at ICs A16 and A17 (high when turn
left and low when turn right). The second signal of the optical encoder goes directly
to pin #2 (CLK) at ICs A16 and A17 and it is a clock for the 74LS169 ICs; this clock
frequency is proportional to the movements of the steering wheel: fast movements
produces a high clock frequency, slow movements a low freq.
***************************************************************************/
#include "driver.h"
#include "cpu/m68000/m68000.h"
#include "cpu/mcs51/mcs51.h"
#include "sound/okim6295.h"
#include "includes/wrally.h"
static UINT16 *wrally_shareram;
static ADDRESS_MAP_START( wrally_map, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x000000, 0x0fffff) AM_ROM /* ROM */
AM_RANGE(0x100000, 0x103fff) AM_READWRITE(SMH_RAM, wrally_vram_w) AM_BASE(&wrally_videoram) /* encrypted Video RAM */
AM_RANGE(0x108000, 0x108007) AM_RAM AM_BASE(&wrally_vregs) /* Video Registers */
AM_RANGE(0x10800c, 0x10800d) AM_WRITENOP /* CLR INT Video */
AM_RANGE(0x200000, 0x203fff) AM_READWRITE(SMH_RAM, paletteram16_xxxxBBBBRRRRGGGG_word_w) AM_BASE(&paletteram16) /* Palette */
AM_RANGE(0x440000, 0x440fff) AM_RAM AM_BASE(&wrally_spriteram) /* Sprite RAM */
AM_RANGE(0x700000, 0x700001) AM_READ_PORT("DSW")
AM_RANGE(0x700002, 0x700003) AM_READ_PORT("P1_P2")
AM_RANGE(0x700004, 0x700005) AM_READ_PORT("WHEEL")
AM_RANGE(0x700008, 0x700009) AM_READ_PORT("SYSTEM")
AM_RANGE(0x70000c, 0x70000d) AM_WRITE(OKIM6295_bankswitch_w) /* OKI6295 bankswitch */
AM_RANGE(0x70000e, 0x70000f) AM_DEVREADWRITE8("oki", okim6295_r, okim6295_w, 0x00ff) /* OKI6295 status/data register */
AM_RANGE(0x70000a, 0x70001b) AM_WRITE(wrally_coin_lockout_w) /* Coin lockouts */
AM_RANGE(0x70002a, 0x70003b) AM_WRITE(wrally_coin_counter_w) /* Coin counters */
AM_RANGE(0x70004a, 0x70004b) AM_WRITENOP /* Sound muting */
AM_RANGE(0x70005a, 0x70005b) AM_WRITE(wrally_flipscreen_w) /* Flip screen */
AM_RANGE(0x70006a, 0x70007b) AM_WRITENOP /* ??? */
AM_RANGE(0xfec000, 0xfeffff) AM_RAM AM_BASE(&wrally_shareram) /* Work RAM (shared with DS5002FP) */
ADDRESS_MAP_END
static READ8_HANDLER( dallas_share_r )
{
UINT8 *shareram = (UINT8 *)wrally_shareram;
return shareram[BYTE_XOR_LE(offset) ^ 1];
}
static WRITE16_HANDLER( svg_m68k_ram_w )
{
pgm_arm_type3_state *state = space.machine().driver_data<pgm_arm_type3_state>();
int ram_sel = (state->m_svg_ram_sel & 1) ^ 1;
UINT16 *share16 = (UINT16 *)(state->m_svg_shareram[ram_sel & 1]);
COMBINE_DATA(&share16[BYTE_XOR_LE(offset)]);
}
static void configure_memory_16bit(i8086_state *cpustate)
{
cpustate->mem.fetch_xor = BYTE_XOR_LE(0);
cpustate->mem.rbyte = memory_read_byte_16le;
cpustate->mem.rword = read_word_16le;
cpustate->mem.wbyte = memory_write_byte_16le;
cpustate->mem.wword = write_word_16le;
}
/***************************************************************************
World Rally (c) 1993 Gaelco (Designed & Developed by Zigurat. Produced by Gaelco)
Driver by Manuel Abadia, Mike Coates, Nicola Salmoria and Miguel Andel Horna
Thanks to GAELCO SA for the DS5002FP code and information about the encryption
Main PCB components:
====================
CPUs related:
=============
* 1xDS5002FP @ D12 (Dallas security processor @ 12 MHz)
* 1xHM62256ALFP-8T (32KB NVSRAM) @ C11 (encrypted DS5002FP program code)
* 1xLithium cell
* 2xMS6264A-20NC (16KB SRAM) @ D14 & D15 (shared memory between M68000 & DS5002FP)
* 4x74LS157 (Quad 2 input multiplexer) @ F14, F15, F16 & F17 (used to select M68000 or DS5002FP address bus)
* 4x74LS245 (Octal bus transceiver) @ C14, C15, C16 & C17 (used to store shared RAM data)
* 2x74LS373 (Octal tristate latch) @ D16 & D17 (used by DS5002FP to access data from shared RAM)
* 1xMC68000P12 @ C20 (Motorola 68000 @ 12 MHz)
* 1xOSC24MHz @ B20
* 2xM27C4001 @ C22 & C23 (M68000 program ROMs)
* 1xPAL20L8 @ B23 (handles 1st level M68000 memory map)
0 -> DTACK M68000 data ack
1 -> SELACT
2 -> Input/sound (see below)
3 -> ACTEXT
4 -> SELMOV
5 -> CSW
6 -> CSR
7 -> EXT
* 1x74LS138 (3 to 8 line decoder) @ B13 (handles 2nd level M68000 memory map)
0 -> IN0 DIPSW #1 & #2
1 -> IN1 Joystick 1P & 2P, COINSW, STARTSW
2 -> IN2 Wheel input
3 -> -
4 -> IN4 TESTSW & SERVICESW
5 -> OUT (see below)
6 -> CSBAN OKIM6295 bankswitch
7 -> CSSON OKIM6295 R/W
* 1x74LS259 (8 bit addressable latches) @A7 (handles 3rd level M68000 memory map)
0 -> Coin lockout 1
1 -> Coin lockout 2
2 -> Coin counter 1
3 -> Coin counter 2
4 -> Sound muting
5 -> flip screen
6 -> ENA/D?
7 -> CKA/D?
* 1x16AS @ B15
0 -> OE
1 -> XSRL Shared RAM @ D14
2 -> XSRH Shared RAM @ D15
3 -> SAD Shared Access with DS5002FP
4 -> SRE Shared Access with M68000
5 -> TRANS
6 -> XLD
7 -> XHI
Sound related:
==============
* 1xOKIM6295 @ C6
* 2xM27C4001 @ C1 & C3 (OKI ADPCM samples)
* 1xPAL16R4 @ E2 (handles OKI ROM banking)
Graphics related:
=================
* 1xOSC30MHz @ D5
* 2xTPC1020AFN-84C (FPGA) @ G8 & G13 (GFX processing)
* 2xMS6264A-20NC (8KB SRAM) @ I16 & I17 (Video RAM)
* 4xUM6116BK-25 (2KB SRAM) @ H1, H2, H4 & H5
* 2xUM6116BK-25 (2KB SRAM) @ H22 & H23
Palette related:
================
* 2xMS6264A-20NC (8KB SRAM) @ C8 & C9 (palette RAM (xxxxBBBBRRRRGGGG))
* 2x74HCT273 (octal D-Type flip-flop with clear) @ B8 & B9 (connected to RGB output)
Controls related: (added by Mirko Mattioli)
=================
When optical wheel is selected (via dipswitch), then gear shift (low/high) is enabled.
On the real PCB the optical wheel encoder is connected to 74LS169 ICs (@A16 and @A17)
via a flip-flop IC mounted in the steering wheel assembly. As a result, the output
of the flip-flop generates a signal that contains the information about the steering
direction; this signal is routed to pin #1 (U/D) at ICs A16 and A17 (high when turn
left and low when turn right). The second signal of the optical encoder goes directly
to pin #2 (CLK) at ICs A16 and A17 and it is a clock for the 74LS169 ICs; this clock
frequency is proportional to the movements of the steering wheel: fast movements
produces a high clock frequency, slow movements a low freq.
***************************************************************************/
#include "emu.h"
#include "cpu/m68000/m68000.h"
#include "cpu/mcs51/mcs51.h"
#include "sound/okim6295.h"
#include "includes/wrally.h"
static ADDRESS_MAP_START( wrally_map, AS_PROGRAM, 16 )
AM_RANGE(0x000000, 0x0fffff) AM_ROM /* ROM */
AM_RANGE(0x100000, 0x103fff) AM_RAM_WRITE(wrally_vram_w) AM_BASE_MEMBER(wrally_state, m_videoram) /* encrypted Video RAM */
AM_RANGE(0x108000, 0x108007) AM_RAM AM_BASE_MEMBER(wrally_state, m_vregs) /* Video Registers */
AM_RANGE(0x10800c, 0x10800d) AM_WRITENOP /* CLR INT Video */
AM_RANGE(0x200000, 0x203fff) AM_RAM_WRITE(paletteram16_xxxxBBBBRRRRGGGG_word_w) AM_BASE_GENERIC(paletteram) /* Palette */
AM_RANGE(0x440000, 0x440fff) AM_RAM AM_BASE_MEMBER(wrally_state, m_spriteram) /* Sprite RAM */
AM_RANGE(0x700000, 0x700001) AM_READ_PORT("DSW")
AM_RANGE(0x700002, 0x700003) AM_READ_PORT("P1_P2")
AM_RANGE(0x700004, 0x700005) AM_READ_PORT("WHEEL")
AM_RANGE(0x700008, 0x700009) AM_READ_PORT("SYSTEM")
AM_RANGE(0x70000c, 0x70000d) AM_WRITE(OKIM6295_bankswitch_w) /* OKI6295 bankswitch */
AM_RANGE(0x70000e, 0x70000f) AM_DEVREADWRITE8_MODERN("oki", okim6295_device, read, write, 0x00ff) /* OKI6295 status/data register */
AM_RANGE(0x70000a, 0x70001b) AM_WRITE(wrally_coin_lockout_w) /* Coin lockouts */
AM_RANGE(0x70002a, 0x70003b) AM_WRITE(wrally_coin_counter_w) /* Coin counters */
AM_RANGE(0x70004a, 0x70004b) AM_WRITENOP /* Sound muting */
AM_RANGE(0x70005a, 0x70005b) AM_WRITE(wrally_flipscreen_w) /* Flip screen */
AM_RANGE(0x70006a, 0x70007b) AM_WRITENOP /* ??? */
AM_RANGE(0xfec000, 0xfeffff) AM_RAM AM_BASE_MEMBER(wrally_state, m_shareram) /* Work RAM (shared with DS5002FP) */
ADDRESS_MAP_END
static READ8_HANDLER( dallas_share_r )
{
wrally_state *state = space->machine().driver_data<wrally_state>();
UINT8 *shareram = (UINT8 *)state->m_shareram;
return shareram[BYTE_XOR_LE(offset) ^ 1];
}
static CPU_INIT( v30 )
{
nec_state_t *nec_state = get_safe_token(device);
nec_init(device, irqcallback);
nec_state->fetch_xor = BYTE_XOR_LE(0);
nec_state->chip_type=V30_TYPE;
nec_state->prefetch_size = 6; /* 3 words */
nec_state->prefetch_cycles = 2; /* two cycles per byte / four per word */
}
// Only share the sound work area
static READ16_HANDLER( c7x_shared_r )
{
UINT16 *share16 = (UINT16 *)namcoc7x_hostram;
if (offset >= 0x400/2)
{
return namcoc7x_mcuram[offset];
}
return share16[BYTE_XOR_LE(offset)];
}
v60_device::v60_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: cpu_device(mconfig, V60, "V60", tag, owner, clock, "v60", __FILE__)
, m_program_config("program", ENDIANNESS_LITTLE, 16, 24, 0)
, m_io_config("io", ENDIANNESS_LITTLE, 16, 24, 0)
, m_fetch_xor(BYTE_XOR_LE(0))
, m_start_pc(0xfffff0)
{
// Set m_PIR (Processor ID) for NEC m_ LSB is reserved to NEC,
// so I don't know what it contains.
m_reg[45] = 0x00006000;
}
static WRITE16_HANDLER( c7x_shared_w )
{
UINT16 *share16 = (UINT16 *)namcoc7x_hostram;
if (offset >= 0x400/2)
{
COMBINE_DATA(&namcoc7x_mcuram[offset]);
}
else
{
COMBINE_DATA(&share16[BYTE_XOR_LE(offset)]);
}
}
int v25_read_byte(v25_state_t *nec_state, unsigned a)
{
unsigned page = a >> 8;
unsigned offs = a & 0xff;
if(RAMEN && page == (nec_state->IDB << 4 | 0xE))
return nec_state->ram.b[BYTE_XOR_LE(offs)];
if(a == 0xFFFFF || page == (nec_state->IDB << 4 | 0xF))
return read_sfr(nec_state, offs);
return nec_state->program->read_byte(a);
}
static CPU_INIT( v33 )
{
nec_state_t *nec_state = get_safe_token(device);
nec_init(device, irqcallback);
nec_state->chip_type=V33_TYPE;
nec_state->prefetch_size = 6;
/* FIXME: Need information about prefetch size and cycles for V33.
* complete guess below, nbbatman will not work
* properly without. */
nec_state->prefetch_cycles = 1; /* two cycles per byte / four per word */
nec_state->fetch_xor = BYTE_XOR_LE(0);
}
void v25_write_byte(v25_state_t *nec_state, unsigned a, unsigned d)
{
unsigned page = a >> 8;
unsigned offs = a & 0xff;
if(RAMEN && page == (nec_state->IDB << 4 | 0xE))
{
nec_state->ram.b[BYTE_XOR_LE(offs)] = d;
return;
}
if(a == 0xFFFFF || page == (nec_state->IDB << 4 | 0xF))
{
write_sfr(nec_state, offs, d);
return;
}
nec_state->program->write_byte(a, d);
}
UINT32 ttchamp_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
{
logerror("update\n");
int y,x,count;
static const int xxx=320,yyy=204;
bitmap.fill(m_palette->black_pen());
UINT8 *videoramfg;
UINT8* videorambg;
count=0;
videorambg = (UINT8*)m_videoram0;
videoramfg = (UINT8*)m_videoram2;
for (y=0;y<yyy;y++)
{
for(x=0;x<xxx;x++)
{
bitmap.pix16(y, x) = videorambg[BYTE_XOR_LE(count)]+0x300;
count++;
}
}
/*
count=0;
videoram = (UINT8*)m_videoram1;
for (y=0;y<yyy;y++)
{
for(x=0;x<xxx;x++)
{
UINT8 pix = videoram[BYTE_XOR_LE(count)];
if (pix) bitmap.pix16(y, x) = pix+0x200;
count++;
}
}
*/
count=0;
for (y=0;y<yyy;y++)
{
for(x=0;x<xxx;x++)
{
UINT8 pix = videoramfg[BYTE_XOR_LE(count)];
if (pix)
{
// first pen values seem to be special
// see char select and shadows ingame
// pen 0 = transparent
// pen 1 = blend 1
// pen 2 = blend 2
// pen 3 = ??
if (pix == 0x01) // blend mode 1
{
UINT8 pix = videorambg[BYTE_XOR_LE(count)];
bitmap.pix16(y, x) = pix + 0x200;
}
else if (pix == 0x02) // blend mode 2
{
UINT8 pix = videorambg[BYTE_XOR_LE(count)];
bitmap.pix16(y, x) = pix + 0x100;
}
else
{
bitmap.pix16(y, x) = pix + 0x000;
}
}
count++;
}
}
#if 0
for (int i = 0; i < 0x8000; i++)
{
// how are layers cleared?
// I think it actually does more blit operations with
// different bits of m_port10 set to redraw the backgrounds using the video ram data as a source rather than ROM - notice the garbage you see behind 'sprites' right now
// this method also removes the text layer, which we don't want
// m_videoram1[i] = 0x0000;
// m_videoram2[i] = 0x0000;
}
#endif
return 0;
}
offs_t activecpu_dasm(char *buffer, offs_t pc)
{
VERIFY_ACTIVECPU(activecpu_dasm);
/* allow overrides */
if (cpu_dasm_override)
{
offs_t result = cpu_dasm_override(activecpu, buffer, pc);
if (result)
return result;
}
/* if there's no old-style assembler, do some work to make this call work with the new one */
if (!cpu[activecpu].intf.disassemble)
{
int dbwidth = activecpu_databus_width(ADDRESS_SPACE_PROGRAM);
int maxbytes = activecpu_max_instruction_bytes();
int endianness = activecpu_endianness();
UINT8 opbuf[64], argbuf[64];
int xorval = 0;
int numbytes;
/* determine the XOR to get the bytes in order */
switch (dbwidth)
{
case 8: xorval = 0; break;
case 16: xorval = (endianness == CPU_IS_LE) ? BYTE_XOR_LE(0) : BYTE_XOR_BE(0); break;
case 32: xorval = (endianness == CPU_IS_LE) ? BYTE4_XOR_LE(0) : BYTE4_XOR_BE(0); break;
case 64: xorval = (endianness == CPU_IS_LE) ? BYTE8_XOR_LE(0) : BYTE8_XOR_BE(0); break;
}
/* fetch the bytes up to the maximum */
memset(opbuf, 0xff, sizeof(opbuf));
memset(argbuf, 0xff, sizeof(argbuf));
for (numbytes = 0; numbytes < maxbytes; numbytes++)
{
offs_t physpc = pc + numbytes;
const UINT8 *ptr;
/* translate the address, set the opcode base, and apply the byte xor */
if (!cpu[activecpu].intf.translate || (*cpu[activecpu].intf.translate)(ADDRESS_SPACE_PROGRAM, &physpc))
{
memory_set_opbase(physpc);
physpc ^= xorval;
/* get pointer to data */
ptr = memory_get_op_ptr(cpu_getactivecpu(), physpc, 0);
if (ptr)
{
opbuf[numbytes] = *ptr;
ptr = memory_get_op_ptr(cpu_getactivecpu(), physpc, 1);
if (ptr)
argbuf[numbytes] = *ptr;
else
argbuf[numbytes] = opbuf[numbytes];
}
}
}
return activecpu_dasm_new(buffer, pc, opbuf, argbuf, maxbytes);
}
return (*cpu[activecpu].intf.disassemble)(buffer, pc);
}
INLINE UINT8 psxreadbyte( UINT32 n_address )
{
return m_p_n_ram[ BYTE_XOR_LE( n_address ) ];
}
UINT32 memory_array::read8_from_16le(int index) { return reinterpret_cast<UINT8 *>(m_base)[BYTE_XOR_LE(index)]; }
static WRITE8_HANDLER( dallas_share_w )
{
UINT8 *shareram = (UINT8 *)wrally_shareram;
shareram[BYTE_XOR_LE(offset) ^ 1] = data;
}
void memory_array::write8_to_16le(int index, UINT32 data) { reinterpret_cast<UINT8 *>(m_base)[BYTE_XOR_LE(index)] = data; }
v33a_device::v33a_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: nec_common_device(mconfig, V33A, "V33A", tag, owner, clock, "v33A", __FILE__, true, BYTE_XOR_LE(0), 6, 1, V33_TYPE)
{
}
v53a_device::v53a_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: v53_base_device(mconfig, V53A, "V53A", tag, owner, clock, "v53a", BYTE_XOR_LE(0), 6, 1, V33_TYPE)
{
}