/**
* ============================================================================
* @n@b Osal_cppiEndMemAccess
*
* @b brief
* @n The function is used to indicate that the block of memory has
* finished being accessed. If the memory block is cached then the
* application would need to ensure that the contents of the cache
* are updated immediately to the actual memory.
*
* @param[in] ptr
* Address of memory block
*
* @param[in] size
* Size of memory block
* @retval
* Not Applicable
* =============================================================================
*/
void Osal_cppiEndMemAccess (void *ptr, uint32_t size)
{
/* Recommended sequence for cache operations is:
* 1) Disable all interrupts
* 2) Perform the cache block operation
* 3) Wait until the cache operation is done either by polling
* the corresponding WC register or using _mfence ()
* instruction.
* 4) Enable interrupts back.
*/
/* Disable all interrupts */
Osal_biosInterruptCsEnter ();
/* Writeback L1D cache and wait until operation is complete.
* Use this approach if L2 cache is not enabled
*/
CACHE_wbL1d (ptr, size, CACHE_FENCE_WAIT);
/* Writeback L2 cache. This should Writeback L1D as well.
* Wait until operation is complete.
*/
/* CACHE_wbL2 (ptr, size, CACHE_FENCE_WAIT); */
/* Enable back interrupts */
Osal_biosInterruptCsExit ();
return;
}
/**
* @b Description
* @n
* The function is used by the SRIO driver to indicate that its
* ending access to a block of memory. We need to ensure that the
* contents of the cache are written back to the actual memory.
*
* @param[in] ptr
* Pointer to the buffer
* @param[in] size
* Size of the buffer
*
* @retval
* None
*/
void Osal_srioEndMemAccess(void* ptr, uint32_t size)
{
#if 0
CACHE_wbL1d (ptr, size, CACHE_WAIT);
_mfence();
#else
UInt key;
/* Disable Interrupts */
key = Hwi_disable();
/* Writeback the cache. */
CACHE_wbL1d (ptr, size, CACHE_FENCE_WAIT);
/* Reenable Interrupts. */
Hwi_restore(key);
#endif
}
/**
* @b Description
* @n
* The function is used to indicate that the block of memory has
* finished being accessed. If the memory block is cached then the
* application would need to ensure that the contents of the cache
* are updated immediately to the actual memory.
*
* @param[in] ptr
* Address of memory block
* @param[in] size
* Size of memory block
*
* @retval
* Not Applicable
*/
void Osal_qmssEndMemAccess (void *ptr, uint32_t size)
{
#if 0
/* Writeback L1D cache and wait until operation is complete.
* Use this approach if L2 cache is not enabled */
CACHE_wbL1d (ptr, size, CACHE_WAIT);
_mfence();
#else
UInt key;
/* Disable Interrupts */
key = Hwi_disable();
/* Writeback the contents of the cache. */
CACHE_wbL1d (ptr, size, CACHE_FENCE_WAIT);
/* Reenable Interrupts. */
Hwi_restore(key);
#endif
}
