_ramfunc uint32_t CGU_Init(void)
{
__disable_irq();
MemoryPinInit(); // Make sure EMC is in high-speed pin mode
/* Set the XTAL oscillator frequency to 12MHz*/
CGU_SetXTALOSC(12000000);
CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE);
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_SPIFI);
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_M3);
/* Set PL160M 12*1 = 12 MHz */
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1);
CGU_SetPLL1(1);
CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE);
/* Run SPIFI from PL160M, /2 */
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_CLKSRC_IDIVA);
CGU_EnableEntity(CGU_CLKSRC_IDIVA, ENABLE);
CGU_SetDIV(CGU_CLKSRC_IDIVA, 2); // This gets adjusted in spi_flash.c to slow the clock when writing
CGU_EntityConnect(CGU_CLKSRC_IDIVA, CGU_BASE_SPIFI);
CGU_UpdateClock();
LPC_CCU1->CLK_M3_EMCDIV_CFG |= (1<<0) | (1<<5); // Turn on clock / 2
LPC_CREG->CREG6 |= (1<<16); // EMC divided by 2
LPC_CCU1->CLK_M3_EMC_CFG |= (1<<0); // Turn on clock
/* Set PL160M @ 12*9=108 MHz */
CGU_SetPLL1(9);
/* Run base M3 clock from PL160M, no division */
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M3);
emc_WaitMS(30);
/* Change the clock to 180 MHz */
/* Set PL160M @ 12*15=180 MHz */
CGU_SetPLL1(15);
emc_WaitMS(30);
CGU_UpdateClock();
emc_WaitMS(10);
__enable_irq();
return 0;
}
_ramfunc void spiflash_mem_mode() {
// WRR CF1 to enable quad and set latency cycles
spiflash_wait();
spiflash_write_enable();
uint8_t buf[2] = {0, (SPIFI_CR1_QUAD)};
spifi_cmd(0x01, SPIFI_FRAMEFORM_0, 0, true, 2, buf);
// timeout CS high time fbclk
LPC_SPIFI->CTRL = (0xffff << 0) | (0x1 << 16) | (1 << 30);
LPC_SPIFI->DATINTM = 0;
LPC_SPIFI->MEMCMD = (0xEC << 24) | SPIFI_FRAMEFORM_4 | SPIFI_FIELDFORM_SERIAL_OPCODE | ((2 + 1) << 16);
while (!(LPC_SPIFI->STAT & SPIFI_STATUS_MCINIT));
// Execute some instructions, or it crashes when jumping to flash...
volatile unsigned j=100000;
while (j--);
CGU_SetDIV(CGU_CLKSRC_IDIVA, 2); // Fast SPIFI clock
}
void clockInit(void)
{
//uint32_t EMCClk;
__disable_irq();
/* Set the XTAL oscillator frequency to 12MHz*/
CGU_SetXTALOSC(__CRYSTAL);
CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE);
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_M3);
/* Set PL160M 12*1 = 12 MHz */
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1);
// CGU_EntityConnect(CGU_CLKSRC_IRC, CGU_CLKSRC_PLL1);
CGU_SetPLL1(1);
CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE);
// setup CLKOUT
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_CLKSRC_IDIVB);
CGU_EnableEntity(CGU_CLKSRC_IDIVB, ENABLE);
CGU_SetDIV(CGU_CLKSRC_IDIVB, 12); // 12 -> 6 pclks per cpu clk, 10 -> 5 pclks
// set input for CLKOUT to IDIVB
LPC_CGU->BASE_OUT_CLK &= ~0x0f000000;
LPC_CGU->BASE_OUT_CLK |= 0x0d000000;
/* Run SPIFI from PL160M, /2 */
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_CLKSRC_IDIVA);
CGU_EnableEntity(CGU_CLKSRC_IDIVA, ENABLE);
CGU_SetDIV(CGU_CLKSRC_IDIVA, 2);
CGU_EntityConnect(CGU_CLKSRC_IDIVA, CGU_BASE_SPIFI);
CGU_UpdateClock();
LPC_CCU1->CLK_M4_EMCDIV_CFG |= (1<<0) | (1<<5); // Turn on clock / 2
LPC_CREG->CREG6 |= (1<<16); // EMC divided by 2
LPC_CCU1->CLK_M4_EMC_CFG |= (1<<0); // Turn on clock
/* Set PL160M @ 12*9=108 MHz */
CGU_SetPLL1(9);
/* Run base M3 clock from PL160M, no division */
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M3);
waitMS(10);
/* Change the clock to 204 MHz */
/* Set PL160M @ 12*15=180 MHz */
CGU_SetPLL1(17);
waitMS(10);
CGU_UpdateClock();
//EMCFlashInit();
//vEMC_InitSRDRAM(SDRAM_BASE_ADDR, SDRAM_WIDTH, SDRAM_SIZE_MBITS, SDRAM_DATA_BUS_BITS, SDRAM_COL_ADDR_BITS);
LPC_SCU->SFSP3_3 = 0xF3; /* high drive for SCLK */
/* IO pins */
LPC_SCU->SFSP3_4=LPC_SCU->SFSP3_5=LPC_SCU->SFSP3_6=LPC_SCU->SFSP3_7 = 0xD3;
LPC_SCU->SFSP3_8 = 0x13; /* CS doesn't need feedback */
#if 0
EMCClk = CGU_GetPCLKFrequency(CGU_PERIPHERAL_M3CORE)/2;
if (spifi_init(&sobj, 9, S_RCVCLK | S_FULLCLK, EMCClk)) {
if (spifi_init(&sobj, 9, S_RCVCLK | S_FULLCLK, EMCClk)) {
while(1);
}
}
#endif
__enable_irq();
// SPIFI_Init();
}
/// Reset into cmd mode
_ramfunc void spifi_reset() {
CGU_SetDIV(CGU_CLKSRC_IDIVA, 4); // Slow SPIFI clock
LPC_SPIFI->STAT = SPIFI_STATUS_RESET;
while(LPC_SPIFI->STAT & SPIFI_STATUS_RESET);
}
