&twi_clk, &spi0_clk, &spi1_clk, &ssc0_clk, &ssc1_clk, &ssc2_clk, &tc0_clk, &tc1_clk, &tc2_clk, &ohci_clk, &lcdc_clk, // irq0 .. irq2 }; static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk), CLKDEV_DEV_ID("at91rm9200-gpio0", &pioA_clk), CLKDEV_DEV_ID("at91rm9200-gpio1", &pioB_clk), CLKDEV_DEV_ID("at91rm9200-gpio2", &pioC_clk), CLKDEV_DEV_ID("at91-pit", &mck), }; static struct clk_lookup usart_clocks_lookups[] = { CLKDEV_CON_DEV_ID("usart", "atmel_usart0", &mck), CLKDEV_CON_DEV_ID("usart", "atmel_usart1", &usart0_clk), CLKDEV_CON_DEV_ID("usart", "atmel_usart2", &usart1_clk), CLKDEV_CON_DEV_ID("usart", "atmel_usart3", &usart2_clk), }; /*
&tcb_clk, &pwm_clk, &macb_clk, &twodge_clk, &udc_clk, &isi_clk, &lcdc_clk, &dma_clk, &ohci_clk, // irq0 .. irq1 }; static struct clk_lookup periph_clocks_lookups[] = { /* One additional fake clock for macb_hclk */ CLKDEV_CON_ID("hclk", &macb_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk), CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk), /* fake hclk clock */ CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), CLKDEV_CON_ID("pioA", &pioA_clk), CLKDEV_CON_ID("pioB", &pioB_clk), CLKDEV_CON_ID("pioC", &pioCDE_clk), CLKDEV_CON_ID("pioD", &pioCDE_clk), CLKDEV_CON_ID("pioE", &pioCDE_clk), /* more usart lookup table for DT entries */ CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck),
&ac97_clk, &macb_clk, &isi_clk, &udphs_clk, &mmc1_clk, &adc_op_clk, &aestdessha_clk, // irq0 }; static struct clk_lookup periph_clocks_lookups[] = { /* One additional fake clock for macb_hclk */ CLKDEV_CON_ID("hclk", &macb_clk), /* One additional fake clock for ohci */ CLKDEV_CON_ID("ohci_clk", &uhphs_clk), CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk), CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk), CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk), CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk), CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk), CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk), CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk), CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi0_clk), CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.1", &twi1_clk), CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.0", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "at91sam9g45_ssc.1", &ssc1_clk), CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc0_clk),
&tcb_clk, &pwm_clk, &macb_clk, &twodge_clk, &udc_clk, &isi_clk, &lcdc_clk, &dma_clk, &ohci_clk, // irq0 .. irq1 }; static struct clk_lookup periph_clocks_lookups[] = { /* One additional fake clock for macb_hclk */ CLKDEV_CON_ID("hclk", &macb_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.0", &mmc0_clk), CLKDEV_CON_DEV_ID("mci_clk", "at91_mci.1", &mmc1_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk), /* fake hclk clock */ CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), CLKDEV_CON_ID("pioA", &pioA_clk), CLKDEV_CON_ID("pioB", &pioB_clk), CLKDEV_CON_ID("pioC", &pioCDE_clk), CLKDEV_CON_ID("pioD", &pioCDE_clk), CLKDEV_CON_ID("pioE", &pioCDE_clk), };
&ssc0_clk, &ssc1_clk, &ssc2_clk, &tc0_clk, &tc1_clk, &tc2_clk, &tc3_clk, &tc4_clk, &tc5_clk, &ohci_clk, ðer_clk, // irq0 .. irq6 }; static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk), CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk), CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk), CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk), CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk), CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk), CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk), CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200.0", &twi_clk), /* fake hclk clock */ CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), CLKDEV_CON_ID("pioA", &pioA_clk), CLKDEV_CON_ID("pioB", &pioB_clk), CLKDEV_CON_ID("pioC", &pioC_clk), CLKDEV_CON_ID("pioD", &pioD_clk),
&pwm_clk, &tsc_clk, &dma_clk, &uhphs_clk, &lcdc_clk, &ac97_clk, &macb_clk, &isi_clk, &udphs_clk, &mmc1_clk, }; static struct clk_lookup periph_clocks_lookups[] = { /* One additional fake clock for ohci */ CLKDEV_CON_ID("ohci_clk", &uhphs_clk), CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk), CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci0", &mmc0_clk), CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci1", &mmc1_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi1", &spi1_clk), CLKDEV_DEV_ID("at91-pit", &mck), CLKDEV_CON_DEV_ID("hck1", "atmel_lcdfb", &lcdc_clk), }; static struct clk_lookup usart_clocks_lookups[] = { CLKDEV_CON_DEV_ID("usart", "atmel_usart0", &mck), CLKDEV_CON_DEV_ID("usart", "atmel_usart1", &usart0_clk), CLKDEV_CON_DEV_ID("usart", "atmel_usart2", &usart1_clk), CLKDEV_CON_DEV_ID("usart", "atmel_usart3", &usart2_clk), CLKDEV_CON_DEV_ID("usart", "atmel_usart4", &usart3_clk), };
&ssc0_clk, &ssc1_clk, &ssc2_clk, &tc0_clk, &tc1_clk, &tc2_clk, &tc3_clk, &tc4_clk, &tc5_clk, &ohci_clk, ðer_clk, // irq0 .. irq6 }; static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk), CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk), CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk), CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk), CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk), CLKDEV_CON_DEV_ID("ssc", "ssc.0", &ssc0_clk), CLKDEV_CON_DEV_ID("ssc", "ssc.1", &ssc1_clk), CLKDEV_CON_DEV_ID("ssc", "ssc.2", &ssc2_clk), }; static struct clk_lookup usart_clocks_lookups[] = { CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck), CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk), CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk), CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),
&tc4_clk, &tc5_clk, &ohci_clk, ðer_clk, // irq0 .. irq6 }; static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_DEV_ID("at91rm9200-gpio0", &pioA_clk), CLKDEV_DEV_ID("at91rm9200-gpio1", &pioB_clk), CLKDEV_DEV_ID("at91rm9200-gpio2", &pioC_clk), CLKDEV_DEV_ID("at91rm9200-gpio3", &pioD_clk), }; static struct clk_lookup usart_clocks_lookups[] = { CLKDEV_CON_DEV_ID("usart", "atmel_usart0", &mck), CLKDEV_CON_DEV_ID("usart", "atmel_usart1", &usart0_clk), CLKDEV_CON_DEV_ID("usart", "atmel_usart2", &usart1_clk), CLKDEV_CON_DEV_ID("usart", "atmel_usart3", &usart2_clk), CLKDEV_CON_DEV_ID("usart", "atmel_usart4", &usart3_clk), }; /* * The four programmable clocks. * You must configure pin multiplexing to bring these signals out. */ static struct clk pck0 = { .name = "pck0", .pmc_mask = AT91_PMC_PCK0, .type = CLK_TYPE_PROGRAMMABLE, .id = 0,
&tsc_clk, &dma_clk, &uhphs_clk, &lcdc_clk, &ac97_clk, &macb_clk, &isi_clk, &udphs_clk, &mmc1_clk, // irq0 }; static struct clk_lookup periph_clocks_lookups[] = { /* One additional fake clock for ohci */ CLKDEV_CON_ID("ohci_clk", &uhphs_clk), CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk), CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk), CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk), CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk), CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), }; static struct clk_lookup usart_clocks_lookups[] = { CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck), CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
&uart0_clk, &uart1_clk, &tcb_clk, &pwm_clk, &adc_clk, &dma_clk, &uhp_clk, &udp_clk, &ssc_clk, &aes_clk, &sha_clk, }; static struct clk_lookup periph_clocks_lookups[] = { /* lookup table for DT entries */ CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck), CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk), CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk), CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk), CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk), CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb_clk), CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb_clk), CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc_clk), CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk), CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk), CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk), CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk), CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk), CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk), CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioCD_clk), CLKDEV_CON_DEV_ID("aes_clk", "f000c000.aes", &aes_clk),
.name = "pck1", .pmc_mask = AT91_PMC_PCK1, .type = CLK_TYPE_PROGRAMMABLE, .id = 1, }; static struct clk pck2 = { .name = "pck2", .pmc_mask = AT91_PMC_PCK2, .type = CLK_TYPE_PROGRAMMABLE, .id = 2, }; static struct clk_lookup periph_clocks_lookups[] = { /* lookup table for DT entries */ CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck), CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk), CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk), CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk), CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioD_clk), CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioE_clk), CLKDEV_CON_DEV_ID("usart", "f001c000.serial", &usart0_clk), CLKDEV_CON_DEV_ID("usart", "f0020000.serial", &usart1_clk), CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart2_clk), CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart3_clk), CLKDEV_CON_DEV_ID("usart", "f0024000.serial", &uart0_clk), CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &uart1_clk), CLKDEV_CON_DEV_ID(NULL, "f0014000.i2c", &twi0_clk), CLKDEV_CON_DEV_ID(NULL, "f0018000.i2c", &twi1_clk), CLKDEV_CON_DEV_ID(NULL, "f801c000.i2c", &twi2_clk), CLKDEV_CON_DEV_ID("mci_clk", "f0000000.mmc", &mmc0_clk),
&uhphs_clk, &lcdc_clk, &ac97_clk, &macb_clk, &isi_clk, &udphs_clk, &mmc1_clk, // }; static struct clk_lookup periph_clocks_lookups[] = { /* */ CLKDEV_CON_ID("hclk", &macb_clk), /* */ CLKDEV_CON_ID("ohci_clk", &uhphs_clk), CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk), CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk), CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk), CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk), CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb0_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tcb0_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), CLKDEV_CON_DEV_ID(NULL, "atmel-trng", &trng_clk), /* */ CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck), CLKDEV_CON_DEV_ID("usart", "fff8c000.serial", &usart0_clk), CLKDEV_CON_DEV_ID("usart", "fff90000.serial", &usart1_clk),
&tcb0_clk, &pwm_clk, &adc_clk, &adc_op_clk, &dma0_clk, &dma1_clk, &uhphs_clk, &udphs_clk, &mmc1_clk, &ssc_clk, // irq0 }; static struct clk_lookup periph_clocks_lookups[] = { /* lookup table for DT entries */ CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck), CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk), CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk), CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk), CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk), CLKDEV_CON_DEV_ID("usart", "f8040000.serial", &uart0_clk), CLKDEV_CON_DEV_ID("usart", "f8044000.serial", &uart1_clk), CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk), CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk), CLKDEV_CON_DEV_ID("mci_clk", "f0008000.mmc", &mmc0_clk), CLKDEV_CON_DEV_ID("mci_clk", "f000c000.mmc", &mmc1_clk), CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma0_clk), CLKDEV_CON_DEV_ID("dma_clk", "ffffee00.dma-controller", &dma1_clk), CLKDEV_CON_DEV_ID("pclk", "f0010000.ssc", &ssc_clk), CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk), CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
&twi_clk, &spi0_clk, &spi1_clk, &ssc0_clk, &ssc1_clk, &ssc2_clk, &tc0_clk, &tc1_clk, &tc2_clk, &ohci_clk, &lcdc_clk, // irq0 .. irq2 }; static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk), CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk), CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc1_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk), }; static struct clk_lookup usart_clocks_lookups[] = { CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck), CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk), CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk), CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk), };
}; static struct platform_device at91sam9g45_isi_device = { .name = "atmel_isi", .id = 0, .dev = { .dma_mask = &isi_dmamask, .coherent_dma_mask = DMA_BIT_MASK(32), .platform_data = &isi_data, }, .resource = isi_resources, .num_resources = ARRAY_SIZE(isi_resources), }; static struct clk_lookup isi_mck_lookups[] = { CLKDEV_CON_DEV_ID("isi_mck", "atmel_isi.0", NULL), }; void __init at91_add_device_isi(struct isi_platform_data *data, bool use_pck_as_mck) { struct clk *pck; struct clk *parent; if (!data) return; isi_data = *data; at91_set_A_periph(AT91_PIN_PB20, 0); /* ISI_D0 */ at91_set_A_periph(AT91_PIN_PB21, 0); /* ISI_D1 */ at91_set_A_periph(AT91_PIN_PB22, 0); /* ISI_D2 */
&twi_clk, &spi0_clk, &spi1_clk, &ssc0_clk, &ssc1_clk, &ssc2_clk, &tc0_clk, &tc1_clk, &tc2_clk, &ohci_clk, &lcdc_clk, // irq0 .. irq2 }; static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("hclk", "at91sam9261-lcdfb.0", &hck1), CLKDEV_CON_DEV_ID("hclk", "at91sam9g10-lcdfb.0", &hck1), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk), CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk), CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk), CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk), CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk), CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc1_clk), CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc2_clk), CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0), CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261.0", &twi_clk), CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10.0", &twi_clk),
&ohci_clk, &macb_clk, &isi_clk, &usart3_clk, &usart4_clk, &usart5_clk, &tc3_clk, &tc4_clk, &tc5_clk, // irq0 .. irq2 }; static struct clk_lookup periph_clocks_lookups[] = { /* One additional fake clock for macb_hclk */ CLKDEV_CON_ID("hclk", &macb_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk), CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk), CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk), CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk), CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk), CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc_clk), CLKDEV_CON_DEV_ID("pclk", "fffbc000.ssc", &ssc_clk), CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk), CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi_clk), /* more usart lookup table for DT entries */ CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck), CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk), CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk),
&ohci_clk, &macb_clk, &isi_clk, &usart3_clk, &usart4_clk, &usart5_clk, &tc3_clk, &tc4_clk, &tc5_clk, // irq0 .. irq2 }; static struct clk_lookup periph_clocks_lookups[] = { /* One additional fake clock for macb_hclk */ CLKDEV_CON_ID("hclk", &macb_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk), CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk), CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk), CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk), CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk), /* more usart lookup table for DT entries */ CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck), CLKDEV_CON_DEV_ID("usart", "fffb0000.serial", &usart0_clk), CLKDEV_CON_DEV_ID("usart", "fffb4000.serial", &usart1_clk), CLKDEV_CON_DEV_ID("usart", "fffb8000.serial", &usart2_clk), CLKDEV_CON_DEV_ID("usart", "fffd0000.serial", &usart3_clk), CLKDEV_CON_DEV_ID("usart", "fffd4000.serial", &usart4_clk),
&ssc0_clk, &ssc1_clk, &ssc2_clk, &tc0_clk, &tc1_clk, &tc2_clk, &tc3_clk, &tc4_clk, &tc5_clk, &ohci_clk, ðer_clk, // irq0 .. irq6 }; static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk), CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk), CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk), CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk), CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk), CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk), CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.2", &ssc2_clk), CLKDEV_CON_DEV_ID("pclk", "fffd0000.ssc", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "fffd4000.ssc", &ssc1_clk), CLKDEV_CON_DEV_ID("pclk", "fffd8000.ssc", &ssc2_clk), CLKDEV_CON_DEV_ID(NULL, "i2c-at91rm9200.0", &twi_clk), /* fake hclk clock */ CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), CLKDEV_CON_ID("pioA", &pioA_clk),
&ssc0_clk, &ssc1_clk, &tc0_clk, &tc1_clk, &tc2_clk, &pwm_clk, &tsc_clk, &dma_clk, &udphs_clk, &lcdc_clk, &ac97_clk, }; static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk), CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk), CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk), CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), CLKDEV_CON_ID("pioA", &pioA_clk), CLKDEV_CON_ID("pioB", &pioB_clk), CLKDEV_CON_ID("pioC", &pioC_clk), CLKDEV_CON_ID("pioD", &pioD_clk), }; static struct clk_lookup usart_clocks_lookups[] = { CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck), CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk),
&twi_clk, &spi0_clk, &spi1_clk, &ssc0_clk, &ssc1_clk, &ssc2_clk, &tc0_clk, &tc1_clk, &tc2_clk, &ohci_clk, &lcdc_clk, // irq0 .. irq2 }; static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk), CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk), CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.1", &ssc1_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.2", &ssc2_clk), CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &hck0), CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9261", &twi_clk), CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g10", &twi_clk), CLKDEV_CON_ID("pioA", &pioA_clk), CLKDEV_CON_ID("pioB", &pioB_clk), CLKDEV_CON_ID("pioC", &pioC_clk), };
&ssc0_clk, &ssc1_clk, &tc0_clk, &tc1_clk, &tc2_clk, &pwm_clk, &tsc_clk, &dma_clk, &udphs_clk, &lcdc_clk, &ac97_clk, // irq0 }; static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk), CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk), CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk), CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk), CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk), CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk), CLKDEV_CON_DEV_ID("pclk", "fffc0000.ssc", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "fffc4000.ssc", &ssc1_clk), CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.0", &twi0_clk), CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9g20.1", &twi1_clk), CLKDEV_CON_ID("pioA", &pioA_clk), CLKDEV_CON_ID("pioB", &pioB_clk), CLKDEV_CON_ID("pioC", &pioC_clk), CLKDEV_CON_ID("pioD", &pioD_clk),
&tcb_clk, &pwm_clk, &macb_clk, &twodge_clk, &udc_clk, &isi_clk, &lcdc_clk, &dma_clk, &ohci_clk, // irq0 .. irq1 }; static struct clk_lookup periph_clocks_lookups[] = { /* One additional fake clock for macb_hclk */ CLKDEV_CON_ID("hclk", &macb_clk), CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.0", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk), CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk), CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk), CLKDEV_CON_DEV_ID("hclk", "at91sam9263-lcdfb.0", &lcdc_clk), CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk), CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tcb_clk), CLKDEV_CON_DEV_ID(NULL, "i2c-at91sam9260.0", &twi_clk), /* fake hclk clock */ CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk), CLKDEV_CON_ID("pioA", &pioA_clk), CLKDEV_CON_ID("pioB", &pioB_clk), CLKDEV_CON_ID("pioC", &pioCDE_clk),
&uart1_clk, &tcb0_clk, &pwm_clk, &adc_clk, &dma0_clk, &dma1_clk, &uhphs_clk, &udphs_clk, &mmc1_clk, &ssc_clk, // irq0 }; static struct clk_lookup periph_clocks_lookups[] = { /* lookup table for DT entries */ CLKDEV_CON_DEV_ID("usart", "fffff200.serial", &mck), CLKDEV_CON_DEV_ID("usart", "f801c000.serial", &usart0_clk), CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart1_clk), CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart2_clk), CLKDEV_CON_DEV_ID("usart", "f8028000.serial", &usart3_clk), CLKDEV_CON_DEV_ID("t0_clk", "f8008000.timer", &tcb0_clk), CLKDEV_CON_DEV_ID("t0_clk", "f800c000.timer", &tcb0_clk), CLKDEV_CON_ID("pioA", &pioAB_clk), CLKDEV_CON_ID("pioB", &pioAB_clk), CLKDEV_CON_ID("pioC", &pioCD_clk), CLKDEV_CON_ID("pioD", &pioCD_clk), /* additional fake clock for macb_hclk */ CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb0_clk), CLKDEV_CON_DEV_ID("hclk", "f8030000.ethernet", &macb1_clk), CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk), CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk),
&tc1_clk, &tc2_clk, &ohci_clk, &macb_clk, &isi_clk, &usart3_clk, &usart4_clk, &usart5_clk, &tc3_clk, &tc4_clk, &tc5_clk, // irq0 .. irq2 }; static struct clk_lookup periph_clocks_lookups[] = { CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk), CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk), CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.0", &tc1_clk), CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.0", &tc2_clk), CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.1", &tc3_clk), CLKDEV_CON_DEV_ID("t1_clk", "atmel_tcb.1", &tc4_clk), CLKDEV_CON_DEV_ID("t2_clk", "atmel_tcb.1", &tc5_clk), CLKDEV_CON_DEV_ID("pclk", "ssc.0", &ssc_clk), }; static struct clk_lookup usart_clocks_lookups[] = { CLKDEV_CON_DEV_ID("usart", "atmel_usart.0", &mck), CLKDEV_CON_DEV_ID("usart", "atmel_usart.1", &usart0_clk), CLKDEV_CON_DEV_ID("usart", "atmel_usart.2", &usart1_clk), CLKDEV_CON_DEV_ID("usart", "atmel_usart.3", &usart2_clk),