&exynos5_clk_mdma1, }; static struct clksrc_clk *exynos5_clksrc_cdev[] = { &exynos5_clk_sclk_uart0, &exynos5_clk_sclk_uart1, &exynos5_clk_sclk_uart2, &exynos5_clk_sclk_uart3, &exynos5_clk_sclk_mmc0, &exynos5_clk_sclk_mmc1, &exynos5_clk_sclk_mmc2, &exynos5_clk_sclk_mmc3, }; static struct clk_lookup exynos5_clk_lookup[] = { CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk), CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk), CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk), CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk), CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk), CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk), CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk), CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk), CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0), CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1), CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1), }; static unsigned long exynos5_epll_get_rate(struct clk *clk) { return clk->rate;
&clk_armdiv, &hsmmc1_clk, }; static struct clksrc_clk *clksrcs[] __initdata = { &clk_i2s_eplldiv, &clk_i2s, &clk_usb_bus_host, &clk_epllref, &clk_esysclk, &clk_msysclk, &clk_arm, }; static struct clk_lookup s3c2443_clk_lookup[] = { CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk), CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_esys_uart.clk), CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &hsmmc1_clk), }; void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, unsigned int *divs, int nr_divs, int divmask) { int ptr; armdiv = divs; nr_armdiv = nr_divs; armdivmask = divmask;
static struct clk dummy_apb_pclk = { .name = "apb_pclk", .id = -1, }; static struct clksrc_clk *clksrc_cdev[] = { &clk_sclk_uclk, &clk_sclk_spi0, &clk_sclk_spi1, &clk_sclk_mmc0, &clk_sclk_mmc1, &clk_sclk_mmc2 }; static struct clk_lookup s5p6440_clk_lookup[] = { CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), }; void __init_or_cpufreq s5p6440_setup_clocks(void) { struct clk *xtal_clk; unsigned long xtal; unsigned long fclk;
.parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit = S3C2416_HCLKCON_HSMMC0, }; static struct clksrc_clk *clksrcs[] __initdata = { &hsspi_eplldiv, &hsspi_mux, &hsmmc_div[0], &hsmmc_div[1], &hsmmc_mux0, &hsmmc_mux1, }; static struct clk_lookup s3c2416_clk_lookup[] = { CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &hsmmc0_clk), CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &hsmmc_mux0.clk), CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &hsmmc_mux1.clk), }; void __init s3c2416_init_clocks(int xtal) { u32 epllcon = __raw_readl(S3C2443_EPLLCON); u32 epllcon1 = __raw_readl(S3C2443_EPLLCON+4); int ptr; /* s3c2416 EPLL compatible with s3c64xx */ clk_epll.rate = s3c_get_pll6553x(xtal, epllcon, epllcon1); clk_epll.parent = &clk_epllref.clk;
static DEFINE_CLK(cpu, &clk_cpu_ops); static unsigned long clk_36864_get_rate(struct clk *clk) { return 3686400; } static struct clkops clk_36864_ops = { .enable = clk_cpu_enable, .disable = clk_cpu_disable, .get_rate = clk_36864_get_rate, }; static DEFINE_CLK(36864, &clk_36864_ops); static struct clk_lookup sa11xx_clkregs[] = { CLKDEV_INIT("sa1111.0", NULL, &clk_gpio27), CLKDEV_INIT("sa1100-rtc", NULL, NULL), CLKDEV_INIT("sa11x0-fb", NULL, &clk_cpu), CLKDEV_INIT("sa11x0-pcmcia", NULL, &clk_cpu), /* sa1111 names devices using internal offsets, PCMCIA is at 0x1800 */ CLKDEV_INIT("1800", NULL, &clk_cpu), CLKDEV_INIT(NULL, "OSTIMER0", &clk_36864), }; int __init sa11xx_clk_init(void) { clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs)); return 0; }
* console to use them */ s3c24xx_setup_clocks(fclk, hclk, pclk); } /* fake ARMCLK for use with cpufreq, etc. */ static struct clk s3c2410_armclk = { .name = "armclk", .parent = &clk_f, .id = -1, }; static struct clk_lookup s3c2410_clk_lookup[] = { CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p), CLKDEV_INIT(NULL, "clk_uart_baud1", &s3c24xx_uclk), }; void __init s3c2410_init_clocks(int xtal) { s3c24xx_register_baseclocks(xtal); s3c2410_setup_clocks(); s3c2410_baseclk_add(); s3c24xx_register_clock(&s3c2410_armclk); clkdev_add_table(s3c2410_clk_lookup, ARRAY_SIZE(s3c2410_clk_lookup)); samsung_wdt_reset_init(S3C24XX_VA_WATCHDOG); } struct bus_type s3c2410_subsys = { .name = "s3c2410-core",
for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) s3c_set_clksrc(&clksrcs[ptr], true); } static struct clk *clks[] __initdata = { &clk_sclk_hdmi27m, &clk_sclk_hdmiphy, &clk_sclk_usbphy0, &clk_sclk_usbphy1, &clk_pcmcdclk0, &clk_pcmcdclk1, &clk_pcmcdclk2, }; static struct clk_lookup s5pv210_clk_lookup[] = { CLKDEV_INIT(NULL, "clk_uart_baud0", &clk_p), CLKDEV_INIT("s5pv210-uart.0", "clk_uart_baud1", &clk_sclk_uart0.clk), CLKDEV_INIT("s5pv210-uart.1", "clk_uart_baud1", &clk_sclk_uart1.clk), CLKDEV_INIT("s5pv210-uart.2", "clk_uart_baud1", &clk_sclk_uart2.clk), CLKDEV_INIT("s5pv210-uart.3", "clk_uart_baud1", &clk_sclk_uart3.clk), CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0), CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1), CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2), CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.0", &clk_hsmmc3), CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &clk_sclk_mmc3.clk), CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
} }; /* clocks to add straight away */ static struct clksrc_clk *clksrcs[] __initdata = { &clk_hsspi, &clk_hsmmc_div, }; static struct clk *clks[] __initdata = { &clk_hsmmc, }; static struct clk_lookup s3c2443_clk_lookup[] = { CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_hsmmc), CLKDEV_INIT("s3c2443-spi.0", "spi_busclk2", &clk_hsspi.clk), }; void __init s3c2443_init_clocks(int xtal) { unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); int ptr; clk_epll.rate = s3c2443_get_epll(epllcon, xtal); clk_epll.parent = &clk_epllref.clk; s3c2443_common_init_clocks(xtal, s3c2443_get_mpll, armdiv, ARRAY_SIZE(armdiv), S3C2443_CLKDIV0_ARMDIV_MASK);
.enable = s5pc100_d1_3_ctrl, .ctrlbit = (1 << 6), }, }; static struct clk *clks[] __initdata = { &clk_ext, &clk_i2scdclk0, &clk_i2scdclk1, &clk_i2scdclk2, &clk_pcmcdclk0, &clk_pcmcdclk1, }; static struct clk_lookup s5pc100_clk_lookup[] = { CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk), CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0), CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1), CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2), CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), CLKDEV_INIT("s5pc100-spi.0", "spi_busclk1", &clk_48m_spi0), CLKDEV_INIT("s5pc100-spi.0", "spi_busclk2", &clk_sclk_spi0.clk), CLKDEV_INIT("s5pc100-spi.1", "spi_busclk1", &clk_48m_spi1), CLKDEV_INIT("s5pc100-spi.1", "spi_busclk2", &clk_sclk_spi1.clk), CLKDEV_INIT("s5pc100-spi.2", "spi_busclk1", &clk_48m_spi2), CLKDEV_INIT("s5pc100-spi.2", "spi_busclk2", &clk_sclk_spi2.clk), CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0),
&clk_i2s1, &clk_i2s2, }; static struct clksrc_clk *clksrc_cdev[] = { &clk_sclk_uclk, &clk_sclk_spi0, &clk_sclk_spi1, &clk_sclk_mmc0, &clk_sclk_mmc1, &clk_sclk_mmc2, &clk_sclk_audio0, }; static struct clk_lookup s5p6450_clk_lookup[] = { CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0), CLKDEV_INIT("samsung-i2s.0", "i2s_opclk1", &clk_sclk_audio0.clk), CLKDEV_INIT("samsung-i2s.1", "i2s_opclk0", &clk_i2s1), CLKDEV_INIT("samsung-i2s.2", "i2s_opclk0", &clk_i2s2), }; /* Clock initialization code */ static struct clksrc_clk *sysclks[] = {
.enable = s5pc100_d1_3_ctrl, .ctrlbit = (1 << 6), }, }; static struct clk *clks[] __initdata = { &clk_ext, &clk_i2scdclk0, &clk_i2scdclk1, &clk_i2scdclk2, &clk_pcmcdclk0, &clk_pcmcdclk1, }; static struct clk_lookup s5pc100_clk_lookup[] = { CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk), CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0), CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1), CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2), CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk1", &clk_48m_spi0), CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk2", &clk_sclk_spi0.clk), CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk1", &clk_48m_spi1), CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk2", &clk_sclk_spi1.clk), CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk1", &clk_48m_spi2), CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk2", &clk_sclk_spi2.clk), };
&exynos4_clk_sclk_uart0, &exynos4_clk_sclk_uart1, &exynos4_clk_sclk_uart2, &exynos4_clk_sclk_uart3, &exynos4_clk_sclk_mmc0, &exynos4_clk_sclk_mmc1, &exynos4_clk_sclk_mmc2, &exynos4_clk_sclk_mmc3, &exynos4_clk_sclk_spi0, &exynos4_clk_sclk_spi1, &exynos4_clk_sclk_spi2, }; static struct clk_lookup exynos4_clk_lookup[] = { CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk), CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk), CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk), CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk), CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk), CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk), CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk), CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk), CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0), CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1), CLKDEV_INIT("s3c64xx-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk), CLKDEV_INIT("s3c64xx-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk), CLKDEV_INIT("s3c64xx-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk), };