/** * Initializes the system. * System control registers must be unlocked. */ void SYS_Init() { // TODO: why is SYS_UnlockReg() needed? Should be already unlocked. SYS_UnlockReg(); // HIRC clock (internal RC 22.1184MHz) CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk); CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); // HCLK clock source: HIRC, HCLK source divider: 1 CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1)); // HXT clock (external XTAL 12MHz) CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); // Enable 72MHz optimization FMC_EnableFreqOptimizeMode(FMC_FTCTL_OPTIMIZE_72MHZ); // Core clock: PLL CLK_SetCoreClock(PLL_CLOCK); CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); // SPI0 clock: PCLK0 CLK_SetModuleClock(SPI0_MODULE, CLK_CLKSEL2_SPI0SEL_PCLK0, 0); CLK_EnableModuleClock(SPI0_MODULE); // TMR0 clock: HXT CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_HXT, 0); CLK_EnableModuleClock(TMR0_MODULE); // USBD clock CLK_SetModuleClock(USBD_MODULE, 0, CLK_CLKDIV0_USB(3)); CLK_EnableModuleClock(USBD_MODULE); // Enable USB 3.3V LDO SYS->USBPHY = SYS_USBPHY_LDO33EN_Msk; // EADC clock: 72Mhz / 8 CLK_SetModuleClock(EADC_MODULE, 0, CLK_CLKDIV0_EADC(8)); CLK_EnableModuleClock(EADC_MODULE); // Enable BOD (reset, 2.2V) SYS_EnableBOD(SYS_BODCTL_BOD_RST_EN, SYS_BODCTL_BODVL_2_2V); // Update system core clock SystemCoreClockUpdate(); // Initialize dataflash Dataflash_Init(); // Initialize I/O Display_SetupSPI(); Button_Init(); ADC_Init(); // Initialize display Display_Init(); }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Enable Internal RC 22.1184 MHz clock */ CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk); /* Waiting for Internal RC clock ready */ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); /* Switch HCLK clock source to Internal RC and set HCLK divider to 1 */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1)); /* Enable external XTAL 12 MHz clock */ CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); /* Waiting for external XTAL clock ready */ CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); /* Set Flash Access Delay */ FMC->FTCTL |= FMC_FTCTL_FOM_Msk; /* Set core clock */ CLK_SetCoreClock(72000000); /* Enable module clock */ CLK_EnableModuleClock(UART0_MODULE); CLK_EnableModuleClock(UART1_MODULE); CLK_EnableModuleClock(USBD_MODULE); /* Select module clock source */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1)); CLK_SetModuleClock(UART1_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1)); CLK_SetModuleClock(USBD_MODULE, 0, CLK_CLKDIV0_USB(3)); /* Enable USB LDO33 */ SYS->USBPHY = SYS_USBPHY_LDO33EN_Msk; /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set GPD multi-function pins for UART0 RXD, TXD and Clock Output */ SYS->GPD_MFPL = SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD | SYS_GPD_MFPL_PD6MFP_CLKO; /* Set GPA multi-function pins for UART1 RXD and TXD */ SYS->GPA_MFPL = SYS_GPA_MFPL_PA0MFP_UART1_TXD | SYS_GPA_MFPL_PA1MFP_UART1_RXD; /* Enable CLKO (PD.6) for monitor HCLK. CLKO = HCLK/8 Hz */ CLK_EnableCKO(CLK_CLKSEL1_CLKOSEL_HCLK, 2, 0); }
//========================================================================= //----- (0000652C) -------------------------------------------------------- void InitDevices() { SYS_UnlockReg(); // Internal 22.1184MHz oscillator CLK_EnableXtalRC( CLK_PWRCTL_HIRCEN_Msk ); CLK_WaitClockReady( CLK_STATUS_HIRCSTB_Msk ); CLK_SetHCLK( CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK( 1 ) ); // 12.000MHz external crystal CLK_EnableXtalRC( CLK_PWRCTL_HXTEN_Msk ); CLK_WaitClockReady( CLK_STATUS_HXTSTB_Msk ); // FMC Frequency Optimisation mode <= 72MHz FMC_EnableFreqOptimizeMode( FMC_FTCTL_OPTIMIZE_72MHZ ); // Setup PLL to 144MHz and HCLK source to PLL/2 CLK_SetCoreClock( CPU_FREQ ); // UART0 CLK = HXT/1 #if (ENABLE_UART) CLK_EnableModuleClock( UART0_MODULE ); CLK_SetModuleClock( UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART( 1 ) ); #endif // USB CLK = PLL/3 (48MHz) CLK_EnableModuleClock( USBD_MODULE ); CLK_SetModuleClock( USBD_MODULE, 0, CLK_CLKDIV0_USB( 3 ) ); SYS->USBPHY = SYS_USBPHY_LDO33EN_Msk; // WDT CLK = LIRC/1 CLK_EnableModuleClock( WDT_MODULE ); CLK_SetModuleClock( WDT_MODULE, CLK_CLKSEL1_WDTSEL_LIRC, 0 ); // SPI0 CLK = PCLK0/1 CLK_EnableModuleClock( SPI0_MODULE ); // EADC CLK = PCLK1/8 (9MHz) CLK_EnableModuleClock( EADC_MODULE ); CLK_SetModuleClock( EADC_MODULE, 0, CLK_CLKDIV0_EADC( 8 ) ); // CRC CLK = HCLK/1 CLK_EnableModuleClock( CRC_MODULE ); // TIMERS CLOCKS CLK_EnableModuleClock( TMR0_MODULE ); CLK_EnableModuleClock( TMR1_MODULE ); CLK_EnableModuleClock( TMR2_MODULE ); CLK_EnableModuleClock( TMR3_MODULE ); CLK_SetModuleClock( TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_HXT, 0 ); CLK_SetModuleClock( TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_PCLK0, 0 ); CLK_SetModuleClock( TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_HIRC, 0 ); CLK_SetModuleClock( TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_HXT, 0 ); // Enable battery voltage sampling by ADC SYS->IVSCTL |= SYS_IVSCTL_VBATUGEN_Msk; // ADC reference voltage SYS->VREFCTL = SYS_VREFCTL_VREF_2_56V; // Brown-out detector; interrupts under 2.2V SYS_EnableBOD( SYS_BODCTL_BOD_RST_EN, SYS_BODCTL_BODVL_2_2V ); // Update clock data SystemCoreClockUpdate(); WDT_Open( WDT_TIMEOUT_2POW18, WDT_RESET_DELAY_18CLK, TRUE, FALSE ); SYS_LockReg(); }
void SYS_Init(void) { /*---------------------------------------------------------------------------------------------------------*/ /* Init System Clock */ /*---------------------------------------------------------------------------------------------------------*/ /* Enable Internal RC 22.1184MHz clock */ CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk); /* Waiting for Internal RC clock ready */ CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); /* Switch HCLK clock source to Internal RC and HCLK source divide 1 */ CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1)); /* Enable external XTAL 12MHz clock */ CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk); /* Waiting for external XTAL clock ready */ CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); /* Set Flash Access Delay */ FMC->FTCTL |= FMC_FTCTL_FOM_Msk; /* Set core clock */ CLK_SetCoreClock(72000000); /* Enable module clock */ CLK_EnableModuleClock(UART0_MODULE); CLK_EnableModuleClock(USBD_MODULE); CLK_EnableModuleClock(TMR0_MODULE); CLK_EnableModuleClock(I2C0_MODULE); CLK_EnableModuleClock(SPI1_MODULE); /* Select module clock source */ CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1)); CLK_SetModuleClock(USBD_MODULE, 0, CLK_CLKDIV0_USB(3)); CLK_SetModuleClock(TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_HXT, 0); CLK_SetModuleClock(SPI1_MODULE, CLK_CLKSEL2_SPI1SEL_PLL, 0); /* Enable USB LDO33 */ SYS->USBPHY = SYS_USBPHY_LDO33EN_Msk; /*---------------------------------------------------------------------------------------------------------*/ /* Init I/O Multi-function */ /*---------------------------------------------------------------------------------------------------------*/ /* Set PD.0, PD.1, PD.6, PD.4 and PD.5 as SPI1_I2SMCLK, UART0 TXD, UART0 RXD, I2C0_SDA and I2C0_SCL function pins */ SYS->GPD_MFPL = SYS_GPD_MFPL_PD0MFP_SPI1_I2SMCLK | SYS_GPD_MFPL_PD1MFP_UART0_TXD | SYS_GPD_MFPL_PD6MFP_UART0_RXD | SYS_GPD_MFPL_PD4MFP_I2C0_SDA | SYS_GPD_MFPL_PD5MFP_I2C0_SCL; /* Set I2S1 interface: I2S1_LRCLK (PA.4), I2S1_DO (PA.5), I2S1_DI (PA.6), I2S1_BCLK (PA.7) */ SYS->GPA_MFPL = SYS_GPA_MFPL_PA4MFP_SPI1_SS | SYS_GPA_MFPL_PA5MFP_SPI1_MOSI | SYS_GPA_MFPL_PA6MFP_SPI1_MISO | SYS_GPA_MFPL_PA7MFP_SPI1_CLK; /* Set PC.1 as CLKO pin */ SYS->GPC_MFPL = SYS_GPC_MFPL_PC1MFP_CLKO; /* Enable CLKO (PC.1) for monitor HCLK. CLKO = HCLK/8 Hz */ CLK_EnableCKO(CLK_CLKSEL1_CLKOSEL_HCLK, 2, 0); }