void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable HIRC clock (Internal RC 22.1184MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
/* Wait for HIRC clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
/* Select HCLK clock source as HIRC and and HCLK source divider as 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
/* Set PLL to Power-down mode and PLLSTB bit in CLK_STATUS register will be cleared by hardware.*/
CLK_DisablePLL();
/* Enable HXT clock (external XTAL 12MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
/* Wait for HXT clock ready */
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
/* Set core clock as PLL_CLOCK from PLL */
CLK_SetCoreClock(PLL_CLOCK);
/* Enable UART module clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Select UART module clock source as HXT and UART module clock divider as 1 */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1));
/* Enable EADC module clock */
CLK_EnableModuleClock(EADC_MODULE);
/* EADC clock source is 72MHz, set divider to 8, ADC clock is 72/8 MHz */
CLK_SetModuleClock(EADC_MODULE, 0, CLK_CLKDIV0_EADC(8));
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PD multi-function pins for UART0 RXD and TXD */
SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD0MFP_Msk | SYS_GPD_MFPL_PD1MFP_Msk);
SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD);
/* Configure the GPB0 - GPB3 ADC analog input pins. */
SYS->GPB_MFPL &= ~(SYS_GPB_MFPL_PB0MFP_Msk | SYS_GPB_MFPL_PB1MFP_Msk |
SYS_GPB_MFPL_PB2MFP_Msk | SYS_GPB_MFPL_PB3MFP_Msk);
SYS->GPB_MFPL |= (SYS_GPB_MFPL_PB0MFP_EADC_CH0 | SYS_GPB_MFPL_PB1MFP_EADC_CH1 |
SYS_GPB_MFPL_PB2MFP_EADC_CH2 | SYS_GPB_MFPL_PB3MFP_EADC_CH3);
/* Disable the GPB0 - GPB3 digital input path to avoid the leakage current. */
GPIO_DISABLE_DIGITAL_PATH(PB, 0xF);
}
void SYS_Init(void)
{
/*---------------------------------------------------------------------------------------------------------*/
/* Init System Clock */
/*---------------------------------------------------------------------------------------------------------*/
/* Enable HIRC clock (Internal RC 22.1184MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
/* Wait for HIRC clock ready */
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
/* Select HCLK clock source as HIRC and and HCLK source divider as 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
/* Set PLL to Power-down mode and PLLSTB bit in CLK_STATUS register will be cleared by hardware.*/
CLK_DisablePLL();
/* Enable HXT clock (external XTAL 12MHz) */
CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
/* Wait for HXT clock ready */
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
/* Set core clock as PLL_CLOCK from PLL */
CLK_SetCoreClock(PLL_CLOCK);
/* Enable UART module clock */
CLK_EnableModuleClock(UART0_MODULE);
/* Select UART module clock source as HXT and UART module clock divider as 1 */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UARTSEL_HXT, CLK_CLKDIV0_UART(1));
/* Enable DAC module clock */
CLK_EnableModuleClock(DAC_MODULE);
/*---------------------------------------------------------------------------------------------------------*/
/* Init I/O Multi-function */
/*---------------------------------------------------------------------------------------------------------*/
/* Set PD multi-function pins for UART0 RXD and TXD */
SYS->GPD_MFPL &= ~(SYS_GPD_MFPL_PD0MFP_Msk | SYS_GPD_MFPL_PD1MFP_Msk);
SYS->GPD_MFPL |= (SYS_GPD_MFPL_PD0MFP_UART0_RXD | SYS_GPD_MFPL_PD1MFP_UART0_TXD);
/* Set PB multi-function pins for DAC voltage output */
SYS->GPB_MFPL &= ~SYS_GPB_MFPL_PB0MFP_Msk;
SYS->GPB_MFPL |= SYS_GPB_MFPL_PB0MFP_DAC ;
}
//=========================================================================
__myevic__ void LightSleep()
{
// Switch Core Clock to HXT/3 (4MHz)
CLK_SetHCLK( CLK_CLKSEL0_HCLKSEL_HXT, CLK_CLKDIV0_HCLK( 3 ) );
// Update clock data
SystemCoreClockUpdate();
// Switch off the PLL Clock & the HIRC
CLK_DisablePLL();
CLK_DisableXtalRC( CLK_PWRCTL_HIRCEN_Msk );
// Disable Clocks of Modules using HCLK/HXT or LIRC
CLK_DisableModuleClock( PWM0_MODULE );
CLK_DisableModuleClock( SPI0_MODULE );
CLK_DisableModuleClock( CRC_MODULE );
#if (ENABLE_UART)
CLK_DisableModuleClock( UART0_MODULE );
#endif
gFlags.wake_up = 0;
do
{
CLK_Idle();
}
while ( !gFlags.wake_up );
// Wake up the HIRC
CLK_EnableXtalRC( CLK_PWRCTL_HIRCEN_Msk );
CLK_WaitClockReady( CLK_STATUS_HIRCSTB_Msk );
// Wake up the PLL
CLK_SetCoreClock( CPU_FREQ );
// Update clock data
SystemCoreClockUpdate();
// Wake up Modules
#if (ENABLE_UART)
CLK_EnableModuleClock( UART0_MODULE );
#endif
CLK_EnableModuleClock( PWM0_MODULE );
CLK_EnableModuleClock( SPI0_MODULE );
CLK_EnableModuleClock( CRC_MODULE );
}
void SYS_PLL_Test(void)
{
int32_t i;
/*---------------------------------------------------------------------------------------------------------*/
/* PLL clock configuration test */
/*---------------------------------------------------------------------------------------------------------*/
printf("\n-------------------------[ Test PLL ]-----------------------------\n");
for(i = 0; i < sizeof(g_au32PllSetting) / sizeof(g_au32PllSetting[0]) ; i++) {
/* Switch HCLK clock source to HXT and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HXT, CLK_CLKDIV_HCLK(1));
/* Set PLL to power down mode and PLL_STB bit in CLKSTATUS register will be cleared by hardware. */
CLK_DisablePLL();
/* Set PLL frequency */
CLK->PLLCON = g_au32PllSetting[i];
/* Waiting for PLL clock ready */
CLK_WaitClockReady(CLK_CLKSTATUS_PLL_STB_Msk);
/* Switch HCLK clock source to PLL */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_PLL, CLK_CLKDIV_HCLK(1));
printf(" Change system clock to %d Hz ...................... ", SystemCoreClock);
/* Output selected clock to CKO, CKO Clock = HCLK / 2^(1 + 1) */
CLK_EnableCKO(CLK_CLKSEL2_FRQDIV_S_HCLK, 1, 0);
/* The delay loop is used to check if the CPU speed is increasing */
Delay(0x400000);
if(pi()) {
printf("[FAIL]\n");
} else {
printf("[OK]\n");
}
/* Disable CKO clock */
CLK_DisableCKO();
}
}
/*---------------------------------------------------------------------------------------------------------*/
int32_t main(void)
{
uint32_t u32data;
/* In end of main function, program issued CPU reset and write-protection will be disabled. */
if(SYS_IsRegLocked() == 0)
SYS_LockReg();
/* Unlock protected registers */
SYS_UnlockReg();
/* Init System, peripheral clock and multi-function I/O */
SYS_Init();
/* Lock protected registers */
SYS_LockReg();
/* Init UART0 for printf */
UART0_Init();
printf("\n\nCPU @ %dHz\n", SystemCoreClock);
/*
This sample code will show some function about system manager controller and clock controller:
1. Read PDID
2. Get and clear reset source
3. Setting about BOD
4. Change system clock depended on different PLL settings
5. Output system clock from CKO pin, and the output frequency = system clock / 4
*/
printf("+--------------------------------------------+\n");
printf("| NUC029xEE System Driver Sample Code |\n");
printf("+--------------------------------------------+\n");
if(M32(FLAG_ADDR) == SIGNATURE) {
printf(" CPU Reset success!\n");
M32(FLAG_ADDR) = 0;
printf(" Press any key to continue ...\n");
getchar();
}
/*---------------------------------------------------------------------------------------------------------*/
/* Misc system function test */
/*---------------------------------------------------------------------------------------------------------*/
/* Read Part Device ID */
printf("Product ID 0x%x\n", SYS_ReadPDID());
/* Get reset source from last operation */
u32data = SYS_GetResetSrc();
printf("Reset Source 0x%x\n", u32data);
/* Clear reset source */
SYS_ClearResetSrc(u32data);
/* Unlock protected registers for Brown-Out Detector settings */
SYS_UnlockReg();
/* Check if the write-protected registers are unlocked before BOD setting and CPU Reset */
if(SYS_IsRegLocked() == 0) {
printf("Protected Address is Unlocked\n");
}
/* Enable Brown-Out Detector, and set Brown-Out Detector voltage 2.7V */
SYS_EnableBOD(SYS_BODCR_BOD_INTERRUPT_EN, SYS_BODCR_BOD_VL_2_7V);
/* Enable BOD IRQ */
NVIC_EnableIRQ(BOD_IRQn);
/* Enable Low Voltage Reset function */
SYS_ENABLE_LVR();
/* Run PLL Test */
SYS_PLL_Test();
/* Write a signature work to SRAM to check if it is reset by software */
M32(FLAG_ADDR) = SIGNATURE;
printf("\n\n >>> Reset CPU <<<\n");
/* Waiting for message send out */
UART_WAIT_TX_EMPTY(UART0);
/* Switch HCLK clock source to Internal RC 22.1184MHz clock and HCLK source divide 1 */
CLK_SetHCLK(CLK_CLKSEL0_HCLK_S_HIRC, CLK_CLKDIV_HCLK(1));
/* Set PLL to Power down mode and HW will also clear PLL_STB bit in CLKSTATUS register */
CLK_DisablePLL();
/* Reset CPU */
SYS_ResetCPU();
}
