* @param divisor: Divisor to check
* @return : An even-number divisor
*/
static inline uint8_t
zynq7000_even_divisor(uint8_t divisor)
{
if ((divisor % 2) != 0) {
return INRANGE(CLK_DIVISOR_MIN + 1, divisor - 1, CLK_DIVISOR_MAX - 1);
} else {
return divisor;
}
}
/* PS_CLK */
static struct clock master_clk = { CLK_OPS_DEFAULT(MASTER) };
static uint32_t
_decode_pll(clk_t* clk, volatile uint32_t** ctrl, volatile uint32_t** cfg)
{
switch (clk->id) {
case CLK_ARM_PLL:
*ctrl = &clk_regs->arm_pll_ctrl;
*cfg = &clk_regs->arm_pll_cfg;
return PLL_STATUS_ARM_PLL_LOCK;
case CLK_DDR_PLL:
*ctrl = &clk_regs->ddr_pll_ctrl;
*cfg = &clk_regs->ddr_pll_cfg;
return PLL_STATUS_DDR_PLL_LOCK;
case CLK_IO_PLL:
*ctrl = &clk_regs->io_pll_ctrl;
if (addr & 0x3) {
printf("Unaligned memory access: 0x%x\n", (uint32_t)addr);
}
addr &= 0xfff;
addr /= 4;
reg[addr] = v;
}
void test(void)
{
reg_write(PPSS_TIMER0_CLK_CTL, CLK_BRANCH_ENA);
reg_write(PPSS_TIMER1_CLK_CTL, CLK_BRANCH_ENA);
}
static struct clock master_clk = { CLK_OPS_DEFAULT(MASTER) };
static struct clock pxo_clk = { CLK_OPS_DEFAULT(PXO) };
static struct clock tcxo_clk = { CLK_OPS_DEFAULT(TCXO) };
static struct clock wcnxo_clk = { CLK_OPS_DEFAULT(WCNXO) };
static struct clock slpxo_clk = { CLK_OPS_DEFAULT(SLPXO) };
static int
apq8064_gate_enable(clock_sys_t* sys, enum clock_gate gate, enum clock_gate_mode mode)
{
(void)sys;
(void)gate;
(void)mode;
return 0;
}
void
