void TM1638_Write(unsigned char DATA) //写数据函数 Q
{
unsigned char i;
DIO_SETOUT();
for(i=0;i<8;i++)
{
//CLK=0
CLK_OUT(0);
if(DATA&0X01)
{
//DIO=1;
DIO_OUT(1);
}
else
{
//DIO=0;
DIO_OUT(0);
}
DATA>>=1;
//CLK=1;
CLK_OUT(1);
delay_tim(10);
}
}
void TM1638_GPIO_Configuration(void)
{
GPIO_InitTypeDef GPIO_InitStructure;
RCC_APB2PeriphClockCmd(DIO_RCC, ENABLE); //使能DIO端口时钟
GPIO_InitStructure.GPIO_Pin = DIO_GPIO_PIN; // 端口配置
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; //推挽输出
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; //IO口速度为50MHz
GPIO_Init(DIO_GPIO, &GPIO_InitStructure); //根据设定参数初始化GPIOB
DIO_OUT(1);
// GPIO_SetBits(GPIOA,GPIO_Pin_4); //初始化设置为0
RCC_APB2PeriphClockCmd(CLK_RCC, ENABLE); //使能PF端口时钟
GPIO_InitStructure.GPIO_Pin = CLK_GPIO_PIN; // 端口配置
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; //推挽输出
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; //IO口速度为50MHz
GPIO_Init(CLK_GPIO, &GPIO_InitStructure); //根据设定参数初始化GPIOB
CLK_OUT(1);
RCC_APB2PeriphClockCmd(STB_RCC, ENABLE); //使能PF端口时钟
GPIO_InitStructure.GPIO_Pin = STB_GPIO_PIN; // 端口配置
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; //推挽输出
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; //IO口速度为50MHz
GPIO_Init(STB_GPIO, &GPIO_InitStructure); //根据设定参数初始化GPIOB
STB_OUT(1);
}
void spi_screenreg_set(u32 Addr, u32 Data)
{
u32 i;
TXD_OUT();
CLK_OUT();
CS_OUT();
DRVDelayUs(2);
DRVDelayUs(2);
CS_SET();
TXD_CLR();
CLK_CLR();
DRVDelayUs(2);
CS_CLR();
for(i = 0; i < 7; i++) //reg
{
if(Addr &(1<<(6-i)))
TXD_SET();
else
TXD_CLR();
// \u6a21\u62dfCLK
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
}
TXD_CLR(); //write
// \u6a21\u62dfCLK
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
for(i = 0; i < 8; i++) //data
{
if(Data &(1<<(7-i)))
TXD_SET();
else
TXD_CLR();
// \u6a21\u62dfCLK
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
}
CS_SET();
CLK_CLR();
TXD_CLR();
DRVDelayUs(2);
}
unsigned char TM1638_Read(void) //读数据函数 Q
{
unsigned char i;
unsigned char temp=0;
DIO_SETIN();
delay_tim(1);
//DIO=1;
for(i=0;i<8;i++)
{
temp>>=1;
// CLK=0
CLK_OUT(0);
delay_tim(10);
if(DIO_IN() == Bit_SET)
temp|=0x80;
//CLK=1
CLK_OUT(1);
delay_tim(1);
}
return temp;
}
static int init(void)
{
if(gLcd_info)
gLcd_info->io_init();
TXD_OUT();
CLK_OUT();
CS_OUT();
RST_CLR();
CS_SET();
CLK_SET();
mdelay(5);
RST_SET();
mdelay(2);
Lcd_WriteSpi_initial3();
return 0;
}
void spi_screenreg_cmd(u8 Addr)
{
u32 i;
u32 control_bit;
TXD_OUT();
CLK_OUT();
CS_OUT();
DRVDelayUs(2);
DRVDelayUs(2);
CS_SET();
TXD_SET();
CLK_CLR();
DRVDelayUs(30);
CS_CLR();
control_bit = 0x0000;
Addr = (control_bit | Addr);//spi_screenreg_set(0x36, 0x0000, 0xffff);
//printk("addr is 0x%x \n", Addr);
for(i = 0; i < 9; i++) //reg
{
if(Addr &(1<<(8-i)))
TXD_SET();
else
TXD_CLR();
// \u6a21\u62dfCLK
CLK_SET();
DRVDelayUs(2);
CLK_CLR();
DRVDelayUs(2);
}
CS_SET();
TXD_SET();
CLK_CLR();
DRVDelayUs(10);
}
void spi_screenreg_set(u32 Addr, u32 Data)
{
#define DRVDelayUs(i) udelay(i*2)
u32 i;
TXD_OUT();
CLK_OUT();
CS_OUT();
DRVDelayUs(2);
DRVDelayUs(2);
CS_SET();
TXD_SET();
CLK_SET();
DRVDelayUs(2);
CS_CLR();
for(i = 0; i < 6; i++) //reg
{
if(Addr &(1<<(5-i)))
TXD_SET();
else
TXD_CLR();
// \u6a21\u62dfCLK
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
}
TXD_CLR(); //write
// \u6a21\u62dfCLK
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
TXD_SET(); //highz
// \u6a21\u62dfCLK
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
for(i = 0; i < 8; i++) //data
{
if(Data &(1<<(7-i)))
TXD_SET();
else
TXD_CLR();
// \u6a21\u62dfCLK
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
}
CS_SET();
CLK_CLR();
TXD_CLR();
DRVDelayUs(2);
}
void spi_screenreg_set(u32 Addr, u32 Data)
{
#define DRVDelayUs(i) udelay(i*2)
u32 i;
u32 control_bit;
TXD_OUT();
CLK_OUT();
CS_OUT();
DRVDelayUs(2);
DRVDelayUs(2);
CS_SET();
TXD_SET();
CLK_SET();
DRVDelayUs(2);
CS_CLR();
control_bit = 0x70<<8;
Addr = (control_bit | Addr);
//printk("addr is 0x%x \n", Addr);
for(i = 0; i < 16; i++) //reg
{
if(Addr &(1<<(15-i)))
TXD_SET();
else
TXD_CLR();
// \u6a21\u62dfCLK
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
}
CS_SET();
TXD_SET();
CLK_SET();
DRVDelayUs(2);
CS_CLR();
control_bit = 0x72<<8;
Data = (control_bit | Data);
//printk("data is 0x%x \n", Data);
for(i = 0; i < 16; i++) //data
{
if(Data &(1<<(15-i)))
TXD_SET();
else
TXD_CLR();
// \u6a21\u62dfCLK
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
}
CS_SET();
CLK_CLR();
TXD_CLR();
DRVDelayUs(2);
}
void spi_screenreg_set(uint32 Addr, uint32 Data)
{
#define CS_OUT() GPIOSetPinDirection(GPIOPortB_Pin3, GPIO_OUT)
#define CS_SET() GPIOSetPinLevel(GPIOPortB_Pin3, GPIO_HIGH)
#define CS_CLR() GPIOSetPinLevel(GPIOPortB_Pin3, GPIO_LOW)
#define CLK_OUT() GPIOSetPinDirection(GPIOPortE_Pin5, GPIO_OUT) //I2C0_SCL
#define CLK_SET() GPIOSetPinLevel(GPIOPortE_Pin5, GPIO_HIGH)
#define CLK_CLR() GPIOSetPinLevel(GPIOPortE_Pin5, GPIO_LOW)
#define TXD_OUT() GPIOSetPinDirection(GPIOPortE_Pin4, GPIO_OUT) //I2C0_SDA
#define TXD_SET() GPIOSetPinLevel(GPIOPortE_Pin4, GPIO_HIGH)
#define TXD_CLR() GPIOSetPinLevel(GPIOPortE_Pin4, GPIO_LOW)
#define DRVDelayUs(i) udelay(i*2)
uint32 i;
TXD_OUT();
CLK_OUT();
CS_OUT();
DRVDelayUs(2);
DRVDelayUs(2);
CS_SET();
TXD_CLR();
CLK_CLR();
DRVDelayUs(2);
CS_CLR();
for(i = 0; i < 7; i++) //reg
{
if(Addr &(1<<(6-i)))
TXD_SET();
else
TXD_CLR();
// \u6a21\u62dfCLK
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
}
TXD_CLR(); //write
// \u6a21\u62dfCLK
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
for(i = 0; i < 8; i++) //data
{
if(Data &(1<<(7-i)))
TXD_SET();
else
TXD_CLR();
// \u6a21\u62dfCLK
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
}
CS_SET();
CLK_CLR();
TXD_CLR();
DRVDelayUs(2);
}
//void spi_screenreg_set(uint32 Addr, uint32 Data)
void spi_screenreg_set(u32 Data)
{
u32 i;
TXD_OUT();
CLK_OUT();
CS_OUT();
DRVDelayUs(2);
DRVDelayUs(2);
CS_SET();
TXD_SET();
CLK_SET();
DRVDelayUs(2);
CS_CLR();
for(i = 0; i < 16; i++) //reg
{
if(Data &(1<<(15-i)))
TXD_SET();
else
TXD_CLR();
// \u6a21\u62dfCLK
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
}
/*
TXD_CLR(); //write
// \u6a21\u62dfCLK
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
TXD_SET(); //highz
// \u6a21\u62dfCLK
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
//for(i = 0; i < 8; i++) //data
for(i = 0; i < 16; i++)
{
if(Data &(1<<(15-i)))
TXD_SET();
else
TXD_CLR();
// \u6a21\u62dfCLK
CLK_CLR();
DRVDelayUs(2);
CLK_SET();
DRVDelayUs(2);
}
*/
CS_SET();
CLK_CLR();
TXD_CLR();
DRVDelayUs(2);
}