void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk) {
// determine the SPI to use
uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
obj->spi.instance = pinmap_merge(spi_data, spi_sclk);
MBED_ASSERT((int)obj->spi.instance != NC);
CLOCK_SYS_EnableSpiClock(obj->spi.instance);
uint32_t spi_address[] = SPI_BASE_ADDRS;
obj->spi.address = spi_address[obj->spi.instance];
DSPI_HAL_Init(obj->spi.address);
DSPI_HAL_Disable(obj->spi.address);
// set default format and frequency
spi_format(obj, 8, 0, SPI_MSB); // 8 bits, mode 0
DSPI_HAL_SetDelay(obj->spi.address, kDspiCtar0, 0, 0, kDspiPcsToSck);
spi_frequency(obj, 1000000);
DSPI_HAL_Enable(obj->spi.address);
DSPI_HAL_StartTransfer(obj->spi.address);
// pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
}
/*FUNCTION**********************************************************************
*
* Function Name : SPI_DRV_MasterInit
* Description : Initialize a SPI instance for master mode operation.
* This function uses a CPU interrupt driven method for transferring data.
* This function initializes the run-time state structure to track the ongoing
* transfers, ungates the clock to the SPI module, resets and initializes the module
* to default settings, configures the IRQ state structure, enables
* the module-level interrupt to the core, and enables the SPI module.
*
*END**************************************************************************/
spi_status_t SPI_DRV_MasterInit(uint32_t instance, spi_master_state_t * spiState)
{
SPI_Type *base = g_spiBase[instance];
/* Clear the state for this instance.*/
memset(spiState, 0, sizeof(* spiState));
/* Enable clock for SPI*/
CLOCK_SYS_EnableSpiClock(instance);
/* configure the run-time state struct with the source clock value */
spiState->spiSourceClock = CLOCK_SYS_GetSpiFreq(instance);
/* Reset the SPI module to it's default state, which includes SPI disabled */
SPI_HAL_Init(base);
/* Init the interrupt sync object.*/
OSA_SemaCreate(&spiState->irqSync, 0);
/* Set SPI to master mode */
SPI_HAL_SetMasterSlave(base, kSpiMaster);
/* Set slave select to automatic output mode */
SPI_HAL_SetSlaveSelectOutputMode(base, kSpiSlaveSelect_AutomaticOutput);
/* Set the SPI pin mode to normal mode */
SPI_HAL_SetPinMode(base, kSpiPinMode_Normal);
#if FSL_FEATURE_SPI_FIFO_SIZE
if (g_spiFifoSize[instance] != 0)
{
/* If SPI module contains a FIFO, enable it and set watermarks to half full/empty */
SPI_HAL_SetFifoMode(base, true, kSpiTxFifoOneHalfEmpty, kSpiRxFifoOneHalfFull);
}
#endif
/* Save runtime structure pointers to irq handler can point to the correct state structure*/
g_spiStatePtr[instance] = spiState;
/* Enable SPI interrupt.*/
INT_SYS_EnableIRQ(g_spiIrqId[instance]);
/* SPI system Enable*/
SPI_HAL_Enable(base);
return kStatus_SPI_Success;
}
void dspi_slave_setup(uint32_t instance, uint32_t baudrate)
{
dspi_data_format_config_t config;
uint32_t baseAddr = SPI0_BASE;
// Enable clock
CLOCK_SYS_EnableSpiClock(instance);
// Clear flags
DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiTxComplete);
DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiTxAndRxStatus);
DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiEndOfQueue);
DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiTxFifoUnderflow);
DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiTxFifoFillRequest);
DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiRxFifoOverflow);
DSPI_HAL_ClearStatusFlag(g_dspiBaseAddr[instance], kDspiRxFifoDrainRequest);
// Enable HAL
DSPI_HAL_Init(baseAddr);
DSPI_HAL_SetMasterSlaveMode(baseAddr, kDspiSlave);
DSPI_HAL_Enable(baseAddr);
// Disable transfer
DSPI_HAL_StopTransfer(baseAddr);
// PCS popularity
DSPI_HAL_SetPcsPolarityMode(baseAddr, kDspiPcs0, kDspiPcs_ActiveLow);
// CTAR
DSPI_HAL_SetBaudRate(baseAddr, kDspiCtar0, baudrate, 72000000);
config.bitsPerFrame = 16;
config.clkPhase = kDspiClockPhase_FirstEdge;
config.clkPolarity = kDspiClockPolarity_ActiveHigh;
config.direction = kDspiMsbFirst;
DSPI_HAL_SetDataFormat(baseAddr, kDspiCtar0, &config);
// Interrupt
INT_SYS_EnableIRQ(g_dspiIrqId[instance]);
DSPI_HAL_SetIntMode(g_dspiBaseAddr[instance], kDspiTxFifoUnderflow, false);
DSPI_HAL_SetIntMode(g_dspiBaseAddr[instance], kDspiTxFifoFillRequest, false);
// DMA
DSPI_HAL_SetTxFifoFillDmaIntMode(g_dspiBaseAddr[instance], kDspiGenerateIntReq, true);
DSPI_HAL_SetRxFifoDrainDmaIntMode(g_dspiBaseAddr[instance], kDspiGenerateDmaReq, true);
}
void SpiInit(Spi_t *obj, PinNames mosi, PinNames miso, PinNames sclk, PinNames nss)
{
/* Check if a proper channel was selected */
if (g_spiBase[obj->instance] == NULL) return;
obj->Spi = g_spiBase[obj->instance];
GpioInit(&obj->Mosi, mosi, PIN_ALTERNATE_FCT, PIN_PUSH_PULL, PIN_PULL_DOWN, 0);
GpioInit(&obj->Miso, miso, PIN_ALTERNATE_FCT, PIN_PUSH_PULL, PIN_PULL_DOWN, 0);
GpioInit(&obj->Sclk, sclk, PIN_ALTERNATE_FCT, PIN_PUSH_PULL, PIN_PULL_DOWN, 0);
if (nss != NC) GpioInit(&obj->Nss, nss, PIN_ALTERNATE_FCT, PIN_PUSH_PULL, PIN_PULL_DOWN, 1);
/* Enable clock for SPI.*/
CLOCK_SYS_EnableSpiClock(obj->instance);
// Initialize the SPI module registers to default value, which disables the module
SPI_HAL_Init(obj->Spi);
// Set the SPI pin mode to normal mode
SPI_HAL_SetPinMode(obj->Spi, kSpiPinMode_Normal);
#if FSL_FEATURE_SPI_FIFO_SIZE
if (g_spiFifoSize[obj->instance] != 0)
{
// If SPI module contains a FIFO, disable it and set watermarks to half full/empty
SPI_HAL_SetFifoMode(obj->Spi, false, kSpiTxFifoOneHalfEmpty, kSpiRxFifoOneHalfFull);
}
#endif
if (!obj->isSlave) {
// 8 bits, CPOL = 0, CPHA = 0, MASTER
SpiFormat(obj, 8, 0, 0, 0);
} else {
// 8 bits, CPOL = 0, CPHA = 0, SLAVE
SpiFormat(obj, 8, 0, 0, 1);
}
SpiFrequency(obj, 10000000);
/* Enable Spi module */
SPI_HAL_Enable(obj->Spi);
}
void SpiInit(Spi_t *obj, PinNames mosi, PinNames miso, PinNames sclk, PinNames nss)
{
/* Check if a proper channel was selected */
if (g_dspiBase[obj->instance] == NULL) return;
obj->Spi = g_dspiBase[obj->instance];
GpioInit(&obj->Mosi, mosi, PIN_ALTERNATE_FCT, PIN_PUSH_PULL, PIN_PULL_DOWN, 0);
GpioInit(&obj->Miso, miso, PIN_ALTERNATE_FCT, PIN_PUSH_PULL, PIN_PULL_DOWN, 0);
GpioInit(&obj->Sclk, sclk, PIN_ALTERNATE_FCT, PIN_PUSH_PULL, PIN_PULL_DOWN, 0);
if (nss != NC) GpioInit(&obj->Nss, nss, PIN_ALTERNATE_FCT, PIN_PUSH_PULL, PIN_PULL_UP, 1);
if (!obj->isSlave) {
// Enable DSPI clock.
CLOCK_SYS_EnableSpiClock(obj->instance);
// Initialize the DSPI module registers to default value, which disables the module
DSPI_HAL_Init(obj->Spi);
// Set to master mode.
DSPI_HAL_SetMasterSlaveMode(obj->Spi, kDspiMaster);
// Configure for continuous SCK operation
DSPI_HAL_SetContinuousSckCmd(obj->Spi, false);
// Configure for peripheral chip select polarity
DSPI_HAL_SetPcsPolarityMode(obj->Spi, kDspiPcs0, kDspiPcs_ActiveLow);
// Disable FIFO operation.
DSPI_HAL_SetFifoCmd(obj->Spi, false, false);
// Initialize the configurable delays: PCS-to-SCK, prescaler = 0, scaler = 1
DSPI_HAL_SetDelay(obj->Spi, kDspiCtar0, 0, 1, kDspiPcsToSck);
// DSPI system enable
DSPI_HAL_Enable(obj->Spi);
// 8 bits, CPOL = 0, CPHA = 0, MASTER
SpiFormat(obj, 8, 0, 0, 0);
} else {
// 8 bits, CPOL = 0, CPHA = 0, SLAVE
SpiFormat(obj, 8, 0, 0, 1);
}
SpiFrequency(obj, 10000000);
}
/*!
* @brief DSPI master Polling.
*
* Thid function uses DSPI master to send an array to slave
* and receive the array back from slave,
* thencompare whether the two buffers are the same.
*/
int main(void)
{
uint32_t i;
uint32_t loopCount = 1;
SPI_Type * dspiBaseAddr = (SPI_Type*)SPI0_BASE;
uint32_t dspiSourceClock;
uint32_t calculatedBaudRate;
dspi_device_t masterDevice;
dspi_command_config_t commandConfig =
{
.isChipSelectContinuous = false,
.whichCtar = kDspiCtar0,
.whichPcs = kDspiPcs0,
.clearTransferCount = true,
.isEndOfQueue = false
};
// Init hardware
hardware_init();
// Init OSA layer, used in DSPI_DRV_MasterTransferBlocking.
OSA_Init();
// Call this function to initialize the console UART. This function
// enables the use of STDIO functions (printf, scanf, etc.)
dbg_uart_init();
// Print a note.
printf("\r\n DSPI board to board polling example");
printf("\r\n This example run on instance 0 ");
printf("\r\n Be sure DSPI0-DSPI0 are connected ");
// Configure SPI pins.
configure_spi_pins(DSPI_MASTER_INSTANCE);
// Enable DSPI clock.
CLOCK_SYS_EnableSpiClock(DSPI_MASTER_INSTANCE);
// Initialize the DSPI module registers to default value, which disables the module
DSPI_HAL_Init(dspiBaseAddr);
// Set to master mode.
DSPI_HAL_SetMasterSlaveMode(dspiBaseAddr, kDspiMaster);
// Configure for continuous SCK operation
DSPI_HAL_SetContinuousSckCmd(dspiBaseAddr, false);
// Configure for peripheral chip select polarity
DSPI_HAL_SetPcsPolarityMode(dspiBaseAddr, kDspiPcs0, kDspiPcs_ActiveLow);
// Disable FIFO operation.
DSPI_HAL_SetFifoCmd(dspiBaseAddr, false, false);
// Initialize the configurable delays: PCS-to-SCK, prescaler = 0, scaler = 1
DSPI_HAL_SetDelay(dspiBaseAddr, kDspiCtar0, 0, 1, kDspiPcsToSck);
// DSPI system enable
DSPI_HAL_Enable(dspiBaseAddr);
// Configure baudrate.
masterDevice.dataBusConfig.bitsPerFrame = 8;
masterDevice.dataBusConfig.clkPhase = kDspiClockPhase_FirstEdge;
masterDevice.dataBusConfig.clkPolarity = kDspiClockPolarity_ActiveHigh;
masterDevice.dataBusConfig.direction = kDspiMsbFirst;
DSPI_HAL_SetDataFormat(dspiBaseAddr, kDspiCtar0, &masterDevice.dataBusConfig);
// Get DSPI source clock.
dspiSourceClock = CLOCK_SYS_GetSpiFreq(DSPI_MASTER_INSTANCE);
calculatedBaudRate = DSPI_HAL_SetBaudRate(dspiBaseAddr, kDspiCtar0, TRANSFER_BAUDRATE, dspiSourceClock);
printf("\r\n Transfer at baudrate %lu \r\n", calculatedBaudRate);
while(1)
{
// Initialize the transmit buffer.
for (i = 0; i < TRANSFER_SIZE; i++)
{
sendBuffer[i] = i + loopCount;
}
// Print out transmit buffer.
printf("\r\n Master transmit:");
for (i = 0; i < TRANSFER_SIZE; i++)
{
// Print 16 numbers in a line.
if ((i & 0x0F) == 0)
{
printf("\r\n ");
}
printf(" %02X", sendBuffer[i]);
}
// Reset the receive buffer.
for (i = 0; i < TRANSFER_SIZE; i++)
{
receiveBuffer[i] = 0;
}
// Restart the transfer by stop then start again, this will clear out the shift register
DSPI_HAL_StopTransfer(dspiBaseAddr);
// Flush the FIFOs
DSPI_HAL_SetFlushFifoCmd(dspiBaseAddr, true, true);
// Clear status flags that may have been set from previous transfers.
DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxComplete);
DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiEndOfQueue);
DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxFifoUnderflow);
DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxFifoFillRequest);
DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiRxFifoOverflow);
DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiRxFifoDrainRequest);
// Clear the transfer count.
DSPI_HAL_PresetTransferCount(dspiBaseAddr, 0);
// Start the transfer process in the hardware
DSPI_HAL_StartTransfer(dspiBaseAddr);
// Send the data to slave.
for (i = 0; i < TRANSFER_SIZE; i++)
{
// Write data to PUSHR
DSPI_HAL_WriteDataMastermodeBlocking(dspiBaseAddr, &commandConfig, sendBuffer[i]);
// Delay to wait slave is ready.
OSA_TimeDelay(1);
}
// Delay to wait slave is ready.
OSA_TimeDelay(10);
// Restart the transfer by stop then start again, this will clear out the shift register
DSPI_HAL_StopTransfer(dspiBaseAddr);
// Flush the FIFOs
DSPI_HAL_SetFlushFifoCmd(dspiBaseAddr, true, true);
//Clear status flags that may have been set from previous transfers.
DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxComplete);
DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiEndOfQueue);
DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxFifoUnderflow);
DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxFifoFillRequest);
DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiRxFifoOverflow);
DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiRxFifoDrainRequest);
// Clear the transfer count.
DSPI_HAL_PresetTransferCount(dspiBaseAddr, 0);
// Start the transfer process in the hardware
DSPI_HAL_StartTransfer(dspiBaseAddr);
// Receive the data from slave.
for (i = 0; i < TRANSFER_SIZE; i++)
{
// Write command to PUSHR.
DSPI_HAL_WriteDataMastermodeBlocking(dspiBaseAddr, &commandConfig, 0);
// Check RFDR flag
while (DSPI_HAL_GetStatusFlag(dspiBaseAddr, kDspiRxFifoDrainRequest)== false)
{}
// Read data from POPR
receiveBuffer[i] = DSPI_HAL_ReadData(dspiBaseAddr);
// Clear RFDR flag
DSPI_HAL_ClearStatusFlag(dspiBaseAddr,kDspiRxFifoDrainRequest);
// Delay to wait slave is ready.
OSA_TimeDelay(1);
}
// Print out receive buffer.
printf("\r\n Master receive:");
for (i = 0; i < TRANSFER_SIZE; i++)
{
// Print 16 numbers in a line.
if ((i & 0x0F) == 0)
{
printf("\r\n ");
}
printf(" %02X", receiveBuffer[i]);
}
// Check receiveBuffer.
for (i = 0; i < TRANSFER_SIZE; ++i)
{
if (receiveBuffer[i] != sendBuffer[i])
{
// Master received incorrect.
printf("\r\n ERROR: master received incorrect ");
return -1;
}
}
printf("\r\n DSPI Master Sends/ Recevies Successfully");
// Wait for press any key.
printf("\r\n Press any key to run again");
getchar();
// Increase loop count to change transmit buffer.
loopCount++;
}
}
/*FUNCTION**********************************************************************
*
* Function Name : DSPI_DRV_DmaMasterInit
* Description : Initializes a DSPI instance for master mode operation to work with DMA.
* This function uses a dma driven method for transferring data.
* This function initializes the run-time state structure to track the ongoing
* transfers, ungates the clock to the DSPI module, resets the DSPI module, initializes the module
* to user defined settings and default settings, configures the IRQ state structure, enables
* the module-level interrupt to the core, and enables the DSPI module.
* The CTAR parameter is special in that it allows the user to have different SPI devices
* connected to the same DSPI module instance in addition to different peripheral chip
* selects. Each CTAR contains the bus attributes associated with that particular SPI device.
* For most use cases where only one SPI device is connected per DSPI module
* instance, use CTAR0.
* This is an example to set up and call the DSPI_DRV_DmaMasterInit function by passing
* in these parameters:
* dspi_dma_master_state_t dspiDmaState; <- the user simply allocates memory for this struct
* uint32_t calculatedBaudRate;
* dspi_dma_master_user_config_t userConfig; <- the user fills out members for this struct
* userConfig.isChipSelectContinuous = false;
* userConfig.isSckContinuous = false;
* userConfig.pcsPolarity = kDspiPcs_ActiveLow;
* userConfig.whichCtar = kDspiCtar0;
* userConfig.whichPcs = kDspiPcs0;
* DSPI_DRV_DmaMasterInit(masterInstance, &dspiDmaState, &userConfig);
*
*END**************************************************************************/
dspi_status_t DSPI_DRV_DmaMasterInit(uint32_t instance,
dspi_dma_master_state_t * dspiDmaState,
const dspi_dma_master_user_config_t * userConfig)
{
uint32_t dspiSourceClock;
SPI_Type *base = g_dspiBase[instance];
dma_request_source_t dspiTxDmaRequest = kDmaRequestMux0Disable;
dma_request_source_t dspiRxDmaRequest = kDmaRequestMux0Disable;
/* Check parameter pointers to make sure there are not NULL */
if ((dspiDmaState == NULL) || (userConfig == NULL))
{
return kStatus_DSPI_InvalidParameter;
}
/* Clear the run-time state struct for this instance.*/
memset(dspiDmaState, 0, sizeof(* dspiDmaState));
/* Note, remember to first enable clocks to the DSPI module before making any register accesses
* Enable clock for DSPI
*/
CLOCK_SYS_EnableSpiClock(instance);
/* Get module clock freq*/
dspiSourceClock = CLOCK_SYS_GetSpiFreq(instance);
/* Configure the run-time state struct with the DSPI source clock */
dspiDmaState->dspiSourceClock = dspiSourceClock;
/* Configure the run-time state struct with the data command parameters*/
dspiDmaState->whichCtar = userConfig->whichCtar; /* set the dspiDmaState struct CTAR*/
dspiDmaState->whichPcs = userConfig->whichPcs; /* set the dspiDmaState struct whichPcs*/
dspiDmaState->isChipSelectContinuous = userConfig->isChipSelectContinuous; /* continuous PCS*/
/* Initialize the DSPI module registers to default value, which disables the module */
DSPI_HAL_Init(base);
/* Init the interrupt sync object.*/
if (OSA_SemaCreate(&dspiDmaState->irqSync, 0) != kStatus_OSA_Success)
{
return kStatus_DSPI_Error;
}
/* Set to master mode.*/
DSPI_HAL_SetMasterSlaveMode(base, kDspiMaster);
/* Configure for continuous SCK operation*/
DSPI_HAL_SetContinuousSckCmd(base, userConfig->isSckContinuous);
/* Configure for peripheral chip select polarity*/
DSPI_HAL_SetPcsPolarityMode(base, userConfig->whichPcs, userConfig->pcsPolarity);
/* Enable fifo operation (regardless of FIFO depth) */
DSPI_HAL_SetFifoCmd(base, true, true);
/* Initialize the configurable delays: PCS-to-SCK, prescaler = 0, scaler = 1 */
DSPI_HAL_SetDelay(base, userConfig->whichCtar, 0, 1, kDspiPcsToSck);
/* Save runtime structure pointers to irq handler can point to the correct state structure*/
g_dspiStatePtr[instance] = dspiDmaState;
/* enable the interrupt*/
INT_SYS_EnableIRQ(g_dspiIrqId[instance]);
/* DSPI system enable */
DSPI_HAL_Enable(base);
/* Request DMA channels from the DMA peripheral driver.
* Note, some MCUs have a separate RX and TX DMA request for each DSPI instance, while
* other MCUs have a separate RX and TX DMA request for DSPI instance 0 only and shared DMA
* requests for all other instances. Therefore, use the DSPI feature file to distinguish
* how to request DMA channels between the various MCU DSPI instances.
* For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to
* trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel.
*/
switch (instance)
{
case 0:
/* SPI0 */
#if FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(0)
dspiRxDmaRequest = kDmaRequestMux0SPI0Rx;
dspiTxDmaRequest = kDmaRequestMux0SPI0Tx;
#else
/* DMA is simple link control, so DSPI - DMA driver does not support the case that DSPI have
* shared DMA channels
*/
return kStatus_DSPI_DMAChannelInvalid;
#endif
break;
#if (SPI_INSTANCE_COUNT > 1)
case 1:
/* SPI1 */
#if FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(1)
dspiRxDmaRequest = kDmaRequestMux0SPI1Rx;
dspiTxDmaRequest = kDmaRequestMux0SPI1Tx;
#else
/* DMA is simple link control, so DSPI - DMA driver does not support the case that DSPI have
* shared DMA channels
*/
return kStatus_DSPI_DMAChannelInvalid;
#endif
break;
#endif
#if (SPI_INSTANCE_COUNT > 2)
case 2:
/* SPI2 */
#if FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(2)
dspiRxDmaRequest = kDmaRequestMux0SPI2Rx;
dspiTxDmaRequest = kDmaRequestMux0SPI2Tx;
#else
/* DMA is simple link control, so DSPI - DMA driver does not support the case that DSPI have
* shared DMA channels
*/
return kStatus_DSPI_DMAChannelInvalid;
#endif
break;
#endif
default :
return kStatus_DSPI_InvalidInstanceNumber;
}
/* This channel transfers data from RX FIFO to receiveBuffer */
if (kDmaInvalidChannel == DMA_DRV_RequestChannel(kDmaAnyChannel,
dspiRxDmaRequest,
&dspiDmaState->dmaRxChannel))
{
return kStatus_DSPI_DMAChannelInvalid;
}
/* This channel transfers data from transmitBuffer to TX FIFO */
if (kDmaInvalidChannel == DMA_DRV_RequestChannel(kDmaAnyChannel,
dspiTxDmaRequest,
&dspiDmaState->dmaTxDataChannel))
{
return kStatus_DSPI_DMAChannelInvalid;
}
/* Source buffer to intermediate command/data
* This channel is not activated by dma request, but by channel link.
*/
if (DMA_DRV_RequestChannel(kDmaAnyChannel,
kDmaRequestMux0Disable,
&dspiDmaState->dmaTxCmdChannel) == kDmaInvalidChannel)
{
return kStatus_DSPI_DMAChannelInvalid;
}
/* Start the transfer process in the hardware */
DSPI_HAL_StartTransfer(base);
return kStatus_DSPI_Success;
}
/*FUNCTION**********************************************************************
*
* Function Name : SPI_DRV_DmaSlaveInit
* Description : Initializes the SPI module for slave mode.
* Saves the application callback info, turns on the clock to the module,
* enables the device, and enables interrupts. Sets the SPI to a slave mode.
*
*END**************************************************************************/
spi_status_t SPI_DRV_DmaSlaveInit(uint32_t instance, spi_dma_slave_state_t * spiState,
const spi_dma_slave_user_config_t * slaveConfig)
{
SPI_Type *base = g_spiBase[instance];
assert(slaveConfig);
assert(instance < SPI_INSTANCE_COUNT);
assert(spiState);
#if FSL_FEATURE_SPI_16BIT_TRANSFERS
if (slaveConfig->bitCount > kSpi16BitMode)
{
/* bits/frame larger than hardware support */
return kStatus_SPI_InvalidParameter;
}
#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
/* Check if the slave already initialized */
if (g_spiStatePtr[instance])
{
return kStatus_SPI_AlreadyInitialized;
}
/* Clear the state for this instance. */
memset(spiState, 0, sizeof(* spiState));
spiState->hasExtraByte = false;
/* Update dummy pattern value */
spiState->dummyPattern = slaveConfig->dummyPattern;
/* Enable clock for SPI */
CLOCK_SYS_EnableSpiClock(instance);
/* Reset the SPI module to its default settings including disabling SPI */
SPI_HAL_Init(base);
/* Initialize the event structure */
if (OSA_EventCreate(&spiState->event, kEventAutoClear) != kStatus_OSA_Success)
{
return kStatus_SPI_Error;
}
/* Set SPI to slave mode */
SPI_HAL_SetMasterSlave(base, kSpiSlave);
/* Configure the slave clock polarity, phase and data direction */
SPI_HAL_SetDataFormat(base, slaveConfig->polarity, slaveConfig->phase,
slaveConfig->direction);
/* Set the SPI pin mode to normal mode */
SPI_HAL_SetPinMode(base, kSpiPinMode_Normal);
#if FSL_FEATURE_SPI_16BIT_TRANSFERS
SPI_HAL_Set8or16BitMode(base, slaveConfig->bitCount);
#endif /* FSL_FEATURE_SPI_16BIT_TRANSFERS */
#if FSL_FEATURE_SPI_FIFO_SIZE
if (g_spiFifoSize[instance] != 0)
{
/* If SPI module contains a FIFO, enable it and set watermarks to half full/empty */
SPI_HAL_SetFifoMode(base, true, kSpiTxFifoOneHalfEmpty, kSpiRxFifoOneHalfFull);
/* Set the interrupt clearing mechansim select for later use in driver to clear
* status flags
*/
SPI_HAL_SetIntClearCmd(base, true);
}
#endif /* FSL_FEATURE_SPI_FIFO_SIZE */
/*****************************************
* Request DMA channel for RX and TX FIFO
*****************************************/
/* This channel transfers data from RX FIFO to receiveBuffer */
if (instance == 0)
{
/* Request DMA channel for RX FIFO */
if (kDmaInvalidChannel == DMA_DRV_RequestChannel(kDmaAnyChannel,
kDmaRequestMux0SPI0Rx,
&spiState->dmaReceive))
{
return kStatus_SPI_DMAChannelInvalid;
}
/* Request DMA channel for TX FIFO */
if (kDmaInvalidChannel == DMA_DRV_RequestChannel(kDmaAnyChannel,
kDmaRequestMux0SPI0Tx,
&spiState->dmaTransmit))
{
return kStatus_SPI_DMAChannelInvalid;
}
}
#if (SPI_INSTANCE_COUNT > 1)
else if (instance == 1)
{
/* Request DMA channel for RX FIFO */
if (kDmaInvalidChannel == DMA_DRV_RequestChannel(kDmaAnyChannel,
kDmaRequestMux0SPI1Rx,
&spiState->dmaReceive))
{
return kStatus_SPI_DMAChannelInvalid;
}
/* Request DMA channel for TX FIFO */
if (kDmaInvalidChannel == DMA_DRV_RequestChannel(kDmaAnyChannel,
kDmaRequestMux0SPI1Tx,
&spiState->dmaTransmit))
{
return kStatus_SPI_DMAChannelInvalid;
}
}
else
{
return kStatus_SPI_OutOfRange;
}
#endif
/* Save runtime structure pointers to irq handler can point to the correct state structure */
g_spiStatePtr[instance] = spiState;
/* Enable SPI interrupt. The transmit interrupt should immediately cause an interrupt
* which will fill in the transmit buffer and will be ready to send once the slave initiates
* transmission.
*/
INT_SYS_EnableIRQ(g_spiIrqId[instance]);
/* SPI module enable */
SPI_HAL_Enable(base);
return kStatus_SPI_Success;
}
/*FUNCTION**********************************************************************
*
* Function Name : SPI_DRV_DmaMasterInit
* Description : Initializes a SPI instance for master mode operation to work with DMA.
* This function uses a dma driven method for transferring data.
* this function initializes the run-time state structure to track the ongoing
* transfers, ungates the clock to the SPI module, resets the SPI module, initializes the module
* to user defined settings and default settings, configures the IRQ state structure, enables
* the module-level interrupt to the core, and enables the SPI module.
*
* This initialization function also configures the DMA module by requesting channels for DMA
* operation.
*
*END**************************************************************************/
spi_status_t SPI_DRV_DmaMasterInit(uint32_t instance, spi_dma_master_state_t * spiDmaState)
{
SPI_Type *base = g_spiBase[instance];
/* Clear the state for this instance.*/
memset(spiDmaState, 0, sizeof(* spiDmaState));
/* Enable clock for SPI*/
CLOCK_SYS_EnableSpiClock(instance);
/* configure the run-time state struct with the source clock value */
spiDmaState->spiSourceClock = CLOCK_SYS_GetSpiFreq(instance);
/* Reset the SPI module to it's default state, which includes SPI disabled */
SPI_HAL_Init(base);
/* Init the interrupt sync object.*/
if (OSA_SemaCreate(&spiDmaState->irqSync, 0) != kStatus_OSA_Success)
{
return kStatus_SPI_Error;
}
/* Set SPI to master mode */
SPI_HAL_SetMasterSlave(base, kSpiMaster);
/* Set slave select to automatic output mode */
SPI_HAL_SetSlaveSelectOutputMode(base, kSpiSlaveSelect_AutomaticOutput);
/* Set the SPI pin mode to normal mode */
SPI_HAL_SetPinMode(base, kSpiPinMode_Normal);
#if FSL_FEATURE_SPI_FIFO_SIZE
if (g_spiFifoSize[instance] != 0)
{
/* If SPI module contains a FIFO, enable it and set watermarks to half full/empty */
SPI_HAL_SetFifoMode(base, true, kSpiTxFifoOneHalfEmpty, kSpiRxFifoOneHalfFull);
/* Set the interrupt clearing mechansim select for later use in driver to clear
* status flags
*/
SPI_HAL_SetIntClearCmd(base, true);
}
#endif
/* Save runtime structure pointers to irq handler can point to the correct state structure*/
g_spiStatePtr[instance] = spiDmaState;
/*****************************************
* Request DMA channel for RX and TX FIFO
*****************************************/
/* This channel transfers data from RX FIFO to receiveBuffer */
if (instance == 0)
{
/* Request DMA channel for RX FIFO */
DMA_DRV_RequestChannel(kDmaAnyChannel, kDmaRequestMux0SPI0Rx, &spiDmaState->dmaReceive);
/* Request DMA channel for TX FIFO */
DMA_DRV_RequestChannel(kDmaAnyChannel, kDmaRequestMux0SPI0Tx, &spiDmaState->dmaTransmit);
}
#if (SPI_INSTANCE_COUNT > 1)
else
{
/* Request DMA channel for RX FIFO */
DMA_DRV_RequestChannel(kDmaAnyChannel, kDmaRequestMux0SPI1Rx, &spiDmaState->dmaReceive);
/* Request DMA channel for TX FIFO */
DMA_DRV_RequestChannel(kDmaAnyChannel, kDmaRequestMux0SPI1Tx, &spiDmaState->dmaTransmit);
}
#endif
/* Enable SPI interrupt.*/
INT_SYS_EnableIRQ(g_spiIrqId[instance]);
/* SPI system Enable */
SPI_HAL_Enable(base);
return kStatus_SPI_Success;
}
/*!
* @brief DSPI slave Polling.
*
* This function sends back received buffer from master through DSPI interface.
*/
int main(void)
{
uint32_t i;
SPI_Type * dspiBaseAddr = (SPI_Type*)SPI0_BASE;
dspi_slave_user_config_t slaveConfig;
// Init hardware
hardware_init();
// Init OSA layer, used in DSPI_DRV_MasterTransferBlocking.
OSA_Init();
// Call this function to initialize the console UART. This function
// enables the use of STDIO functions (printf, scanf, etc.)
dbg_uart_init();
// Configure SPI pins.
configure_spi_pins(DSPI_SLAVE_INSTANCE);
// Print a note.
printf("\r\n DSPI board to board polling example");
printf("\r\n This example run on instance 0 ");
printf("\r\n Be sure DSPI0-DSPI0 are connected ");
// Enable clock for DSPI
CLOCK_SYS_EnableSpiClock(DSPI_SLAVE_INSTANCE);
// Reset the DSPI module, which also disables the DSPI module
DSPI_HAL_Init(dspiBaseAddr);
// Set to slave mode.
DSPI_HAL_SetMasterSlaveMode(dspiBaseAddr, kDspiSlave);
// Set data format
slaveConfig.dataConfig.clkPhase = kDspiClockPhase_FirstEdge;
slaveConfig.dataConfig.clkPolarity = kDspiClockPolarity_ActiveHigh;
slaveConfig.dataConfig.bitsPerFrame = 8;
DSPI_HAL_SetDataFormat(dspiBaseAddr, kDspiCtar0, &(slaveConfig.dataConfig));
// DSPI system enable
DSPI_HAL_Enable(dspiBaseAddr);
// Disable FIFO operation.
DSPI_HAL_SetFifoCmd(dspiBaseAddr, false, false);
while(1)
{
printf("\r\n Slave example is running...");
// Reset the receive buffer.
for (i = 0; i < TRANSFER_SIZE; i++)
{
receiveBuffer[i] = 0;
}
// Restart the transfer by stop then start again, this will clear out the shift register
DSPI_HAL_StopTransfer(dspiBaseAddr);
// Flush the FIFOs
DSPI_HAL_SetFlushFifoCmd(dspiBaseAddr, true, true);
// Clear status flags that may have been set from previous transfers
DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxComplete);
DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiEndOfQueue);
DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxFifoUnderflow);
DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxFifoFillRequest);
DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiRxFifoOverflow);
DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiRxFifoDrainRequest);
// Clear the transfer count
DSPI_HAL_PresetTransferCount(dspiBaseAddr, 0);
// Start the transfer process in the hardware
DSPI_HAL_StartTransfer(dspiBaseAddr);
for (i = 0; i < TRANSFER_SIZE; i++)
{
// Check RFDR flag
while (DSPI_HAL_GetStatusFlag(dspiBaseAddr, kDspiRxFifoDrainRequest)== false)
{}
// Read data from POPR
receiveBuffer[i] = DSPI_HAL_ReadData(dspiBaseAddr);
// Clear RFDR flag
DSPI_HAL_ClearStatusFlag(dspiBaseAddr,kDspiRxFifoDrainRequest);
}
// Restart the transfer by stop then start again, this will clear out the shift register
DSPI_HAL_StopTransfer(dspiBaseAddr);
// Flush the FIFOs
DSPI_HAL_SetFlushFifoCmd(dspiBaseAddr, true, true);
// Clear status flags that may have been set from previous transfers
DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxComplete);
DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiEndOfQueue);
DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxFifoUnderflow);
DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiTxFifoFillRequest);
DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiRxFifoOverflow);
DSPI_HAL_ClearStatusFlag(dspiBaseAddr, kDspiRxFifoDrainRequest);
// Clear the transfer count
DSPI_HAL_PresetTransferCount(dspiBaseAddr, 0);
// Start the transfer process in the hardware
DSPI_HAL_StartTransfer(dspiBaseAddr);
// Send the data to slave.
for (i = 0; i < TRANSFER_SIZE; i++)
{
// Write data to PUSHR
DSPI_HAL_WriteDataSlavemodeBlocking(dspiBaseAddr, receiveBuffer[i]);
}
// Print out receive buffer.
printf("\r\n Slave receive:");
for (i = 0; i < TRANSFER_SIZE; i++)
{
// Print 16 numbers in a line.
if ((i & 0x0F) == 0)
{
printf("\r\n ");
}
printf(" %02X", receiveBuffer[i]);
}
}
}
/*FUNCTION**********************************************************************
*
* Function Name : DSPI_DRV_MasterInit
* Description : Initialize a DSPI instance for master mode operation.
* This function uses a CPU interrupt driven method for transferring data.
* This function will initialize the run-time state structure to keep track of the on-going
* transfers, ungate the clock to the DSPI module, reset the DSPI module, initialize the module
* to user defined settings and default settings, configure the IRQ state structure and enable
* the module-level interrupt to the core, and enable the DSPI module.
* The CTAR parameter is special in that it allows the user to have different SPI devices
* connected to the same DSPI module instance in conjunction with different peripheral chip
* selects. Each CTAR contains the bus attributes associated with that particular SPI device.
* For simplicity and for most use cases where only one SPI device is connected per DSPI module
* instance, it is recommended to use CTAR0.
* The following is an example of how to set up the dspi_master_state_t and the
* dspi_master_user_config_t parameters and how to call the DSPI_DRV_MasterInit function by passing
* in these parameters:
* dspi_master_state_t dspiMasterState; <- the user simply allocates memory for this struct
* uint32_t calculatedBaudRate;
* dspi_master_user_config_t userConfig; <- the user fills out members for this struct
* userConfig.isChipSelectContinuous = false;
* userConfig.isSckContinuous = false;
* userConfig.pcsPolarity = kDspiPcs_ActiveLow;
* userConfig.whichCtar = kDspiCtar0;
* userConfig.whichPcs = kDspiPcs0;
* DSPI_DRV_MasterInit(masterInstance, &dspiMasterState, &userConfig);
*
*END**************************************************************************/
dspi_status_t DSPI_DRV_MasterInit(uint32_t instance,
dspi_master_state_t * dspiState,
const dspi_master_user_config_t * userConfig)
{
uint32_t dspiSourceClock;
dspi_status_t errorCode = kStatus_DSPI_Success;
SPI_Type *base = g_dspiBase[instance];
/* Clear the run-time state struct for this instance.*/
memset(dspiState, 0, sizeof(* dspiState));
/* Note, remember to first enable clocks to the DSPI module before making any register accesses
* Enable clock for DSPI
*/
CLOCK_SYS_EnableSpiClock(instance);
/* Get module clock freq*/
dspiSourceClock = CLOCK_SYS_GetSpiFreq(instance);
/* Configure the run-time state struct with the DSPI source clock */
dspiState->dspiSourceClock = dspiSourceClock;
/* Configure the run-time state struct with the data command parameters*/
dspiState->whichCtar = userConfig->whichCtar; /* set the dspiState struct CTAR*/
dspiState->whichPcs = userConfig->whichPcs; /* set the dspiState struct whichPcs*/
dspiState->isChipSelectContinuous = userConfig->isChipSelectContinuous; /* continuous PCS*/
/* Initialize the DSPI module registers to default value, which disables the module */
DSPI_HAL_Init(base);
/* Init the interrupt sync object.*/
OSA_SemaCreate(&dspiState->irqSync, 0);
/* Initialize the DSPI module with user config */
/* Set to master mode.*/
DSPI_HAL_SetMasterSlaveMode(base, kDspiMaster);
/* Configure for continuous SCK operation*/
DSPI_HAL_SetContinuousSckCmd(base, userConfig->isSckContinuous);
/* Configure for peripheral chip select polarity*/
DSPI_HAL_SetPcsPolarityMode(base, userConfig->whichPcs, userConfig->pcsPolarity);
/* Enable fifo operation (regardless of FIFO depth) */
DSPI_HAL_SetFifoCmd(base, true, true);
/* Initialize the configurable delays: PCS-to-SCK, prescaler = 0, scaler = 1 */
DSPI_HAL_SetDelay(base, userConfig->whichCtar, 0, 1, kDspiPcsToSck);
/* Save runtime structure pointers to irq handler can point to the correct state structure*/
g_dspiStatePtr[instance] = dspiState;
/* enable the interrupt*/
INT_SYS_EnableIRQ(g_dspiIrqId[instance]);
/* DSPI system enable */
DSPI_HAL_Enable(base);
/* Start the transfer process in the hardware */
DSPI_HAL_StartTransfer(base);
return errorCode;
}
/*!
* @brief SPI slave polling.
*
* This function sends back received buffer from master through SPI interface.
*/
int main (void)
{
uint32_t j;
SPI_Type * spiBaseAddr = g_spiBase[SPI_SLAVE_INSTANCE];
// init the hardware, this also sets up up the SPI pins for each specific SoC
hardware_init();
OSA_Init();
PRINTF("\r\nSPI board to board polling example");
PRINTF("\r\nThis example run on instance %d", (uint32_t)SPI_SLAVE_INSTANCE);
PRINTF("\r\nBe sure master's SPI%d and slave's SPI%d are connected",
(uint32_t)SPI_SLAVE_INSTANCE, (uint32_t)SPI_SLAVE_INSTANCE);
// Enable clock for SPI
CLOCK_SYS_EnableSpiClock(SPI_SLAVE_INSTANCE);
// Reset the SPI module to its default settings including disabling SPI
SPI_HAL_Init(spiBaseAddr);
// Set SPI to slave mode
SPI_HAL_SetMasterSlave(spiBaseAddr, kSpiSlave);
// Set the SPI pin mode to normal mode
SPI_HAL_SetPinMode(spiBaseAddr, kSpiPinMode_Normal);
#if FSL_FEATURE_SPI_FIFO_SIZE
if (g_spiFifoSize[SPI_SLAVE_INSTANCE] != 0)
{
// If SPI module contains a FIFO, disable it and set watermarks to half full/empty
SPI_HAL_SetFifoMode(spiBaseAddr, false, kSpiTxFifoOneHalfEmpty, kSpiRxFifoOneHalfFull);
}
#endif
//USER CONFIGURABLE OPTION FOR 8 or 16-BIT MODE (if applicable)
#if FSL_FEATURE_SPI_16BIT_TRANSFERS
SPI_HAL_Set8or16BitMode(spiBaseAddr, kSpi8BitMode);
#endif
// SPI system Enable
SPI_HAL_Enable(spiBaseAddr);
// Setup format as same as master
SPI_HAL_SetDataFormat(spiBaseAddr, kSpiClockPolarity_ActiveHigh, kSpiClockPhase_FirstEdge, kSpiMsbFirst);
while(1)
{
PRINTF("\r\nSlave example is running...\r\n");
// Reset the sink buffer
for (j = 0; j < TRANSFER_SIZE; j++)
{
s_spiSinkBuffer[j] = 0;
}
SPI_HAL_Disable(spiBaseAddr);
SPI_HAL_Enable(spiBaseAddr);
// Disable module to clear shift register
for (j = 0; j <TRANSFER_SIZE; j++)
{
// Check if data received
while(SPI_HAL_IsReadBuffFullPending(spiBaseAddr)==0){}
#if FSL_FEATURE_SPI_16BIT_TRANSFERS
// Read data from data register
s_spiSinkBuffer[j] = SPI_HAL_ReadDataLow(spiBaseAddr);
#else
s_spiSinkBuffer[j] = SPI_HAL_ReadData(spiBaseAddr);
#endif
}
// Disable module to clear shift register
SPI_HAL_Disable(spiBaseAddr);
SPI_HAL_Enable(spiBaseAddr);
// Send data back to master
for (j = 0; j <TRANSFER_SIZE; j++)
{
#if FSL_FEATURE_SPI_16BIT_TRANSFERS
SPI_HAL_WriteDataBlocking(spiBaseAddr, kSpi8BitMode, 0, s_spiSinkBuffer[j]);
#else
SPI_HAL_WriteDataBlocking(spiBaseAddr, s_spiSinkBuffer[j]);
#endif
}
// Print out receive buffer
PRINTF("\r\nSlave receive:");
for (j = 0; j < TRANSFER_SIZE; j++)
{
// Print 16 numbers in a line.
if ((j & 0x0F) == 0)
{
PRINTF("\r\n ");
}
PRINTF(" %02X", s_spiSinkBuffer[j]);
}
}
}
