static irqreturn_t cmdq_irq_handler(int IRQ, void *pDevice)
{
int index;
uint32_t irqStatus;
bool handled = false; /* we share IRQ bit with CQ-DMA, */
/* so it is possible that this handler */
/* is called but GCE does not have IRQ flag. */
do {
if (cmdq_dev_get_irq_id() == IRQ) {
irqStatus = CMDQ_REG_GET32(CMDQ_CURR_IRQ_STATUS) & 0x0FFFF;
for (index = 0; (irqStatus != 0xFFFF) && index < CMDQ_MAX_THREAD_COUNT;
index++) {
/* STATUS bit set to 0 means IRQ asserted */
if (irqStatus & (1 << index))
continue;
/* so we mark irqStatus to 1 to denote finished processing */
/* and we can early-exit if no more threads being asserted */
irqStatus |= (1 << index);
cmdqCoreHandleIRQ(index);
handled = true;
}
} else if (cmdq_dev_get_irq_secure_id() == IRQ) {
CMDQ_ERR("receive secure IRQ %d in NWD\n", IRQ);
}
} while (0);
if (handled) {
cmdq_core_add_consume_task();
return IRQ_HANDLED;
}
/* allow CQ-DMA to process this IRQ bit */
return IRQ_NONE;
}
void cmdq_core_dump_clock_gating(void)
{
uint32_t value[3] = { 0 };
value[0] = CMDQ_REG_GET32(MMSYS_CONFIG_BASE + 0x100);
value[1] = CMDQ_REG_GET32(MMSYS_CONFIG_BASE + 0x110);
/* value[2] = CMDQ_REG_GET32(MMSYS_CONFIG_BASE + 0x890); */
CMDQ_ERR("MMSYS_CG_CON0(deprecated): 0x%08x, MMSYS_CG_CON1: 0x%08x\n", value[0], value[1]);
/* CMDQ_ERR("MMSYS_DUMMY_REG: 0x%08x\n", value[2]); */
#ifdef CONFIG_MTK_LEGACY
#ifndef CONFIG_MTK_FPGA
CMDQ_ERR("ISPSys clock state %d\n", subsys_is_on(SYS_IMG));
CMDQ_ERR("DisSys clock state %d\n", subsys_is_on(SYS_DIS));
/* CMDQ_ERR("VDESys clock state %d\n", subsys_is_on(SYS_VDE)); */
#endif
#endif /* defined(CONFIG_MTK_LEGACY) */
}
void cmdq_virtual_dump_gpr(void)
{
int i = 0;
long offset = 0;
uint32_t value = 0;
CMDQ_LOG("========= GPR dump =========\n");
for (i = 0; i < 16; i++) {
offset = CMDQ_GPR_R32(i);
value = CMDQ_REG_GET32(offset);
CMDQ_LOG("[GPR %2d]+0x%lx = 0x%08x\n", i, offset, value);
}
CMDQ_LOG("========= GPR dump =========\n");
}
void cmdq_virtual_dump_clock_gating(void)
{
uint32_t value[3] = { 0 };
value[0] = CMDQ_REG_GET32(MMSYS_CONFIG_BASE + 0x100);
value[1] = CMDQ_REG_GET32(MMSYS_CONFIG_BASE + 0x110);
CMDQ_ERR("MMSYS_CG_CON0(deprecated): 0x%08x, MMSYS_CG_CON1: 0x%08x\n", value[0], value[1]);
#ifdef CMDQ_USE_LEGACY
value[2] = CMDQ_REG_GET32(MMSYS_CONFIG_BASE + 0x890);
CMDQ_ERR("MMSYS_DUMMY_REG: 0x%08x\n", value[2]);
#endif
#if !defined(CMDQ_USE_CCF) && !defined(CONFIG_MTK_FPGA)
CMDQ_ERR("DisSys clock state %d\n", subsys_is_on(SYS_DIS));
#ifdef CMDQ_DUMP_IMG_CLOCK_STATE
CMDQ_ERR("IMGSys clock state %d\n", subsys_is_on(SYS_IMG));
#else
CMDQ_ERR("ISPSys clock state %d\n", subsys_is_on(SYS_ISP));
CMDQ_ERR("VDESys clock state %d\n", subsys_is_on(SYS_VDE));
#endif
#endif
}