int frvbf_model_fr450_u_media_4_mclracca (SIM_CPU *cpu, const IDESC *idesc, int unit_num, int referenced) { int cycles; int acc; FRV_PROFILE_STATE *ps; if (model_insn == FRV_INSN_MODEL_PASS_1) return 0; /* The preprocessing can execute right away. */ cycles = idesc->timing->units[unit_num].done; ps = CPU_PROFILE_STATE (cpu); /* The post processing must wait for any pending ACC writes. */ ps->post_wait = cycles; for (acc = 0; acc < 4; acc++) post_wait_for_ACC (cpu, acc); for (acc = 8; acc < 12; acc++) post_wait_for_ACC (cpu, acc); for (acc = 0; acc < 4; acc++) { update_ACC_latency (cpu, acc, ps->post_wait); update_ACC_ptime (cpu, acc, 2); } for (acc = 8; acc < 12; acc++) { update_ACC_latency (cpu, acc, ps->post_wait); update_ACC_ptime (cpu, acc, 2); } return cycles; }
/* Initialize the frv simulator. */ void frv_initialize (SIM_CPU *current_cpu, SIM_DESC sd) { FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu); PROFILE_DATA *p = CPU_PROFILE_DATA (current_cpu); FRV_CACHE *insn_cache = CPU_INSN_CACHE (current_cpu); FRV_CACHE *data_cache = CPU_DATA_CACHE (current_cpu); int insn_cache_enabled = CACHE_INITIALIZED (insn_cache); int data_cache_enabled = CACHE_INITIALIZED (data_cache); USI hsr0; /* Initialize the register control information first since some of the register values are used in further configuration. */ frv_register_control_init (current_cpu); /* We need to ensure that the caches are initialized even if they are not initially enabled (via commandline) because they can be enabled by software. */ if (! insn_cache_enabled) frv_cache_init (current_cpu, CPU_INSN_CACHE (current_cpu)); if (! data_cache_enabled) frv_cache_init (current_cpu, CPU_DATA_CACHE (current_cpu)); /* Set the default cpu frequency if it has not been set on the command line. */ if (PROFILE_CPU_FREQ (p) == 0) PROFILE_CPU_FREQ (p) = 266000000; /* 266MHz */ /* Allocate one cache line of memory containing the address of the reset register Use the largest of the insn cache line size and the data cache line size. */ { int addr = RSTR_ADDRESS; void *aligned_buffer; int bytes; if (CPU_INSN_CACHE (current_cpu)->line_size > CPU_DATA_CACHE (current_cpu)->line_size) bytes = CPU_INSN_CACHE (current_cpu)->line_size; else bytes = CPU_DATA_CACHE (current_cpu)->line_size; /* 'bytes' is a power of 2. Calculate the starting address of the cache line. */ addr &= ~(bytes - 1); aligned_buffer = zalloc (bytes); /* clear */ sim_core_attach (sd, NULL, 0, access_read_write, 0, addr, bytes, 0, NULL, aligned_buffer); } PROFILE_INFO_CPU_CALLBACK(p) = frv_profile_info; ps->insn_fetch_address = -1; ps->branch_address = -1; cgen_init_accurate_fpu (current_cpu, CGEN_CPU_FPU (current_cpu), frvbf_fpu_error); /* Now perform power-on reset. */ frv_power_on_reset (current_cpu); /* Make sure that HSR0.ICE and HSR0.DCE are set properly. */ hsr0 = GET_HSR0 (); if (insn_cache_enabled) SET_HSR0_ICE (hsr0); else CLEAR_HSR0_ICE (hsr0); if (data_cache_enabled) SET_HSR0_DCE (hsr0); else CLEAR_HSR0_DCE (hsr0); SET_HSR0 (hsr0); }