/**
* save_pll - Copy PLL settings a PLL to memory
*
* This will copy PLL settings from the memory mapped registers for a PLL to
* an array in memory.
*
* Note that: above the PLL exclude PPLL.
*
* pll_id: One of the values from enum plls_id
* src: Pointer to the array of values to save to.
*/
static void save_pll(uint32_t *dst, int pll_id)
{
int i;
for (i = 0; i < PLL_CON_COUNT; i++)
dst[i] = mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, i));
}
static void set_pll_normal_mode(uint32_t pll_id)
{
if (pll_id == PPLL_ID)
mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_NOMAL_MODE);
else
mmio_write_32(CRU_BASE +
CRU_PLL_CON(pll_id, 3), PLL_NOMAL_MODE);
}
static void set_pll_slow_mode(uint32_t pll_id)
{
if (pll_id == PPLL_ID)
mmio_write_32(PMUCRU_BASE + PMUCRU_PPLL_CON(3), PLL_SLOW_MODE);
else
mmio_write_32((CRU_BASE +
CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE);
}
static void set_pll_bypass(uint32_t pll_id)
{
if (pll_id == PPLL_ID)
mmio_write_32(PMUCRU_BASE +
PMUCRU_PPLL_CON(3), PLL_BYPASS_MODE);
else
mmio_write_32(CRU_BASE +
CRU_PLL_CON(pll_id, 3), PLL_BYPASS_MODE);
}
static void pll_suspend_prepare(uint32_t pll_id)
{
int i;
if (pll_id == PPLL_ID)
for (i = 0; i < PLL_CON_COUNT; i++)
slp_data.plls_con[pll_id][i] =
mmio_read_32(PMUCRU_BASE + PMUCRU_PPLL_CON(i));
else
for (i = 0; i < PLL_CON_COUNT; i++)
slp_data.plls_con[pll_id][i] =
mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, i));
}
/**
* restore_pll - Copy PLL settings from memory to a PLL.
*
* This will copy PLL settings from an array in memory to the memory mapped
* registers for a PLL.
*
* Note that: above the PLL exclude PPLL.
*
* pll_id: One of the values from enum plls_id
* src: Pointer to the array of values to restore from
*/
static void restore_pll(int pll_id, uint32_t *src)
{
/* Nice to have PLL off while configuring */
mmio_write_32((CRU_BASE + CRU_PLL_CON(pll_id, 3)), PLL_SLOW_MODE);
mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 0), src[0] | REG_SOC_WMSK);
mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 1), src[1] | REG_SOC_WMSK);
mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 2), src[2]);
mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 4), src[4] | REG_SOC_WMSK);
mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 5), src[5] | REG_SOC_WMSK);
/* Do PLL_CON3 since that will enable things */
mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3), src[3] | REG_SOC_WMSK);
/* Wait for PLL lock done */
while ((mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 2)) &
0x80000000) == 0x0)
;
}
