/* On pcm038 there's a sram attached to CS1, we enable the chipselect here and * setup other stuffs to access the sram. */ static void __init pcm038_init_sram(void) { __raw_writel(0x0000d843, CSCR_U(1)); __raw_writel(0x22252521, CSCR_L(1)); __raw_writel(0x22220a00, CSCR_A(1)); }
int board_init (void) { int i; /* CS0: Nor Flash */ /* * CS0L and CS0A values are from the RedBoot sources by Freescale * and are also equal to those used by Sascha Hauer for the Phytec * i.MX31 board. CS0U is just a slightly optimized hardware default: * the only non-zero field "Wait State Control" is set to half the * default value. */ __REG(CSCR_U(0)) = 0x00000f00; __REG(CSCR_L(0)) = 0x10000D03; __REG(CSCR_A(0)) = 0x00720900; /* setup pins for UART1 */ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); /* SPI2 */ mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B); mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK); mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B); mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI); mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO); mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B); mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B); /* start SPI2 clock */ __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4); /* PBC setup */ /* Enable UART transceivers also reset the Ethernet/external UART */ readw(CS4_BASE + 4); writew(0x8023, CS4_BASE + 4); /* RedBoot also has an empty loop with 100000 iterations here - * clock doesn't run yet */ for (i = 0; i < 100000; i++) ; /* Clear the reset, toggle the LEDs */ writew(0xDF, CS4_BASE + 6); /* clock still doesn't run */ for (i = 0; i < 100000; i++) ; /* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */ readb(CS4_BASE + 8); readb(CS4_BASE + 7); readb(CS4_BASE + 8); readb(CS4_BASE + 7); gd->bd->bi_arch_number = MACH_TYPE_MX31ADS; /* board id for linux */ gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */ return 0; }
int board_early_init_f(void) { #ifdef CONFIG_QONG_FPGA /* CS1: FPGA/Network Controller/GPIO, 16-bit, no DTACK */ static const struct mxc_weimcs cs1 = { /* sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */ CSCR_U(0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 0, 0, 1), /* oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */ CSCR_L(2, 0, 0, 4, 0, 0, 5, 0, 0, 0, 0, 1), /* ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/ CSCR_A(0, 4, 0, 2, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0) }; mxc_setup_weimcs(1, &cs1); /* setup pins for FPGA */ mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO)); mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO)); mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO)); mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO)); mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO)); /* FPGA reset Pin */ /* rstn = 0 */ gpio_direction_output(QONG_FPGA_RST_PIN, 0); /* set interrupt pin as input */ gpio_direction_input(QONG_FPGA_IRQ_PIN); /* FPGA JTAG Interface */ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS6, MUX_CTL_GPIO)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK6, MUX_CTL_GPIO)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_CAPTURE, MUX_CTL_GPIO)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_COMPARE, MUX_CTL_GPIO)); gpio_direction_output(QONG_FPGA_TCK_PIN, 0); gpio_direction_output(QONG_FPGA_TMS_PIN, 0); gpio_direction_output(QONG_FPGA_TDI_PIN, 0); gpio_direction_input(QONG_FPGA_TDO_PIN); #endif /* setup pins for UART1 */ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); /* setup pins for SPI (pmic) */ mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B); mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI); mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO); mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK); mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B); /* Setup pins for USB2 Host */ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_CLK, MUX_CTL_FUNC)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DIR, MUX_CTL_FUNC)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_NXT, MUX_CTL_FUNC)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD3, MUX_CTL_FUNC)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD3, MUX_CTL_FUNC)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK3, MUX_CTL_FUNC)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS3, MUX_CTL_FUNC)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD6, MUX_CTL_FUNC)); mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD6, MUX_CTL_FUNC)); #define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) mx31_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG); mx31_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG); mx31_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG); mx31_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG); mx31_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */ mx31_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */ mx31_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */ mx31_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */ mx31_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */ mx31_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */ mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */ mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */ writel(readl((IOMUXC_BASE + 0x8)) | (1 << 11), IOMUXC_BASE + 0x8); return 0; }
int board_init (void) { /* Chip selects */ /* CS0: Nor Flash #0 - it must be init'ed when executing from DDR */ /* Assumptions: HCLK = 133 MHz, tACC = 130ns */ __REG(CSCR_U(0)) = ((0 << 31) | /* SP */ (0 << 30) | /* WP */ (0 << 28) | /* BCD */ (0 << 24) | /* BCS */ (0 << 22) | /* PSZ */ (0 << 21) | /* PME */ (0 << 20) | /* SYNC */ (0 << 16) | /* DOL */ (3 << 14) | /* CNC */ (21 << 8) | /* WSC */ (0 << 7) | /* EW */ (0 << 4) | /* WWS */ (6 << 0) /* EDC */ ); __REG(CSCR_L(0)) = ((2 << 28) | /* OEA */ (1 << 24) | /* OEN */ (3 << 20) | /* EBWA */ (3 << 16) | /* EBWN */ (1 << 12) | /* CSA */ (1 << 11) | /* EBC */ (5 << 8) | /* DSZ */ (1 << 4) | /* CSN */ (0 << 3) | /* PSR */ (0 << 2) | /* CRE */ (0 << 1) | /* WRAP */ (1 << 0) /* CSEN */ ); __REG(CSCR_A(0)) = ((2 << 28) | /* EBRA */ (1 << 24) | /* EBRN */ (2 << 20) | /* RWA */ (2 << 16) | /* RWN */ (0 << 15) | /* MUM */ (0 << 13) | /* LAH */ (2 << 10) | /* LBN */ (0 << 8) | /* LBA */ (0 << 6) | /* DWW */ (0 << 4) | /* DCT */ (0 << 3) | /* WWU */ (0 << 2) | /* AGE */ (0 << 1) | /* CNC2 */ (0 << 0) /* FCE */ ); #ifdef CONFIG_QONG_FPGA /* CS1: FPGA/Network Controller/GPIO */ /* 16-bit, no DTACK */ __REG(CSCR_U(1)) = 0x00000A01; __REG(CSCR_L(1)) = 0x20040501; __REG(CSCR_A(1)) = 0x04020C00; /* setup pins for FPGA */ mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO)); mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO)); mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO)); mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO)); mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO)); #endif /* setup pins for UART1 */ mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); /* board id for linux */ gd->bd->bi_arch_number = MACH_TYPE_QONG; gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */ return 0; }