CSL_Status GPIO_read (
GPIO_Handle hGpio,
CSL_GpioPinNum pinNum,
Uint16 *buffer
)
{
Uint16 pin;
/* For Invalid handle */
if(NULL == hGpio)
{
return CSL_ESYS_BADHANDLE;
}
/* For Invalid buffer and wrong Pin index */
if((NULL == buffer)||(CSL_GPIO_PIN31 < pinNum)||(pinNum < CSL_GPIO_PIN0))
{
return CSL_ESYS_INVPARAMS;
}
if(pinNum < CSL_GPIO_PIN16)
{
/* Lower Sixteen GPIO Pin - 0 to 15 GPIO pin */
pin = pinNum;
*buffer = CSL_FEXTR (hGpio->baseAddr->IOINDATA1,pin,pin);
}
else
{
/* Upper Sixteen 16 to 31 GPIO Pin */
pin = pinNum - CSL_GPIO_PIN16;
*buffer = CSL_FEXTR (hGpio->baseAddr->IOINDATA2,pin,pin);
}
return CSL_SOK;
}
/**
* @b Description
* @n
* Given the queue handle the function returns the queue manager and queue number within
* the queue manager corresponding to the handle
*
* @param[in] hnd
* Queue handle
*
* @retval
* Queue Manager and Queue Number within the Queue Manager
*/
Qmss_Queue Qmss_getQueueNumber (Qmss_QueueHnd hnd)
{
Qmss_Queue queue;
queue.qMgr = CSL_FEXTR (hnd, 13, 12);
queue.qNum = CSL_FEXTR (hnd, 11, 0);
return (queue);
}
Uint64 getCount(CSL_TmrRegsOvly timer)
{
Uint32 cnt12;
Uint32 cnt34;
Uint64 Count;
cnt12 = (CSL_FEXTR(timer->TIM12, 31,16) << 16) | CSL_FEXTR(timer->TIM12, 15,0) ; //Get Count from TIM12
cnt34 = (CSL_FEXTR(timer->TIM34, 31,16) << 16) | CSL_FEXTR(timer->TIM34, 15,0) ; //Get Count from TIM34
Count = cnt34;
Count = (Count << 32) | cnt12;
return(Count);
}
/** ============================================================================
* @n@b I2C_getConfig
*
* @b Description
* @n Gets the I2C configuration parameters
*
* @b Arguments
* @verbatim
i2cgetConfig I2C Configuration structure pointer
@endverbatim
*
* <b> Return Value </b> CSL_Status
* @li CSL_SOK - Returned for success
* @li CSL_ESYS_INVPARAMS - Invalid parameter
*
* <b> Pre Condition </b>
* @n I2C_config should be called successfully
*
* <b> Post Condition </b>
* @n Populates the I2C config structure
*
* @b Modifies
* @n Structure pointed by getI2cConfig
*
* @b Example
* @verbatim
CSL_Status status;
CSL_I2cConfig i2cConfig;
CSL_I2cConfig i2cgetConfig
i2cConfig.icoar = CSL_I2C_ICOAR_DEFVAL;
i2cConfig.icimr = CSL_I2C_ICIMR_DEFVAL;
i2cConfig.icclkl = CSL_I2C_ICCLK_DEFVAL;
i2cConfig.icclkh = CSL_I2C_ICCLK_DEFVAL;
i2cConfig.iccnt = CSL_I2C_DATA_SIZE;
i2cConfig.icsar = CSL_I2C_ICSAR_DEFVAL;
i2cConfig.icmdr = CSL_I2C_ICMDR_WRITE_DEFVAL;
i2cConfig.icemdr = CSL_I2C_ICEMDR_DEFVAL;
i2cConfig.icpsc = CSL_I2C_ICPSC_DEFVAL;
status = I2C_init(CSL_I2C0);
....
status = I2C_config(&i2cConfig);
....
....
status = I2C_getConfig(&i2cgetConfig);
@endverbatim
* ============================================================================
*/
CSL_Status I2C_getConfig(CSL_I2cConfig *i2cgetConfig)
{
if(i2cgetConfig != NULL)
{
/* Read I2C Own Address register */
i2cgetConfig->icoar = CSL_FEXT(i2cHandle->i2cRegs->ICOAR,
I2C_ICOAR_OADDR);
/* Read I2C interrupt mask register */
i2cgetConfig->icimr = CSL_FEXTR(i2cHandle->i2cRegs->ICIMR,
CSL_I2C_ICIMR_AAS_SHIFT,
CSL_I2C_ICIMR_AL_SHIFT);
/* Read I2C clock low register */
i2cgetConfig->icclkl = CSL_FEXT(i2cHandle->i2cRegs->ICCLKL,
I2C_ICCLKL_ICCL);
/* Read I2C clock high register */
i2cgetConfig->icclkh = CSL_FEXT(i2cHandle->i2cRegs->ICCLKH,
I2C_ICCLKH_ICCH);
/* Read I2C count register */
i2cgetConfig->iccnt = CSL_FEXT(i2cHandle->i2cRegs->ICCNT,
I2C_ICCNT_ICDC);
/* Read I2C slave address register */
i2cgetConfig->icsar = CSL_FEXT(i2cHandle->i2cRegs->ICSAR,
I2C_ICSAR_SADDR);
/* Read I2C mode address register */
i2cgetConfig->icmdr = i2cHandle->i2cRegs->ICMDR;
/* Read I2C extended mode address register */
i2cgetConfig->icemdr = CSL_FEXTR(i2cHandle->i2cRegs->ICEMDR,
CSL_I2C_ICEMDR_IGNACK_SHIFT,
CSL_I2C_ICEMDR_BCM_SHIFT);
/* Read I2C prescaler register */
i2cgetConfig->icpsc = CSL_FEXT(i2cHandle->i2cRegs->ICPSC,
I2C_ICPSC_IPSC);
}
else
{
return(CSL_ESYS_INVPARAMS);
}
return(CSL_SOK);
}
/**
* @b Description
* @n
* This function returns the threshold status of the queue. There are 2 conditions under which the
* threshold bit is set
*
* The threshold bit is set for a queue if the number of element in a queue is above or below
* a certain threshold number of items configured using Qmss_setQueueThreshold() API.
*
* The threshold bit is set for a queue if there is atleast 1 element on the queue when the threshold
* is not set Qmss_setQueueThreshold() API
*
* @param[in] hnd
* Queue handle.
*
* @pre
* Qmss_queueOpen function should be called before calling this function.
*
* @retval
* 0 - Configured threshold is not met
* @retval
* 1 - Configured threshold is met
*/
uint16_t Qmss_getQueueThresholdStatus (Qmss_QueueHnd hnd)
{
uint32_t regIndex, bitField;
regIndex = hnd / 32;
bitField = hnd % 32;
return (uint16_t) CSL_FEXTR (qmssLObj.qmStatusRAM->QUEUE_THRESHOLD_STATUS_REG[regIndex], bitField, bitField);
}
/**
* @b Description
* @n
* The starvation count is incremented every time the Free Descriptor/Buffer
* queue is read when empty. This function returns the starvation count of queue.
*
* @param[in] hnd
* Queue handle.
*
* @pre
* Qmss_queueOpen function should be called before calling this function.
*
* @retval
* 8 bit Starvation count
*/
uint32_t Qmss_getStarvationCount (Qmss_QueueHnd hnd)
{
uint32_t queNum, regIndex, bitField;
queNum = hnd - Qmss_QueueType_STARVATION_COUNTER_QUEUE;
regIndex = queNum / 4;
bitField = (queNum % 4) * 8;
return (uint32_t) CSL_FEXTR (qmssLObj.qmConfigReg->FREE_DESCRIPTOR_STARVE_COUNT_REG[regIndex], bitField + 7, bitField);
}
int GPIO_statusBit (
GPIO_Handle hGpio,
CSL_GpioPinNum pinNum,
CSL_Status *status
)
{
int flagBit;
Uint16 pin;
/* For Invalid handle */
if(NULL == hGpio)
{
*status = CSL_ESYS_BADHANDLE;
return CSL_ESYS_BADHANDLE;
}
/* For wrong pin index */
if((CSL_GPIO_PIN31 < pinNum)||(pinNum < CSL_GPIO_PIN0))
{
*status = CSL_ESYS_INVPARAMS;
return CSL_ESYS_INVPARAMS;
}
if(pinNum < CSL_GPIO_PIN16)
{
/* Lower Sixteen GPIO Pin - 0 to 15 GPIO pin */
pin = pinNum;
flagBit = CSL_FEXTR(hGpio->baseAddr->IOINTFLG1,pin,pin );
}
else
{
/* Upper Sixteen 16 to 31 GPIO Pin */
pin = pinNum - CSL_GPIO_PIN16;
flagBit = CSL_FEXTR(hGpio->baseAddr->IOINTFLG2,pin,pin );
}
*status = CSL_SOK;
return flagBit;
}
